JPS62239216A - Constant current circuit - Google Patents
Constant current circuitInfo
- Publication number
- JPS62239216A JPS62239216A JP61083006A JP8300686A JPS62239216A JP S62239216 A JPS62239216 A JP S62239216A JP 61083006 A JP61083006 A JP 61083006A JP 8300686 A JP8300686 A JP 8300686A JP S62239216 A JPS62239216 A JP S62239216A
- Authority
- JP
- Japan
- Prior art keywords
- field effect
- effect transistor
- constant current
- voltage
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 claims description 31
- 239000004065 semiconductor Substances 0.000 claims description 6
- 230000000694 effects Effects 0.000 abstract description 7
- 229920006395 saturated elastomer Polymers 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 9
- 230000000996 additive effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 101100484930 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) VPS41 gene Proteins 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000000747 cardiac effect Effects 0.000 description 1
- 230000001364 causal effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Landscapes
- Amplifiers (AREA)
- Control Of Electrical Variables (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路における定電流回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a constant current circuit in a semiconductor integrated circuit.
不発面は、半導体集積回路の定電流回搭において、同一
導電型の電界効果塑トランジスタの動作点の差を利用す
る回路”jf:4fl成する事によう、負荷や1源電圧
の変動に対して特性音より安定させたものである。The unexploited aspect is that in the constant current circuit of a semiconductor integrated circuit, a circuit that utilizes the difference in the operating point of field effect plastic transistors of the same conductivity type is constructed. This makes the characteristic sound more stable.
従来の半導体集積回路における定電流回路としては第5
因の回路が代表例としてあげられる。The fifth constant current circuit in conventional semiconductor integrated circuits
A typical example is the causal circuit.
第5図は半導体集積回路におけるオペアンプの定電流源
としてよく用いられる回路である。第5図において、P
チャンネルのトランジスタ1のβをβPム、スレッシホ
ールド電圧k VTPとし、Nチャンネルのトランジス
タ2のβtβN人スレッシホールド電圧k VTNとし
、Nチャンネルのトランジスタ5のβ?βNB1スレシ
ホールドIE圧k VTNとする。また電源電圧t−V
npとし、接地線の電圧2゜とし、Nチャンネルのトラ
ンジスタ3は領和領域で動作するとすれば、負荷4?流
れる電流はよりは下式(1)のようになる。FIG. 5 shows a circuit often used as a constant current source for an operational amplifier in a semiconductor integrated circuit. In Figure 5, P
Let β of channel transistor 1 be βP, threshold voltage kVTP, βtβN threshold voltage kVTN of N-channel transistor 2, β of N-channel transistor 5? Let βNB1 threshold IE pressure kVTN. Also, the power supply voltage t-V
np, the voltage of the ground line is 2°, and the N-channel transistor 3 operates in the sum region, then the load 4? The flowing current is expressed by the following equation (1).
(り式よシ明らかなようにこの回路は負荷変動には無関
係な定電流回路となっている。(As is clear from the formula, this circuit is a constant current circuit that is unrelated to load fluctuations.
第5図の定電流回路はNチャンネルトランジスタ5のゲ
ート電圧?一定にし、Nチャンネルトランジスタ3のド
レイン′J?L流の飽和誤域特性を利用する事により定
電流特性を得ている。Is the constant current circuit in Figure 5 the gate voltage of N-channel transistor 5? The drain 'J? of N-channel transistor 3 is kept constant. Constant current characteristics are obtained by utilizing the saturation error range characteristics of the L current.
しかし、尖細にはドレイン電流はドレイン電圧の変化(
負荷の変mJ)に対し一定とはならず、ドレイン′(圧
の増加にともない、ドレイン電流は増加する。本発明t
よ上記の問題点全解決するもので、負荷や電源電圧の変
動に対して安定な特性を示すという脣似tもった定電流
回路全得る半金目的とする。However, at the tip, the drain current changes as the drain voltage changes (
The drain current does not remain constant as the load changes (mJ), and increases as the drain pressure increases.
The purpose is to solve all of the above problems, and to obtain a constant current circuit that exhibits stable characteristics against fluctuations in load and power supply voltage.
(υ 本発明の定電流回路は
a)第1の電界効果型トランジスタは第2の電界効果型
トランジスタに直列接続され
b) 前記第1の電界効果型トランジスタのゲート電
極は、前記第2の電界効果型トランジスタのゲートJL
極と共通接続され、
C) 前記第2の電界効果型トランジスタのドレイン′
1Jic極は負荷と接続され
d)前記第1の電界効果型トランジスタはドレイン電流
の飽和領域を動作点としてならしめ、前記M2の電界効
果型トランジスタはドレイン電流の旧札娯域紮動作点と
してならしめる。(υ) In the constant current circuit of the present invention, a) the first field effect transistor is connected in series with the second field effect transistor, and b) the gate electrode of the first field effect transistor is connected to the second field effect transistor. Effect transistor gate JL
C) the drain' of the second field effect transistor;
1Jic pole is connected to the load; and d) the first field effect transistor has a drain current saturation region as an operating point, and the M2 field effect transistor has a drain current saturation region as an operating point; Close.
(2) 第1、第2の電界効果型トランジスタの動作
点を得る手段として、前記第1の電界効果型トランジス
タのしきい値電圧Vシ全前記1lfI2の電界効果型ト
ランジスタのしきい値電圧VT、よりも高くならしめる
特許請求の範囲第1項記載の定電流回路のような構成と
し之こと金特徴七する。(2) As a means for obtaining the operating points of the first and second field effect transistors, the threshold voltage V of the first field effect transistor and the threshold voltage VT of the field effect transistor of the 1lfI2 are determined. , the constant current circuit has a configuration similar to that of the constant current circuit described in claim 1, which makes the voltage higher than .
本発明の定電流回路の作用?述べると、いま負荷の変動
により、第2の電界効果型トランジスタのドレイン電圧
が上昇すると、第2の電界効果型トランジスタは飽和領
域で動作するがドレイン電流はわずかに増加する。この
とき第1の電界効果型トランジスタのドレイン電圧も上
昇するが、第1の電界効果型トランジスタのドレイン電
圧の上昇は第2の電界効果型トランジスタのゲートとリ
ース間の電圧を減少させ、第2の電界効果型トランジス
タのドレインを流會減少させる働きをする。Effect of the constant current circuit of the present invention? In other words, when the drain voltage of the second field effect transistor increases due to a load change, the second field effect transistor operates in the saturation region, but the drain current increases slightly. At this time, the drain voltage of the first field effect transistor also increases, but the increase in the drain voltage of the first field effect transistor decreases the voltage between the gate and lease of the second field effect transistor, and It functions to reduce current flow at the drain of a field effect transistor.
この作用全利用し、第1の加昇効果型トランジスタの動
作点を第1、第2の′ル界効果県トランジスタノしきい
(+t VTI e VT、 k VTI > vTt
とする事で飽和領域に設定する事により、非常に安定し
たドレイン電流の飽和特性に得る事ができ、従来よりも
レギュレーション特性の良い定電流回路?得ることがで
きる。Taking full advantage of this effect, the operating point of the first additive effect transistor is set to the first and second additive effect transistor thresholds (+t VTI e VT, k VTI > vTt
By setting it in the saturation region, it is possible to obtain very stable saturation characteristics of the drain current, creating a constant current circuit with better regulation characteristics than conventional ones. Obtainable.
第1図は本発明の1実施例でおる。 FIG. 1 shows one embodiment of the present invention.
第1図はNチャンネルMOEI型電界効果トランジスタ
(以下MosrgT)で構成されているが、Pチャンネ
ルMO8ET’KTにおいても同様な構成が可能である
。Although FIG. 1 is configured with an N-channel MOEI field effect transistor (hereinafter referred to as MosrgT), a similar configuration is also possible with a P-channel MO8ET'KT.
51よ第1の電界効果型トランジスタ(以下FETと記
すンで、52は第2のFKT、4は負荷でVRE)Gは
FET31.EI’′F2T32のゲート電極に与える
基準電圧で、第5図におけるFKTl、FET2のよう
なmffにする事により集積回路内部で与えても良いし
、また集積回路外部より基!!A電圧を与える事も可能
である。51 is the first field effect transistor (hereinafter referred to as FET), 52 is the second FKT, 4 is the load and VRE, and G is the FET 31. The reference voltage applied to the gate electrode of EI''F2T32 can be applied inside the integrated circuit by setting it to mff like FKTl and FET2 in Fig. 5, or it can be applied from outside the integrated circuit. ! It is also possible to apply A voltage.
VBUB¥i基根電位で心根電位11図のようにVSS
と別電源としても良いがV2Oと同電位とする事も可能
である。VBUB\i Fundamental root potential and cardiac root potential VSS as shown in Figure 11
It is possible to use a separate power supply, but it is also possible to use the same potential as V2O.
第2のFET32はドレイン電流の飽和領域で動作させ
るが、負荷4の変動、あるいは電源電圧vDDの変動に
よりドレイン電流が変化しようゆする。このとき、第1
のFKT31のドレイン電圧が変化し、第2のFKTの
ゲート、リース間の電圧が変化し、第2のFITの動作
点が変動し、第2のFF3Tのドレイン電流の変化は抑
制される。The second FET 32 is operated in the drain current saturation region, but the drain current changes due to fluctuations in the load 4 or fluctuations in the power supply voltage vDD. At this time, the first
The drain voltage of the FKT 31 changes, the voltage between the gate and lease of the second FKT changes, the operating point of the second FIT changes, and changes in the drain current of the second FF 3T are suppressed.
本発明では、第10F’m’l’の動作点をドレイン電
流の飽和領域に設定する事により上記の作用をうまく利
用し、より電流特性の安定な定電流回路全構成する事が
出来る。In the present invention, by setting the operating point of the 10th F'm'l' in the saturation region of the drain current, the above-mentioned effect can be effectively utilized, and the entire constant current circuit can be constructed with more stable current characteristics.
第2図は本発明の1実施例である。FIG. 2 shows one embodiment of the present invention.
第2図はNチャンネルMO13FETで構成されている
が、PチャンネルMO81F1!:Tにおいても同様な
構成が可能である。Although FIG. 2 is composed of N-channel MO13FET, P-channel MO81F1! A similar configuration is also possible for :T.
55.54のFl!iT+’l:直列に接続され、その
接続点は51.52のFFXTのゲート電極に接続され
51゜52のFETに基準α圧を与えている。55.54 Fl! iT+'l: Connected in series, the connection point thereof is connected to the gate electrode of FFXT at 51.52, and applies reference α pressure to FET at 51.52.
FTAT55の動作点i FET 51の動作点と同様
に設定すれば、FKT33とFET54の接続点の電位
はVDDの変動に影響されに<<、安定な電位が得られ
、基準電圧として使用でき、外部からの基準電圧の供給
を必要としない。さらにFil:T54の電流増巾率を
過当に設定する事により、温度の変化に対しても非常に
安定な定′!1!流回路を構成する事が可能である。If the operating point i of FTAT55 is set in the same way as the operating point of FET 51, the potential at the connection point of FKT33 and FET54 will not be affected by fluctuations in VDD, and a stable potential will be obtained, which can be used as a reference voltage and can be used as a reference voltage. does not require a reference voltage supply from the Furthermore, by setting the current amplification rate of Fil:T54 to an excessive value, it is extremely stable even when the temperature changes! 1! It is possible to configure a flow circuit.
すなわち、FICT31とF’KT52のドレイン電流
の温度に対する変動t% I#T55とFll:T34
の接続点の電位の温度変化により補償するものである。That is, the variation t% of the drain current of FICT31 and F'KT52 with respect to temperature I#T55 and Fll:T34
This is compensated by temperature changes in the potential at the connection point.
第3図、第4図は本発明の一実施例である。FIGS. 3 and 4 show an embodiment of the present invention.
第31は第1図の実施例と基本的な動作は同一であるが
、基板電位をリース電位と同一電位とし、バックゲート
バイアスによるしきい値の変動tなくしたものである。The 31st embodiment has the same basic operation as the embodiment shown in FIG. 1, but the substrate potential is set to the same potential as the lease potential, and the fluctuation t of the threshold value due to the back gate bias is eliminated.
第4図は第2図の実施例と基本的な動作は同一であるが
、基板電位を各トランジスタの各リース電位と同一にし
、パックゲートバイアスによるしきい値の変動tなくし
たものである。The embodiment shown in FIG. 4 has the same basic operation as the embodiment shown in FIG. 2, but the substrate potential is made the same as each lease potential of each transistor, and the fluctuation t in the threshold value due to the pack gate bias is eliminated.
本発明によれば、同−導電型のトランジスタt2個直列
に接続し、それぞれのトランジスタの動作点を適当だ設
定するような構成とする草によυ従来よりもレギュレー
ションの良い定゛厄流回路金得ることが出来る。また回
路が非常に簡単で、同一4 ′、jl: Wのトランジ
スタを使用するため半導体袋層プロセスへの負担も低減
でき、またコストダウンにも大き71効来がるる。According to the present invention, two transistors of the same conductivity type are connected in series, and the operating point of each transistor is appropriately set. You can get money. In addition, the circuit is very simple, and since the same 4', jl:W transistors are used, the load on the semiconductor bag layer process can be reduced, and the cost can be reduced significantly.
41図−不発明の実施例を示す回路図
第2図一本発明の実施例上水す回路図
第6図一本発明の実施[+lJ k示す回路図第4図−
不発明の実施例勿示す回路図
第2図−従来例を示す回路図
1、2.5.51.32.33.34
・・・・・・電界効果型トランジスタ
4・・・・・・負荷。
以上
ま電う克B路のg苫19
箋lj図
虐肴茨回路1回路t5D
冨2 u
定肴遺8路Q8路回
菓3回
走電−″見回路り回路図
葛+回
従来Q定電j乏lヨ贋トの!回路回
議 51刃Figure 41 - Circuit diagram showing an embodiment of the invention Figure 2 - Circuit diagram showing an embodiment of the invention Fig. 6 - Circuit diagram showing an embodiment of the invention [+lJ k Figure 4 -
Circuit diagram showing an example of the non-inventive example Fig. 2 - Circuit diagram showing a conventional example 1, 2.5.51.32.33.34...Field effect transistor 4...Load . More than that, the circuit diagram of the circuit B is 19, the circuit diagram is 1 circuit, t5D, 2 u, the 8th route is Q8, the circuit diagram is 3 times, and the circuit diagram is 3 times. Electricity is poor and counterfeit! Circuit discussion 51 blades
Claims (2)
トランジスタに直列接続されておりb)前記第1の電界
効果型トランジスタのゲート電極は、前記第2の電界効
果型トランジスタのゲート電極と共通接続されており、 c)前記第2の電界効果型トランジスタのドレイン電極
は負荷と接続されており d)前記第1の電界効果型トランジスタはドレイン電流
の飽和領域を動作点としてならしめ、前記第2の電界効
果型トランジスタはドレイン電極の飽和領域を動作点と
してならしめることを特徴とする定電流回路。(1) In a constant current circuit using a semiconductor integrated circuit device, a) a first field effect transistor is connected in series to a second field effect transistor, and b) a gate electrode of the first field effect transistor. are commonly connected to the gate electrode of the second field effect transistor, c) the drain electrode of the second field effect transistor is connected to a load, and d) the first field effect transistor A constant current circuit characterized in that the second field effect transistor has a drain electrode saturation region as an operating point, and the second field effect transistor has a drain electrode saturation region as an operating point.
得る手段として、前記第1の電界効果型トランジスタの
しきい値電圧V_T_1を前記第2の電界効果型トラン
ジスタのしきい値電圧V_T_2よりも高くならしめる
ことを特徴とする特許請求の範囲第1項記載の定電流回
路。(2) As a means for obtaining the operating points of the first and second field effect transistors, the threshold voltage V_T_1 of the first field effect transistor is set to the threshold voltage V_T_2 of the second field effect transistor. 2. The constant current circuit according to claim 1, wherein the constant current circuit is made to be higher than .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61083006A JPS62239216A (en) | 1986-04-10 | 1986-04-10 | Constant current circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61083006A JPS62239216A (en) | 1986-04-10 | 1986-04-10 | Constant current circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62239216A true JPS62239216A (en) | 1987-10-20 |
Family
ID=13790163
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61083006A Pending JPS62239216A (en) | 1986-04-10 | 1986-04-10 | Constant current circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62239216A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003224437A (en) * | 2002-01-30 | 2003-08-08 | Sanyo Electric Co Ltd | Current drive circuit and display device equipped with the current drive circuit |
WO2010086949A1 (en) * | 2009-01-28 | 2010-08-05 | 学校法人明治大学 | Semiconductor device |
JP2010176680A (en) * | 2010-02-12 | 2010-08-12 | Meiji Univ | Semiconductor device |
-
1986
- 1986-04-10 JP JP61083006A patent/JPS62239216A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003224437A (en) * | 2002-01-30 | 2003-08-08 | Sanyo Electric Co Ltd | Current drive circuit and display device equipped with the current drive circuit |
WO2010086949A1 (en) * | 2009-01-28 | 2010-08-05 | 学校法人明治大学 | Semiconductor device |
JP2010176270A (en) * | 2009-01-28 | 2010-08-12 | Meiji Univ | Semiconductor device |
JP2010176680A (en) * | 2010-02-12 | 2010-08-12 | Meiji Univ | Semiconductor device |
JP4543193B2 (en) * | 2010-02-12 | 2010-09-15 | 学校法人明治大学 | Semiconductor device |
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