JPS5923607A - Bias circuit - Google Patents

Abstract

PURPOSE:To stabilize the bias voltage of a bias circuit composed of a C- MOSFET by forming a semiconductor resistance simultaneously with a P<-> type well area for forming an N channel MOSFET. CONSTITUTION:The bias circuit consists of a P channel MOSFETQ10 and an N channel MOSFETQ11 formed on the same substrate. The FETQ11 is formed in the P<-> type well area and the semiconductor diffused resistance R11 is formed therein simultaneously. Consequently, even if the resistance R11 has an undesirable resistance error, a current I11 flowing through the resistance R11 is made constant. Therefore, a bias voltage VB developed at the connection point between the TRs Q10 and Q11 is stabilized.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bias circuit suitable for use in a differential amplifier configured with MOS transistors.

The differential amplifier configured with MOS transistors shown in FIG. 1 was studied by the present inventor prior to the invention of the present application. The differential amplifier is connected between a pair of P channels (O8)
It consists of transistors Q, , Q, and N-channel MO8) transistors Q, , Q at its output terminal.

A current mirror circuit is provided.

P-channel MQS) transistor Q6 and resistor R1 are:
A bias circuit is constituted, and the resistor R8 is constituted by a semiconductor diffusion layer. Then, the transistor Q6 and the resistor R8
are formed on the same silicon substrate. P-channel MQS) When +vDD power is supplied to the source of transistor Q6, current I flows through resistor R1. A bias voltage V is obtained by the voltage drop at this time, and the bias voltage of the transistor Q between the P channels is determined.

By the way, since the resistor R1 is constituted by a semiconductor diffusion layer, there is an error in its resistance value. Now, if the resistance value of resistor R2 is higher than the desired resistance value, +vD
Since the D power supply is constant, the current l decreases.

According to studies conducted by the inventors of the present invention, it has been found that even if the resistor R1 and the transistor Q6 are formed on the same silicon substrate, an error in the resistor R1 occurs regardless of the characteristics of the transistor Q6. Therefore, if the resistance value of resistor R is large,
When the current 11 decreases, the source-drain voltage of the transistor Q6 decreases and the bias voltage VB increases. The above-mentioned undesired fluctuations in the bias voltage VB appear as fluctuations in the amount of current in the constant current circuit constituted by the transistor Q. This results in a voltage level variation in the output signal of the differential amplifier circuit.

That is, the inventor's study revealed that the bias voltage fluctuates due to an error in the resistor R, which constitutes a part of the bias circuit, and this causes undesired circuit operation.

Therefore, it is an object of the present invention to provide a bias circuit in which the bias voltage does not vary due to the resistance error pressure of a resistor formed of a semiconductor diffusion layer.

An embodiment of the present invention will be described below with reference to FIGS. 2 to 4. Note that the same reference numerals are given to the parts that perform the same circuit operations as those of the differential amplifier shown in FIG. 1, and the explanation thereof will be omitted.

The bias circuit shown in Fig. 2 consists of a CMQS) transistor (
(inverter circuit). CMQ S
(Complementary MQ8) The transistors are KP channel enhancement type MOS transistors Q on the same semiconductor substrate. and an N-channel enhancement WMOS transistor QI+ are connected in cascade. In addition, in the following, for convenience of explanation, the transistor Q will be simply referred to. pQ.

It is written as. The resistor R1I is the transistor Q. .

It is formed on the same semiconductor substrate as Qt+.

The CMQS transistor shown in FIG. 2 has a structure as shown in FIG.

The structure of the CMQS transistor will be described below.

On the N-type silicon substrate 1, as shown in the figure, a transistor Qz
o*Qt+ + resistor R11 is configured. Transistor Q. is a single layer source and drain.

It is composed of a gate (G) that supplies a control voltage. Note that the terminal of G) is connected to the conductive thin film layer 2,
An insulating oxide film (Sin, ) 3 is formed below it. The space between each P+ layer becomes an induced channel, and the charge therebetween is controlled by a control voltage supplied to GK.

Transistor Qll is configured within the P-well region 11. The source S and the drain D are each formed by a layer, and between them is an enhancement layer and an ion implantation layer. The terminal of G) is connected to a conductive thin film layer 12, and an insulating oxide film (S
in, ) 13 is formed.

Resistor R1I is configured within P-well region 21. Then, a CM of the above structure in which a resistor RIl is formed by the semiconductor diffusion resistor between the P layers formed at a predetermined interval.
QS) When configuring a transistor, the P-well layer 11.1
2 are simultaneously formed on the N-type silicon substrate l. As a result, when an undesired error occurs in the resistance value of the resistor R11, the following circuit operation is performed.

For example, assume that the P-type impurity concentration in the P-well regions 11 and 12 is reduced. In this case, the resistance value of the resistor RffiI becomes high. Therefore, the current I11 shown in FIG. 2 tends to decrease.

However, since the P-type well layers 11 and 21 are formed at the same time, when the P-type impurity concentration of the P-well layer 21 is small,
P-well layer 11 changes similarly. Therefore, resistance RI
At the same time as the resistance value of l increases, the P-type impurity concentration decreases, so that the threshold voltage vTH of the transistor Qn decreases.

As a result, transistor Q11 operates to increase current III. Therefore, the current decrease due to the resistor R1° is canceled out, and a constant current 111 always flows. As a result, bias voltage VB is stabilized.

However, the threshold voltage vTH is reduced on the condition that the E implantation dose, that is, the amount of impurity implanted into the Si surface, is not changed.

FIG. 4 shows an example of data obtained when the inventor conducted a circuit experiment. Characteristic A shows the change in current III with respect to the change in resistance Rl1 in this example, and characteristic B shows experimental data conducted by the inventor prior to the invention of the present application.

Comparing characteristics A and B, the current 11 in this example is
It can be seen very clearly how stable the current amount of No. 1 is.

In this way, when the amount of current III becomes stable, transistor Q. The bias voltage vR obtained from the cascade connection position of +QI+ is also stabilized. Therefore, the bias voltage of the MOS transistor Q is stabilized, and the voltage amplification operation by the MOS transistors Q, , Q is also performed extremely stably.

Since the bias circuit configured as described above can absorb errors in the resistance value of the semiconductor diffused resistor, CMQS)
It can be applied to all semiconductor integrated circuits using transistors.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a bias circuit and an amplifier circuit studied by the inventor prior to the invention of the present application, FIG. 2 is a circuit diagram showing a bias circuit and an amplifier circuit showing an embodiment of the present invention, and FIG. 4 is a sectional view of a main part of a semiconductor integrated circuit showing the structure of a bias circuit to which the present invention is applied, and FIG. 4 is a characteristic diagram showing experimental data. Q,,Q,,Q,,Q,,Q,...MOS) transistor, Q+o ・,Q++ ”・0MO8) transistor, RlI...semiconductor diffused resistance, VB...bias voltage. Agent: Patent attorney Usuki 1) Toshiyuki 2 Figure 3 Figure 4 zcKn)

Claims (1)

[Claims] 1. O3 between P channels configured on the same semiconductor substrate
transistor and N-channel MO8) A transistor and at least the N-channel MO configured on the semiconductor substrate;
8) A bias circuit having a semiconductor diffused resistor formed simultaneously with a p-W well region for forming a transistor.