GB2100540A - Reference voltage generators - Google Patents

Reference voltage generators Download PDF

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Publication number
GB2100540A
GB2100540A GB8119561A GB8119561A GB2100540A GB 2100540 A GB2100540 A GB 2100540A GB 8119561 A GB8119561 A GB 8119561A GB 8119561 A GB8119561 A GB 8119561A GB 2100540 A GB2100540 A GB 2100540A
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Prior art keywords
voltage
gate
difference
circuit
reference voltage
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GB8119561A
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GB2100540B (en
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Hitachi Ltd
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Hitachi Ltd
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Priority claimed from JP2544478A external-priority patent/JPS54119653A/en
Priority claimed from JP3554578A external-priority patent/JPS54129348A/en
Priority claimed from JP3924278A external-priority patent/JPS54132753A/en
Priority claimed from JP11172278A external-priority patent/JPS5539411A/en
Priority claimed from JP11172578A external-priority patent/JPS5539413A/en
Priority claimed from JP11172378A external-priority patent/JPS5538677A/en
Priority claimed from JP11172478A external-priority patent/JPS5539412A/en
Priority claimed from JP11171878A external-priority patent/JPS5539606A/en
Priority claimed from JP11171778A external-priority patent/JPS5539605A/en
Priority claimed from JP11172078A external-priority patent/JPS5539608A/en
Priority claimed from JP11171978A external-priority patent/JPS5539607A/en
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to GB8119561A priority Critical patent/GB2100540B/en
Publication of GB2100540A publication Critical patent/GB2100540A/en
Application granted granted Critical
Publication of GB2100540B publication Critical patent/GB2100540B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G05F3/245—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the temperature
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
    • G11C11/4113—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access to base or collector of at least one of said transistors, e.g. via access diodes, access transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
    • H03F3/45748—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using a feedback circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018514—Interface arrangements with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0231—Astable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0233—Bistable circuits
    • H03K3/02337—Bistables with hysteresis, e.g. Schmitt trigger
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45394—Indexing scheme relating to differential amplifiers the AAC of the dif amp comprising FETs whose sources are not coupled, i.e. the AAC being a pseudo-differential amplifier

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  • General Engineering & Computer Science (AREA)
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Abstract

A reference voltage generator comprises a differential amplifier with a negative feedback loop and having an input offset determining the output voltage, this offset being due to the difference in threshold voltages of two IGFETs T1, T2 resulting from the provision of differently doped semiconductor gate electrodes. The output of the amplifier is fed back to the inverting input either directly or via a potential divider and a reference voltage level (eg VSS or VDD) is connected to the non- inverting input. The output voltage is determined (relative to the reference voltage level) by the difference in threshold voltages of the input transistors this difference being substantially independent of temperature variations. <IMAGE>

Description

SPECIFICATION Reference voltage generating device The present invention specifically relates to a reference voltage generating device. Included within the present disclosure are other examples of reference voltage generating devices not within the scope of the present invention, applications of the generating devices, for example to a battery checker, and methods of manufacturing semiconductor generating devices.
In generating reference voltages in various semi-conductor electronic circuits, it is necessary to utilize any physical quantity having the dimension of voltage. For such a physical quantity, only the forward voltage drop VF or reverse breakdown voltage (Zener voltage) Vz of a PN-junction diode, the threshold voltage Vth of an insulated gate field-effect transistor (often represented by an IGFET or MOSFET), have been used.
These physical quantities do not provide voltage values which are fixed absolutely, but their voltage values are subject to fluctuations due to various factors. In order to make use of such physical quantities for the reference voltage generating devices of various electronic circuits, attention must be paid to factors causing fluctuations of the voltage values to be obtained and to the allowable widths of such fluctations.
With reference to the temperature characteristics of the physical quantities, the voltages VF and Vth usually have a temperature-dependency of approximately 2 - 3 mV/ C. The fluctuation of the reference voltage due to the temperature change attains a magnitude such that the application of these quantities in some uses must be abandoned.
For example, when a battery checker to give an alarm when the voltage of a battery has lowered below a predetermined reference value is intended to be used in an electronic timepiece which employs a silver oxide battery having a nominal voltage of 1.5 V, whether the battery voltage is high or low needs to be judged with the boundary (detection level) or the detection reference value at about 1.4 V.
When a reference voltage generating device is to be constructed by exploiting the threshold voltage Vth of a MOSFET or the forward drop voltage VF of a diode which is about 0.6 V, the detection level aimed at 1.4 V has a temperature-dependency of: 1.4V 0.6 V4Vx2 2#33make 467 70make' Accordingly, even when the practical operating temperature range is estimated as narrow as 0 C to 50 C, the detection level fluctuates by as much as 1.23 V to 1.57 V, and a practical battery checker is not achieved.
Also, the physical quantities have variations or deviations in the manufacture. For example, the threshold voltage Vth of a MOSFET has a variation of about +0.2V, which is greater than the temperature fluctuation.
Thus, in the case where such a battery checker is in the form of an iC (integrated circuit) and exploiting the voltage Vth, not only external components and external connection pins (external connection terminals) for adjusting the reference voltage are required but also the labour of adjustment after the fabrication of the IC.
The lower voltage limit of the Zenervoltage V2 is about 3 V, and it is impossible to generate a reference voltage to be used in a low voltage range of about 1 to 3 V. If the Zenervoltage or the forward drop voltage of a diode are used as a reference voltage, a current of the order of several mA to several tens of mA needs to flow, which is inappropriate if it is necessary to minimize the power dissipation of the reference voltage generating device.
Therefore the conventional reference voltage generating devices exploiting the voltages Vth, VF and V2 have not been suited to all the uses when the temperature characteristics, the variations or deviations in manufacture, the power dissipation, the voltage level etc. have been taken into account. For uses requiring very precise tolerances, it has often been necessary to relinquish either the practical use or the advantages of mass production.
Thus it is known that improvements in the conventional reference voltage generating devices are subject to physical limitation.
It is known that semiconductors have energy gaps Eg and various levels such as donor, acceptor and Fermi levels. However, no example has been proposed of a reference voltage generating device with note taken of the physics of semiconductors, especially the energy gap Eg and the Fermi level Ef.
According to the present invention there is provided a reference voltage generating device including: an operational amplifier including first and second insulating gate field-effect transistors (lGFETs) which have a difference of threshold voltages corresponding to a difference of Fermi levels of gate electrodes thereof, both said gate electrodes of said first and second IGFETs being made of an identical semiconductor material but having different conductivity types, a gate of said first IGFET being used as an inverting input of said operational amplifier whilst a gate of said second IGFET is used as a non-inverting input of said operational amplifier, an output terminal for delivering an output signal in response to a potential difference between said inverting and non-inverting inputs, and an input which is offset corresponding to said difference of threshold voltages; a feedback connection means connected between said inverting input and output terminals of said onerational amplifier for applying an output signal at said output terminal of the operational amplifier to said inverting input terminal thereof; and a reference connection means for applying a reference potential to said non-inverting input terminal of the operational amplifier, whereby the reference voltage based on the difference of said threshold voltages of said first and second insulated gate field-effect transistors is derived between said output terminal of said operational amplifier and said reference potential.
The feedback connection means may include a controlling amplifier element having its control electrode which is coupled to said output terminal of said operational amplifier, its first output electrode, which is coupled to a power supply terminal, and its second output electrode which is coupled to said inverting input of said operational amplifier.
The second output electrode of said controlling amplifier element may be coupled to said inverting input of said operational amplifier through a voltage divider which is connected to said output electrode of said controlling amplifier element.
Alternatively, the feedback connection means may include a voltage divider connected between said output terminal of said operational amplifier and said reference potential for applying a divided voltage of the output voltage appearing at said output terminal to said inverting input terminal.
Preferably, said second insulated gate field-effect transistor is of the depletion type.
The operational amplifier may include a third insulated gate field-effect transistor (IGFET) which is commonly coupled in series with drain-source paths of said first and second IGFETs, said third IGFET being driven by a timing signal, whereby during the conductive state of said third IGFET a stabilized output voltage is derived from said output terminal of said operational amplifier.
The reference voltage generator device may additionally include: a first constant current source connected in series with the source-drain path of said first insulated gate field-effect transistor; and a second constant current source connected in series with the source-drain path of said second insulated gate field-effect transistor.
The controlling amplifier element may be a fourth insulated gate field-effect transistor (IGFET).
Alternatively the controlling amplifier element may be a bipolar transistor.
The present invention will now be described, by way of example, with reference to the accompanying drawings, wherein: Figure 1 is a diagram showing the band gaps Eg of GaAs, Si and Ge and theirtemperature-dependence; Figures 2(aJ to 2(d) are diagrams showing the band structures and Fermi levels Ef of semiconductors, in which Figures 2(a) and 2(b) illustrate an example of an N-type semiconductor and Figures 2(c) and 2(d) illustrate an example of a P-type semiconductor; Figure 3 is a diagram showing the temperature characteristics of the Fermi levels of N-type and P-type Si with the impurity density being a parameter;; Figures4(a),4(b) and 4(c) are diagrams showing the distributions of energy levels possessed by Ge, Si and GaAs semiconductors and various donor and acceptor impurities, respectively; Figures 5(al and 5(b) are diagrams showing the energy state and the states of charges of a P±type semiconductor - insulator - N-type semiconductor structure respectively; while Figures 5(c) and 5(d) are diagrams showing the energy state and the states of charges of an N±type semiconductor - insulator N-type semiconductor structure respectively; Figures 6FaJ and 6fbJ are diagrams of the characteristic and circuit of a MOS diode circuit for obtaining the difference of Vth of two FETs having unequal threshold voltages Vth respectively; Figure 7 is a diagram of a characteristic showing the situation in which a threshold voltage is changed by ion implantation; Figures 8 and 9 are diagrams each showing one embodiment of a reference voltage generating circuit which uses the difference of threshold voltages Vth;; Figure 10(a) is a circuit diagram of a reference voltage generating circuit according to an embodiment of the present invention, while Figure 70/by is a diagram of the operating waveform of the circuit in Figure 10(a); Figure 11(a) shows a further embodiment of a reference voltage generating circuit according to the present invention, while Figure 11rub) shows timing signal waveforms of such a circuit; Figure 12 shows another embodiment of reference voltage generating circuit according to the present invention; Figure 13 shows an operational amplifier circuit which has an offset voltage in accordance with the present invention; Figure 14 shows a reference voltage generating circuit which utilizes the operational amplifier circuit of Figure 13; ; Figures 15, 16and 17 show reference voltage generating circuits which utilize operational amplifier circuits according to other embodiments of the present invention; Figures 18 and 19 show voltage detector circuits each of which employs a reference voltage produced from the reference voltage generator circuit according to the present invention; Figure 20 shows a voltage detector circuit which utilizes an operational amplifier circuit having an offset voltage in accordance with the present invention; Figure 21 shows a voltage comparator which is formed by connecting MOSFETs of unequal threshold voltages Vth in the differential type in accordance with the present invention;; Figure 22 shows a differential amplifier circuit which employes MOSFETs of unequal threshold voltages Vth in accordance with the present invention; Figure 23 shows the drain current - versus - gate voltage characteristics of the differential pair MOS transistors of the differential amplifier circuit shown in Figure 22; Figure 24 shows an offset type voltage comparator circuit which is constructed of a voltage comparator circuit and source follower circuits employing two Metal Oxide Semiconductor Field Effect Transistors (herein referred to as MOSFETs) which are a type of IGFET, and have threshold voltages different from each other in accordance with the present invention;; Figure 25 shows an offset type voltage comparator circuit which is constructed of a voltage comparator circuit and grounded-source circuits employing two MOSFETs of threshold voltages different from each other in accordance with the present invention; Figure 26 shows an example of a constant-current circuit which is used in the offset type voltage comparator circuit of Figure 24; Figure 27 shows a reference voltage generating circuit which employs the differential amplifier circuit shown in Figure 22; Figure 28 shows the details of the offset type voltage comparator circuit shown in Figure 24, and illustrates an embodiment where a reference voltage generating circuit is constructed by employing this voltage comparator circuit; Figure 29 shows a constant-current circuit which utilizes the difference of the threshold voltages of two MOSFETs in accordance with the present invention;; Figure 30 shows a constant-current circuit to which is applied a reference voltage generating circuit that produces a reference voltage on the basis of the difference of the threshold voltages of two MOSFETs in accordance with the present invention; Figure 31 shows a constant-current circuit in which a current mirror circuit is added to the constant-current circuit shown in Figure 30; Figures 32 and 33 are circuit diagrams each showing a stabilized power supply circuit to which is applied a reference voltage generating circuit that produces a reference voltage based on the difference of the threshold voltages of MOSFETs in accordance with the present invention; Figure 34 shows a stabilized power supply circuit to which is applied an operational amplifier that has the difference of the threshold voltages of MOSFETs as its offset voltage in accordance with the present invention;; Figure 35(aJ is a circuit diagram showing one embodiment of a voltage regulator circuit to which an offset type operational amplifier circuit according to the present invention is applied, while Figure 35fbJ is a diagram showing an electrical characteristic of such a voltage regulator; Figure 36(at is a circuit diagram showing a voltage regulator circuit according to another embodiment of the present invention, while Figure 366b) is a diagram showing an electrical characteristic of the voltage regulator of Figure 35; Figure 37 is a circuit diagram showing an embodiment of the present invention, as applied to a battery lifetime detector circuit; Figure 38 is a diagram of a circuit for a clock-driven battery checker according to another embodiment of the present invention;; Figure 39 is a diagram of a reference voltage generating circuit whose reference voltage can be finely adjusted with a resistor outside an IC; Figure 40(aJ shows a Schmitt trigger circuit to which the principle of the present invention is applied, while Figure 40fbJ shows the hysteresis characteristic of such a Schmitt trigger circuit; Figure 41 shows a Schmitt trigger circuit according to another embodiment, of the present invention; Figures 42 and 43 are diagrams each showing an oscillator circuit to which the Schmitt trigger circuit according to the present invention is applied; Figure 44 shows a differential amplifier which employs MOSFETs; Figure 45 shows a TTL - MOS signal level shifter circuit according to the present invention; Figure 46 shows a logic threshold stabilizer circuit according to the present invention;; Figure 47 shows a substrate bias generating circuit according to the present invention; Figure 48 shows a status setting circuit according to the present invention; Figure 49 shows a status setting circuit which has previously been proposed; Figure 50 shows a MOS memory which employs the substrate bias generator circuit shown in Figure 47; Figure 51 shows a memory cell in the MOS memory of Figure 50; Figure 52 shows a semiconductor random access memory according to the present invention; Figure 53(at shows a voltage detector circuit which is used in a semiconductor random access memory according to the present invention, while Figure 53(b) shows the operating waveforms of this voltage detector circuit; Figure 54 shows an electronic timepiece to which the battery checker shown in Figure 20 is applied;; Figure 55 shows an electronic timepiece to which a similar battery checker is applied; Figure 56 shows an electronic timepiece to which the voltage regulator as shown in Figure 36(a) is applied; Figure 57 shows an electronic timepiece to which a similar voltage regulator is applied; Figure 58 is a structural sectional view of two MOSFETs which have threshold voltages different from each other in accordance with the present invention; Figure 59 shows schematically sectional structures of p+ gate and N+ gate MOSFETs usable for deriving the difference (Efn - Efp) of the Fermi levels of N-type and P-type semiconductors, in which the left half shows a a P-channel FET while the right half shows an N-channel FET;; Figure 60 also shows schematically sectional structures of pe gate and N+ gate MOSFETs usable for deriving the difference (Efn - Efp) of the Fermi levels of N-type and P-type semiconductors, in which the left half shows a P-channel FET while the right half shows an N-channel FET; Figure 61 similarly shows a structure of two P-channel MOSFETs which have threshold voltages different from each other; Figures 62 and 63 are sectional views each showing the essential portions of MOSFETs which are required for the construction of the present invention and which have gate electrodes of different Fermi levels; Figure 64 is a sectional view of the essential portions of MOSFETs which constitute a reference voltage generating device according to the present invention;; Figures 65raJ and 65{by are plan view and a sectional view respectively of an N+ gate P-channel MOSFET, the sectional view being taken along lines indicated by arrows in the corresponding plan view; Figures 66raJ and 66raj are a plan view and a sectional view of a P+ gate P-channel MOSFET, respectively; Figures 67hay and 67fbJ show a plan view and a sectional view of a P+ gate P-channel MOSFET, respectively; Figures 68RaJ and 68FbJ show a plan view and a sectional view of an igate P-channel MOSFET, respectively; Figures 69hay and 69/by show a plan view and a sectional view of an N+ gate P-channel MOSFET, respectively;; Figures 70raJ and 70fbJ show a plan view and a sectional view of an N+ gate N-channel MOSFET, respectively; Figures 71(at and 71raj show a plan view and a sectional view of an igate N-channel MOSFET, respectively; Figures 72/at and 72{by show a plan view and a sectional view of a P+ gate N-channel MOSFET, respectively; Figures 73(aJ to 73(fJ illustrate that N+ gate (part B) and P+ gate (part A) P-channel MOSFETs are fabricated together with a P-channel FET (part C) and an N-channel FET (part D) which constitute a conventional complementary MOS device;; Figures 74(aJ to 74/do, Figures 75(aJ to 75(d), Figures 76raJ to 76fdJ and Figures 77hay to 77/do show sectional view in the principal steps of manufacture of two MOSFETs according to the present invention together with a complementary MOS device, respectively; Figures 78RaJ to 78bet show sectional views in the various steps of the manufacture of N-channel MOSFETs;; Figures 79bat to 79hex, Figures 80bat to 80/do and Figures 81/awl to 87/do are sectional views showing various steps in a method of manufacturing MOSFETs for use in a reference voltage generating circuit device according to the present invention, respectively; and Figures 82(a) and 82fbJ and Figures 83(at to 83/do show sectional views of various steps of another method of manufacturing MOSFETs for use in a reference voltage generating circuit device according to the present invention, respectively.
The physics of semiconductors which begins with the crystalline structure of a semiconductor and which develops into the energy band theory of a semiconductor and phenomena brought about in semiconductors by donor and acceptor impurities is explained in numerous texts.
It is, well known that semiconductors of different compositions have inherent energy gaps Eg and that the energy gap Eg expressed in eV has the dimension of voltage. However, there has not been any example of its use as a reference voltage source, from observations of the fact that the semiconductor has an inherent energy gap Eg and that it exhibits a low temperature-dependence.
The present invention has been made by starting from the fundamentals of the physics of semiconductors.
Therefore, the detailed description of this invention will begin with the principle features by firstly referring to the physics of semiconductors. Since the material properties of semiconductors are explained in detail in many texts they will now be briefly described with the aid of one of the texts, "Physics of Semiconductor Devices" by S.M. SZE, published by John Wiley & Sons in 1969, especially Chapter 2 "Physics and Properties of Semiconductors" on pages 11 and 65.
There are various compositions of semiconductors. Among them, typical as semiconductors industrially utilized at present, are non-compound semiconductors of germanium (Ge) or silicon (Si), and galliumarsenic (GaAs) compound semiconductors. The relations between the energy gaps Eg of these semiconductors and the temperature are explained on page 24 of the cited text and are reprinted in Figure 1.
As seen from Figure 1, the energy gaps Eg of Ge, Si and GaAs are 0.80 1.12eV and 1.43 eV at the normal temperature normal temperature (300 K) respectively. Theirtemperature-dependencies are 0.39 meV K-1, 0.24 meV K-1 and 0.43 meV K-1, respectively. By obtaining voltages having values equivalent to or close to the energy gaps Eg, reference voltage gererating devices are obtained which have a temperaturedependence one order smaller than those of the forward voltage drop VF of a PN-junction diode and the threshold voltage Vth of an IGFET as described previously. Furthermore, the voltage obtained is determined by the energy gap Eg inherent to the semiconductor.With, for example, Si, it is determined to be about 1.12 V at the normal temperature substantially independent of the other factors. It is possible to obtain a reference voltage which is not affected by variations in the manufacturing conditions etc.
The states of energy levels in the case of doping semiconductors with donor and acceptor impurities are well known. A feature necessary to the present invention is the phenomenon that the energy levels at which the Fermi energies of N-type and P-type semiconductors are located are separated towards a conduction band and towards a valence band with respect to the Fermi energy level Ej of an intrinsic semiconductor. As the densities of the acceptor and donor impurities gets higher, there is a tendency for the energy levels to become more distant from the Fermi level E; of the intrinsic semiconductor. Hence, the Fermi level Efp of the P-type semiconductor comes close to the top Ev of the valence band, while the Fermi level Efn of the N-type semiconductor comes close to the bottom Ec of the conduction band.Thus, when the difference (Efn - Efp) of both the Fermi levels is taken, the energy level difference is approximate to the energy gap Eg possessed by the semiconductor and its temperature-dependence is also approximate to that of the energy gap Eg. This also applies to the differences (Efn - E;) and (Ej - Efp) between the Fermi levels of the P-type semiconductor and the intrinsic semiconductor and between the Fermi levels of the N-type semiconductor and the intrinsic semiconductor. In this case, however, the absolute value approaches Eg/2. The differences relative to the intrinsic semiconductor will not be described in detail because they are a half of the difference between the P-type and the N-type. As will be described in detail later, the higher the impurity concentration, the lower the temperature-dependency of (Efn - Efp).In order to attain a large energy level difference of approximately the energy gap Eg and to attain a low temperature-dependency, it is advantageous to obtain an impurity density as close to the saturation density as possible.
The position of the Fermi levels Efn and Efp involves not only the density of the donor or acceptor impurity but also the donor or acceptor levels Ed or Eal which differ depending upon impurity material. The nearer the energy level Ed or Ea approaches the conduction band or the valence band respectively, the nearer the Fermi level Efd or Efa comes to one or other. Thus, as the impurity levels Ed and Ea of the donor and acceptor have shallower levels, the difference (Efn - Efp) of the Fermi levels approaches the energy gap Eg of the semiconductor.
As the impurity level Ed or Ea of the donor or acceptor is closer to the Fermi level Ej of the intrinsic semiconductor, that is, as it has a deeper level, the difference (Efn - Efp) of the Fermi levels becomes increasingly different from the energy gap Eg of the semiconductor. This, however, does not mean that the temperature-dependence degrades, but means that the absolute value of the difference (Efn - Efp) of the Fermi levels diminishes. Therefore, the difference (Efn - Efp) of the Fermi levels or the difference of work functions is a physical quantity inherent to the semiconductor material, the impurity materials, etc. From another viewpoint, it can become a reference voltage source parallel or similar to, the energy gap Eg of the semiconductor.Thus, the difference (Efn - Efp) of the Fermi levels can become a reference voltage source which has a lower temperature-dependence and is less liable to be affected by the manufacturing conditions than the forward voltage drop VF of a PN-junction or the threshold voltage Vth of an IGFET. Therefore, by obtaining the difference (Efn - Efp) of the Fermi levels by the use of impurity materials exhibiting donor and acceptor levels Ed and Ea having shallow levels, it is possible to obtain a voltage with a value approximately that of the energy gap Eg of the semiconductor.Also, as regards the setting of a voltage value to be obtained, in the case of intending to attain a comparatively large reference voltage equivalent to the energy gap of the semiconductor, impurities which exhibit shallow levels may be used, and in the case of intending to attain a comparatively small reference voltage, impurities which exhibit deep levels may be used.
The relations between the Fermi level Ef and the donor level Ed, acceptor level Eal donor density Nd, acceptor density Na and the temperature T will now be described in more detail with reference to Figure 2 and Figure 3. Prior to this description, data on page 30 of the cited text and reprinted in Figure 4 will be referred to in order to explain what levels various impurities have in Ge, Si and GaAs semiconductors and to explain how the impurities are utilized in this invention.
Figures 4(a), 4(b) and 4(c) are diagrams which show the energy distributions of various impurities for Ge, Si and GaAs, respectively. In the respective diagrams the numerals indicate energy differences (Ec - Ed) from the bottom Ec of a conduction band to levels located above the center of the energy gap, the Fermi level of an intrinsic semiconductor Ej, shown by the broken line, and energy differences (Ea - Ev) from the top Ev of a valence band to levels located below the gap center Ej, the unit being eV in both cases.
Thus, an impurity material indicated by a small numerical value in each diagram has its level close to the bottom Ec of the conduction band or the top Ev of the valence band, and it is appropriate as an impurity for obtaining a voltage close to the energy gap Eg. For example, for Si which is used most frequently at present, level differences (Ec - Ed) and (Ea - Ev) respectively exhibited by the donor impurities of Li, Sb, P, As and Bi and the acceptor impurities of B, Al and Ga are the smallest, and both the level differences are below about 6% of the energy gap Eg of Si. If differences of temperature from 0 K are ignored, the difference (Efd - Elf0) of the Fermi levels of N-type Si and P-type Si employing these impurities becomes about 94% to 97% of the energy gap Eg of Si, a value approximately equal to Eg. A donor impurity and an acceptor impurity which exhibit the smallest level differences (Ec - Ed) and (Ea - Ev) after the above impurities are S (about 16% of Eg) and In (about 14% of Eg), respectively. The difference (Efd - Efa) of the Fermi levels of N-type Si and P-type Si employing the respective impurities becomes about 0.85 Eg at O K, and the deviation from the energy gap Eg of Si is as great as about 15%.Thus, the deviation is much greater than those of the impurities mentioned earlier.
Thus, one donor impurity selected from the group consisting of Li, Sb, P, As and Bi and one acceptor impurity selected from the group consisting of B, Al and Ga are suitable as the impurity materials of P-type and N-type Si for obtaining a voltage substantially equal to the energy gap Eg of Si. The other impurities can be used when it is necessary to obtain voltages considerably smaller than the energy gap Eg of Si.
The difference (Efn - Efp) of Fermi levels will be explained from the physical properties of the materials with reference to Figures 2(a) to 2(d). These Figures are diagrams illustrating the energy levels of semiconductors.
Figures 2(a) and 2(b) show the energy level model and the temperature characteristic, respectively, of an N-type semiconductor while Figures 2(c) and 2(d) show the energy level model and the temperature characteristic of a P-type semiconductor.
Carriers in a semiconductor consist of both electrons nd created by ionization of donor impurities Nd and electron-hole pairs excited from a valence band. When the donor impurity density Nd is sufficiently high, the number of the excited electron-hole pairs is negligible, and the number of conduction electrons, n is given by the equation: n=nd (1) nd and n are respectively evaluated from the probability at which electrons are trapped by the donor level and the number of electrons which exist in a conduction band, and have values given by the equations:
=Nd (2) If exp (EF - and n=Ncexp(EF#4Ec ) ..... (3) Here, the effective density of states in the conduction band, Nc is given by the equation::
where his Planck's constant, m*is the effective mass of electron, k is Boltzmann's constant, and T is the lattice temperature. From Equations (1), (2) and (3),
and Nd = exp (EF E, ) + exp (2 EF EkTd - Ec ..... (5) Nc = exp kT Since the Fermi level is supposed to lie near to the bottom of the conduction band Ec, the first term of Equation (5) is negligible, so that the following equation is obtained.
i EF = 1/2 (Ed + Ec) - 1/2 kT~ ..... (s) Nd It can be seen from this equation that, in the case where the impurity concentration density Nd is high, not only at a low temperature, but also at the normal temperature, NC/Nd approximates to one and Ne n Nd tends to zero so that the Fermi level EF lies at the intermediate point between the bottom Ec of the conduction band and the donor level Ed and the temperature-dependence becomes substantially equal to the temperature characteristic of Ec.
However, in the case where the temperature has become sufficiently high, the electron-hole pairs excited from the valence band are predominant, the influences of the impurities lessen and the Fermi level EFn in the N-type semiconductor approaches the level Ej of the intrinsic semiconductor. This relationship is illustrated in Figure 2(b).
This also applies to the case of a P-type semiconductor containing only an acceptor impurity, as shown in Figure 2(c). When the temperature is low and the acceptor impurity density is high, the Fermi level EFP in the P-type semiconductor lies at a substantially intermediate position between the top Ev of the valence band and the acceptor level Ea. When the temperature rises, it approaches the Fermi level Ej of the intrinsic semiconductor.
The temperature-dependence of the Fermi level EFp in the P-type semiconductor is illustrated in Figure 2(d).
The relations between the temperature-dependence of the Fermi levels Efp and Efn and the impurity densities have been explained on physical properties. Now, by taking as an example the Si semiconductor which is used most frequently in practice at this present time, the difference of the Fermi levels (Efn - Efp) and its temperature-dependence in practical use will now be discussed with reference to data on page 37 of the cited text. The data are reprinted in Figure 3.
In conventional processes for manufacturing a Si semiconductor integrated circuit, only boron B and phosphorus Pare used as impurity materials. Their high impurity densities are 1020 atoms cm~3. However, even when the donor and acceptor impurity densities Nd and Na are made 1018 atoms cm-3 which is lower by two orders, the difference (Efn - Efp) of the Fermi levels of the N-type semiconductor and the P-type semiconductor is 0.5 - (-0.5) = 1.0 eV at 300 K as can be seen from Figure 3, and it is a value comparatively close to the energy gap Eg ~ 1.1 eV at the same temperature.The changes of this difference with temperatures are from about 1.04 eV to 0.86 eV in a range of from 200 Kto 400 K (-700C to 130 C), and the rate of change is 0.9 mV K-l. This is a small value of approximately a third in comparison with 2 to 3 mV K-1, the rates of change with temperatures of the threshold voltage Vth of an IGFET and the forward drop voltage VF of a diode as stated previously.
When the impurity densities are 1020 cm-3 or higher, the Fermi level difference becomes substantially equal to the silicon energy gap (Eg)si = 1.1 eV, and the changing rate versus temperatures becomes about 0.2 mV K-1 which is a sufficiently small value.
Thus, if the impurity concentrations are about 1013cm-3 or higher, a temperature-dependence which is reduced to at least a half to a third of those of the prior art can be attained. Preferably, the impurity concentrations are 1 020cm-3 or higher, and most preferably, they are the saturation densities or degenerate densities.
One method of obtaining the voltage corresponding to the difference of the Fermi levels (Efn - Efp), (Efn Ej) is to utilize the difference of the threshold voltages Vth of two MOSFETs with channels of the same conductivity type which have semiconductor gate electrodes that are formed on gate insulating films formed under substantially the same conditions on different surface areas of an identical semiconductor body and that are made of materials being of an identical semiconductor substance (for example, silicon) but having different conductivity types.
Each of Figures 59 and 60 depicts conceptually the sectional structures of the respective FETs formed within a complementary MOS integrated circuit (CMOSIC). For the sake of brevity, the MOS transistor whose gate electrode is made of a P±type semiconductor shall be called the "P+ gate MOS", the MOS transistor whose gate electrode is made of an N±type semiconductor shall be called the "N+ gate MOS", and the MOS transistor whose gate electrode is made of an intrinsic or i-type semiconductor shall be called the "i gate MOS". In Figure 60, the left half shows P+, i and N+ gate P-channel MOS transistors, while the right half shows P+, iand N+ gate N-channel MOS transistors.
The differences of threshold voltages among the MOSFETs, (Q1) - (Q3) and (Q4- (Qe) in Figure 60, take values as shown in the following table: TABLE (Unit: volt) Q1 Q2 Q3 Q4 Q5 Of Q, 0.55 1.1 - - Q2 0.55 0.55 - - - Q3 1.1 0.55 - - - Q4 - - - 0.55 1.1 Of - - - 0.55 0.55 Of - - - 1.1 0.55 As will be described in detail later, Figures 73(a) to 73(f) illustrate sectional views of the principal steps which indicate that the P+ gate MOS and the N+ gate MOS can be fabricated without altering or adding any step of a conventional process for manufacturing a complementary MOS integrated circuit (CMOS IC).
Figures 65(a) and 65(b) or Figures 66(a) and 66(b) depict a plan view and a sectional structural view respectively of N+ gate or P+ gate P-channel MOS transistors to be actually used in circuit structures.
Referring to Figures 65(a) and 65(b) or Figures 66(a) and 66(b), in order to form a self-alignment structure, a P-type impurity is diffused in both those end parts Es and ED of the gate electrode G formed of an i-type or intrinsic semiconductor which are close to a source S and a drain D, for both the P+ gate MOS and the N+ gate MOS because the MOS transistor has the P-channel in this example. In a central part Cp of the gate electrode G, a P-type impurity is diffused for the P+ gate MOS, and an N-type impurity is diffused for the N+ gate MOS. A region i in which no impurity is diffused is provided between the central region and both the end parts Es and ED close to the source and the drain.Thus, the difference between the P+ gate MOS and the N+ gate MOS is only whether the region of the central region part Cp of the gate is of P-type semiconductor or N-type semiconductor.
Shown in Figures 65(a) and 65(b) or Figures 66(a) and 66(b), is an N- silicon substrate 101, a P+ source region 108, a P+ drain region 113, a gate oxide film 105, a thick field oxide film 108, and another oxide film 111. As is clear from Figures 65(a) or Figure 66(a), a plurality of P+ source regions 108 are electrically connected to one another by an interconnection layer 114, a plurality of P+ drain regions 113 are electrically connected to each other by an interconnection layer 112, and a plurality of gate electrodes G are electrically connected to one another by an interconnection layer 115.
In order to reduce the variation of the effective channel lengths of the MOS transistors, due to the fact that the P-type impurity diffused regions at both the end parts Es and ED of the gate electrodes G, formed for the self-alignment, shift to either the left or right side (source side or drain side) during manufacture because of an error in mask alignment, the columns of the source regions and the drain regions are alternately arranged, and the columns are arranged so that the left half and the right half may be put into a linear symmetry with respect to the channel direction as a whole.Thus, even when the shifting of the mask alignment with respect to the channel direction (leftward or rightward shifting) changes the effective channel lengths of the FETs in the respective columns, the average effective channel lengths of the P+ gate MOS and the N+ gate MOS in the respective columns connected in parallel have the changes cancelled out overall and become substantially constant.
Figures 73(a) to 73(f) illustrate how the P+ gate MOS and the N+ gate MOS are constructed by the use of the conventional manufacturing process for a silicon gate CMOS IC.
In Figure 73(a) is shown an N-type silicon semiconductor 101 having a resistivity of 1 Qcm to 8 Qcm, on which a thermal oxidation film 102 is grown to a thickness of about 4,000 A to 16,000 A. In an area of the film, a a window for selective diffusion is provided by the photoetching technique. Boron, to serve as a P-type impurity, is non-implanted in a quantity of approximately 1011 to 10'3 cm at energy of 50 keV to 200 keV, and is thermally diffused for about 8 to 20 hours, to form a P- well region 103 which serves as a substrate of an N-channel MOS transistor.
In Figure 73(b), the thermal oxidation film 102 is entirely removed, a new thermal oxidation film 104 is formed about 1 lim to 2 Fm, and a region of this film corresponding to the source, drain and gate of the MOS transistor is removed by etching. Then, a gate oxide film 105 which is about 300 A to 1,500 A thick is formed.
On the resultant substrate, polycrystalline Si 106 being of i-type, or intrinsic semiconductor, is grown to a thickness of about 2,000 A to 6,000 . By etching, it is removed with the gate part G of the MOS transistor left behind.
In Figure 73(c), a mask oxide film 107 is formed by vapour growth, and its regions under which a P-type impurity is to be diffused are removed by the photoetching technique. Subsequently, boron, being the P-type impurity, is diffused at a high density of about 1020 to 1021 cm-3 to form a source region 108 and a drain region 113 of the P-channel MOS transistor and simultaneously to form a gate electrode of P-type semiconductor.
In Figure 73(d), as in the foregoing, a mask oxide film 109 is formed by vapour growth, and its regions under which an N-type impurity is to be diffused are removed by the photoetching technique. Then, phosphorus, being the N-type impurity, is diffused at a high density of about 1020 to 1021 cm-3,toform a source region 110 and a drain region 116 of the N-channel MOS transistor and simultaneously to form a gate electrode of an N-type semiconductor.
In Figure 73(e), the oxide film 109 is removed. An oxide film 111 which is approximately 4,000 A to 8,000 A thick is formed by vapour growth, and its region corresponding to an electrode leading-out portion is removed by the photoetching technique. Thereafter, a metal (Aluminium) is evaporated, and an electrode interconnection portion 112 is formed by the photoetching technique.
In Figure 73(f), the resultant substrate is covered with an oxide film being 1 m to 2 m thick by vapour growth.
The threshold voltage of the MOS transistor employing the semiconductor for the gate electrode will be described with reference to Figures 5(a) to 5(d). First, in the case of the P+ gate MOS, the energy band diagram of Figure 5(a) shows that the following equation holds; ~qVG + q #FP + + Eg/2 + q ?e = q Vo + q #,f
#MP+ + q X + E9/2 - Q ~B .....
#si where VG is the potential difference between a semiconductor substrate and a gate electrode (P+ semiconductor), X is the electron affinity, Eg is the energy gap, ~srf is the surface potential of an N-type semiconductor substrate, ~FP is the Fermi potential of a P-type semiconductor with reference to the Fermi potential of an intrinsic semiconductor, ~B is the Fermi potential of the N-type semiconductor substrate with reference to the Fermi potential of the intrinsic semiconductor, q is the unit charge of electron, Vo is the potential difference applied to an insulator, Ec is the bottom of a conduction band, Ev is the top of a valence band, Ej is the Fermi level of the intrinsic semiconductor.
In Equation (7), the work function of the gate electrode is denoted as ~MP+ and the work function of the semiconductor is similarly denoted as pass. Then, ~MP = X + Eg/2q + ~FP ..... (8) ~si = X + Eg/2Q - prF ..... (9) Therefore, VO= Vc + ~MP +~~Si~~SrF ..... (10) From the relation of charges in Figure 5(b), -Cox.Vo + Qss + Q1 + QB = ..... (11) where Cox is the capacitance of the insulator per unit area, Qss are the fixed charges in the insulator, QB are the fixed charges due to ionization of impurities in the semiconductor substrate, Oi are carriers formed as a channel.
From (10) and (11), -Cox (-VG + ~MP + - - ~Srf) + + Qss +0+ QD =0 (12 The gate voltage VG at the time when the channel Qj is formed is the threshold voltage. Therefore, letting Vthp + denote the threshold voltage of the P+ gate MOS, Vthp += VG|a=o = ~MP + - #Si - #Srf -OSS/COX -QD/COX ..... (13) At this time, ~Srf = 2 ~F- Similarly, in the N+ gate MOS transistor, only the work function ~MN+ of the gate electrode differs, as shown in the following equation: ~MN + = X + Eq/2q + ~FN (14) Hence, the threshold voltage VthN+ of the N+ gate MOS is given by the equation:: VthN+ = ~MN + - - ~Srf -Oss/Cox - QD/COX (15) where ~Srf = 2 BF Thus, the difference VthP+ - VthN+ of the threshold voltages of the P+ gate MOS and the N+ gate MOS is given by the equation VthP+ - VthN+ = ~MP - #MN+ = ~FP - BN+ (16) which is equal to the difference of the Fermi potentials of the semiconductors making up the gate electrodes.
This can be seen from comparison of Figures 5(a) and 5(c) since the gate voltage at the time when the same charge profile is established is equal to the difference of the work functions of the gate electrodes and the difference of the Fermi levels.
While the above description has been made by taking the P--channel MOS transistor as an example, the same applies to the case of the N±channel MOS transistor.
From the above description, it is clear that a voltage substantially equal to the energy gap Eg can be derived from the difference of the threshold voltages of the P+ gate MOS and the N+ gate MOS.
Alternatively, the voltage of the energy gap Eg can be derived from the difference of the threshold voltage of a MOS whose gate electrode is made of an intrinsic semiconductor (hereinafter referred to as the "i gate MOS") and the threshold voltage of the P+ gate MOS or the N+ gate MOS.
Letting Vthi denote the threshold voltage of the gate MOS, since the Fermi level of the intrinsic semiconductor is 0 (zero) (as the Fermi level of the intrinsic semiconductor is made the reference), the difference of the threshold voltages of the igate MOS and the P+ gate MOS is given by the equation: |Vthi -VthP+I = 10 - #FP+I =. 1/2 Eg ----- (17) The difference of the threshold voltages of the i gate MOS and the N+ gate MOS is given by the equation: IVthi - VthN+I = I#FN+ - |~FN ~ 0~. 1/2 Eg ----- (18) It is clear that the differences provide a voltage of half of the energy gap Eg.
The voltage which is obtained owing to the difference of the threshold voltages of the i gate MOS and the P+ gate or N+ gate MOS is very useful in that it is approximately 0.55 V and suitable for a low reference voltage source, and hence, a reference voltage source of high precision is easily obtained, not only by the manufacturing process of the CMOS integrated circuit, but also by the manufacturing process of single-channel MOS integrated circuit because the doping of gate electrodes with an impurity can be carried out in one step.
Figures 67(a) and 67(b) to Figures 72(a) and 72(b) depict plan patterns and sectional structures along lines A - A in the plan patterns, of P+ gate, i gate and N+ gate P-channel and N-channel MOS transistors respectively, to be used in circuit structures.
In the figures, similarly to the examples of Figures 65(a) and 65(b) or Figures 66(a) and 66(b), P- or N-type regions of a source and a drain are formed by the diffusion of an impurity by employing polycrystalline Si for a mask. In order to allow a margin for the mask alignment between the mask for selectively diffusing a P-type impurity or an N-type impurity and the source and drain regions, the same impurity as that of the source and drain regions is diffused in both end parts Es and ED of a gate electrode G adjoining the source S and drain D in both the P+ gate MOS and the N+ gate MOS, In, for example, the P-channel MOS, boron, which is the P-type impurity, is diffused. In a central part of the gate electrode, a P-type impurity is diffused for the P+ gate MOS, and an N-type impurity is diffused for the N+ gate MOS.
Figures 67(a) and 67(b), Figures 68(a) and 68(b) and Figures 69(a) and 69(b) represent plan views and sectional views of P-channel MOS transistors of the P+ gate, igate and N+ gate, respectively, while Figures 70(a) and 70(b), Figures 71 (a) and 71 (b) and Figures 72(a) and 72(b) represent N-channel MOS transistors of the N+ gate, igate and P+ gate, respectively.
In Figures 67(a) and 67(b) to Figures 72(a) and 72(b), in order to reduce the variation of the effective channel lengths of the MOS transistors due to the fact that those regions at both the end parts Es and ED of the gate electrodes G which are formed for the self-alignment and in which the same impurity as that of the source and drain regions is diffused, shift to either the left or right side (source side or drain side) during manufacture because of an error in the mask alignment, the columns of the source regions and the drain regions are alternately arranged, and the columns are arranged so that the left half and the right half may be put into a line symmetry with respect to the channel direction as a whole.Thus, even when the shifting of the mask alignment with respect to the channel direction (leftward or rightward shifting) changes the effective channel lengths of the FETs in the respective columns, the average effective channel lengths of the P+ gate MOS, i gate MOS and the N+ gate MOS in the respective columns connected in parallel have the changes cancelled out overall and become substantially constant.
Figures 74(a) to 74(d) illustrate how the P+ gate MOS and the N+ gate MOS are constructed by the use of conventional silicon gate CMOS manufacturing process.
In Figure 74(a) is shown an N-type silicon semiconductor having a resistivity of 1 Qcm to 8Qcm, on which a thermal oxidation film 102 is grown to a thickness of about 4,000 A - 16,000 A. In an area of the film, a window for selective diffusion is provided by the photoetching technique. Boron to serve as a P-type impurity is ion-implanted in a quantity of approximately 1011#1013 cm-' at energy of 50 keVto 200 keV, whereupon it is thermally diffused for about 8 to 20 hours, thereby to form a P well region 103 which serves as a substrate of an N-channel MOS transistor.
In Figure 74(b), the thermal oxidation film 102 is entirely removed, a new thermal oxidation film 104 is formed about 1 Fm to 2ism, and a region of this film corresponding to the source, drain and gate of the MOS transistor is removed by etching. Thereafter, a gate oxide film 105 which is about 300 A - 1,500 A thick is formed. On the resultant substrate, polycrystalline Si 106 being of the i-type or intrinsic semiconductor is grown to a thickness of 2,000 A - 6,000 A. By etching, it is removed with the gate part G of the MOS transistor left behind.
In Figure 74(c), a mask oxide film 107 is formed by vapour growth, and its regions under which a P-type impurity is to be diffused are removed by the photoetching technique. Subsequently, boron to become the P-type impurity, is diffused at a high density of about 1020 to 1021 cm#3, to form a source region 108 and a drain region 113 of the P-channel MOS transistor and simultaneously to form a gate electrode of a P-type semiconductor.
In Figure 74(d), as in the foregoing, a mask oxide film 109 is formed by vapour growth, and its regions under which an N-type impurity is to be diffused are removed by the photoetching technique. Then, phosphorus to become the N-type impurity at a high concentration of about 1020 - 1021 cm-3 is diffused, to form a source region 110 and a drain region 116 of the N-channel MOS transistor and simultaneously to form a gate electrode of an N-type semiconductor.
Subsequently, the oxide film 109 is removed. An oxide film which is approximately 4,000 A - 8,000 A thick is formed by vapour growth, and its region corresponding to an electrode leading-out portion is removed by the photoetching technique. Thereafter, a metal (Aluminium) is evaporated, and an electrode interconnection portion is formed by the photoetching technique.
Subsequently, the resultant substrate is covered with an oxide film being 1 um to 2 um thick by vapour growth.
Here, in Figure 74(d), Q3 and 04 indicates MOS transistors which constitute a conventional CMOS inverter, and Qi and Q2 indicate P+ gate and N+ gate MOS transistors for generating a reference voltage.
Figures 75(a) to 75(d) show sections in the manufacturing process of P+ gate MOS and igate MOS transistors of the P-channel type. In this example, the steps up to Figure 75(c) are the same as those up to Figure 74(c). In Figure 75(d), however, the N-type impurity is diffused without removing an oxide film 109b overlying the gate of the MOSFET a2~ Figures 76(a) to 76(d) show sections in the manufacturing process of P+ gate MOS and N+ gate MOS transistors of the N-channel type.
Figures 77(a) to 77(d) show sections in the manufacturing process of N gate MOS and i gate MOS transistors of the N-channel type.
A process in an N-channel MOS semiconductor integrated circuit will now be described with reference to sections illustrated in Figures 78(a) to 78(e). The process has steps as described below.
(1) A P-type semiconductor substrate 101 having a resistivity of 8 - 20 Qcm is prepared, and a thermal oxidation film 102 which is 1 um thick is formed on the surface of the substrate.
(2) In order to expose the semiconductor substrate surface corresponding to portions in which MISFETs are to be formed, selected parts of the thermal oxidation film are etched.
(3) A gate oxide film (SiO2) 103, which is 750 to 1,000 A thick, is formed on the exposed semiconductor substrate surface (Figure 78(a)).
(4) That part of the gate oxide film 103 which is to come into direct contact with a polycrystalline silicon layer is selectively etched, to form a direct contact hole 103a. (Figure 78(b)).
(5) Silicon is deposited by the CVD (Chemical Vapor Deposition) process onto the whole major surface of the semiconductor substrate 101 having the oxide film 102, the gate oxide film 103 and the contact hole 103a to form the polycrystalline silicon layer which is 3,000 to 5,000 A thick.
(6) Selected parts of the polycrystalline silicon layer 104 being of the i-type or intrinsic semiconductor are etched. (Figure 78(c)).
(7) A CVD-mask SiO2 film is deposited to a thickness of 2,000 to 3,000 A on the whole major surface of the semiconductor substrate 101 by the CVD process.
(8) The CVD-mask SiO2 film 105 is selectively left only at high resistance parts such as memory cell load resistors, and on the polycrystalline silicon layer of intrinsic level gate portions 104a. (Figure 78(d)).
(9) Phosphorus is diffused into the semiconductor substrate 101, to form source regions and drain regions 106 at an impurity density of 1020 atoms cm-3. Simultaneously, the impurity is also introduced into the polycrystalline silicon layer, to form gate electrodes 1 04b, a direct contact 104c and a polycrystalline silicon interconnection portion 104d. (Figure 78(d)).
(10) A PSG (Phospho-Silicate-Glass) film 107 is formed at a thickness of 7,000 to 9,000 A on the entire major surface of the semiconductor substrate 101.
(11) Al (aluminium) is thereafter evaporated on the whole area of the major surface of the semiconductor substrate 101, to form an Al film 108 which is 1 mm thick.
(12) The Al film is selectively etched to form interconnection regions 108. (Figure 78(e)).
The principle of obtaining the difference of Fermi levels described above and actual examples will be briefly explained again. Figure 58 shows enhancement type p-channel Metal Insulator Semiconductor Field-Effect transistors (herein referred to as MISFETs) Q1 and Q2 which are formed on an n-type semiconductor substrate 1. The gate electrodes of the respective MISFETs are made of conductor layers which are constructed in such a way that polycrystalline silicon layers are doped with semiconductor impurities of different conductivity types. More specifically, the MISFETs 01, Q2 are fabricated as follows. As shown in Figure 58, p±type semiconductor region 4, 5 to form the sources and drains of MISFETs are selectively formed on an n-type semiconductor substrate 1.Gate insulating films 2 are formed on the areas of the surface of the semiconductor substrate between the opposing source and drain regions 4,5, and polycrystalline silicon layers 6 and 6' are formed on the gate insulating films 2. The polycrystalline silicon layer to constitute the gate 6' of one MISFET Q, is doped with a semiconductor impurity of the same conductivity type as that of the substrate (n-type). The polycrystalline silicon layer to constitute the gate 6 of the other MISFET Q2 is doped with a semiconductor impurity of the conductivity type opposite to that of the substrate (p-type).
The threshold voltages (VthQ1, Vtho2) of the respective MISFETs Q1, Q2 in the above construction are derived from the following equations: VthO, = #Mn + OSS/Cox + OD/Cox ~---- (19) VthQ2 = ~Mp + Oss/Cox + OD/Cax ..... (20) Here, ~Mn and ~Mp denote the work functions between the gates of the respective MISFETs Q1, Q2 and the substrate, COX the gate capacitance per unit area QSS the surface charge, and QD the charge of a substrate depletion layer.
When the difference of the threshold voltages of both the MlSFETs Q1, Q2 is evaluated, it becomes the difference (#Mp - #Mn) between the work functions which are the first terms of the right-hand sides of Equations (19) and (20), and it can be derived as a voltage which corresponds to the energy gap of silicon.
Since this voltage becomes a voltage determined by the energy gap of silicon, deviations in the manufacture are not involved. In addition, the temperature-dependence is extremely small. The reason why the threshold voltages of MISFETs exhibit large deviations is that the second terms (Oss/Qox) and the third terms (OD/Cax) on the right-hand sides of Equations (19) and (20) fluctuate depending upon the conditions of manufacture.
In this embodiment, the MlSFETs Qi, Q2 are manufactured under the same conditions and hence the second terms and third terms on the right-hand sides of equations (19) and (20) are made substantially equal. By evaluating the difference between the right-hand sides, the second and third terms are cancelled. Thus, the magnitude equivalent to the energy gap is used as an output voltage.
Since the MISFET Q2 has the source, drain and gate electrode formed by the use of the semiconductor impurity of an identical conductivity type, the conventional manufacturing technology of a silicon gate MISFET, in which the semiconductor impurity diffusions of its source and drain and its gate electrode are performed simultaneously, can be employed. However, the gate electrode of the MISFET Q1 cannot be formed simultaneously with the source and drain and therefore needs to be formed by a separate step. To perform this, a method is considered wherein the MISFETs Qi, Q2 as above described are formed while employing the conventional manufacturing technology of the silicon gate MISFET in which a gate insulating film and a field insulating film are used as a mask. Alternatively, a measure illustrated in Figure 61 is considered.Those parts 6a, 6'a of gate electrodes 6, 6' of MISFETs Q1,Q2 which are close to sources and drains are made gate electrode portions in which a p-type semiconductor of the same conductivity type as that of the sources and drains is diffused. The central parts of the gate electrodes which are not doped with any semiconductor impurity, that is, which are made of the intrinsic semiconductor (i-type), are selectively formed with a gate electrode portion 6b in which a p-type impurity is diffused and a gate electrode portion 6'b in which an n-type semiconductor impurity is diffused, respectively.Herein, the parts doped with no semiconductor impurity have been disposed in consideration of the misregistration of the mask alignment in the case of forming the gate electrode portions 6b, 6'b of the different semiconductor impurities in the selected regions. In this method, the gate electrode portions 6a, 6b of the MISFET (02) are formed by the same step as that for the diffusion of the source and drain.
Each of the MlSFETs in the above construction has the gate electrode which is made up of the plurality of gate electrode portions. The plurality of gate electrode portions are connected together and the difference of threshold voltages of both the MlSFETs Qi, Q2 are obtained. Hence, threshold voltage components based on the electrode portions of the same structures (gate electrode portions 6a and 6'a, and i-type electrode portions) in both the MISFETs Qi, Q2 are cancelled. In addition, regarding the MISFETs owing to the gate electrode portions 6b, 6'b, the second and third terms on the right-hand sides of Equations (19) and (20) are not cancelled.As the difference voltage, there is obtained the voltage which corresponds to the silicon energy gap being the difference of the work function between the central parts 6b, 6'b of the gate electrodes and the substrate as described previously, and which is approximately 1.1 V.
Figure 62 shows a complementary insulated gate field-effect transistor integrated circuit (CMOSIC) according to another embodiment of this invention. P-channel MOS transistors A, B and C are formed on an N-type silicon body 1, while N-channel MOS transistors D, E and F are formed on a well layer 2 in which a P-type impurity is diffused at a low concentration. A reference voltage generating device is constructed by utilizing the difference between the threshold voltages of the MOS transistors A and B, the MOS transistors A and C or the MOS transistors B and C, or the difference between the threshold voltages of the MOS transistors D and E, the MOS transistors D and F or the MOS transistors E and F. Shown in Figure 62 is a thick field oxide film (SiO2) 3, and a gate oxide film (SiO2) 4.Also shown is a P-type semiconductor region 5 for the source or drain of the P-channel MOSFET, and an N-type semiconductor region 6 for the source or drain of the N-channel MOSFET, P-type polycrystalline silicon 7, N-type polycrystalline silicon 8, and the intrinsic semiconductor or i-type polycrystalline silicon 9. The reference voltage generating device derives the Fermi level difference among the materials 7,8 and 9 in the form of the voltage.
Figure 63 shows an embodiment which is a further improvement on the embodiment of Figure 62. P-type impurity layers 10 shown in Figure 63 are disposed under the gate oxide films 4 in a manner to overlap with the central parts 8 and 9 of the gate electrodes of the respective transistors B and C in Figure 62, and the transistor A is also provided with a P-type impurity layer 10 so as to have an effective channel length equal to those of the transistors B and C. Also, N-type impurity layers 11 shown in Figure 63 are provided under the gate oxide films 4 in a manner to overlap with the central parts 7 and 9 of the gate electrodes of the respective transistors E and F in Figure 62, and the transistor D is also provided with an N-type impurity layer 11 so as to have an effective channel length equal to those of the transistors E and F.The effective channel lengths of the transistors A, B and C or the transistors D, E and F can be made substantially equal by providing the P-type impurity layers 10 or the N-type impurity layers 11. Hence, the characteristics between the drain currents and gate voltages of the transistors A, B and C or the transistors D, E and F become curves which are parallel to one another and which shift in the direction of the gate voltage axis by the differences of the Fermi levels of the polycrystalline silicon materials at the central parts of the gate electrodes of these transistors. Therefore, the differences of the threshold voltages of the transistors can be obtained with high precision in reference voltage generating circuits to be described later.
The temperature-dependence of the differences of the threshold voltage of the three sorts of IG FETs are very small because the temperature-dependence of the differences of the Fermi levels of the gate electrode semiconductors are low.
Figures 79(a) to 79(e) illustrate a method of manufacturing the CMOSIC shown in Figure 63. The process has steps as described below.
(a) A low concentration P-type well region 102 is formed in an N-type silicon body 101 by the conventional selective diffusion process. Subsequently, a field oxide film 103 is formed. After forming a gate oxide film 104 in recesses of the film 103, a P-type impurity layers 105 and an N-type impurity layers 106 are formed by conventional selective ion implantation processes.
(b) Polycrystalline silicon gate electrodes 107 are formed by conventional chemical vapour deposition and photoetching. At this stage, the electrodes 107 are made of the intrinsic semiconductor.
(c) A mask oxide film 108 is formed on selected areas by chemical vapour deposition. Using it as a mask, source and drain layers 109 of P-channel MOSFETs and P-type polycrystalline layers 110 are formed by the selective diffusion of a P-type impurity.
(d) A mask oxide film 108' is formed on selected areas by chemical vapour deposition. Using it as a mask, source and drain layers 111 of N-channel MOSFETs and N-type polycrystalline layers 112 are formed by the selective diffusion of an N-type impurity.
(e) A phosphosilicate glass film 113 is depositioned, in which contact holes and aluminium electrodes 114 are formed. The device is then complete.
Figure 64 shows another embodiment of the structure of IGFETs which form the reference voltage generating device according to the present invention and which have gate electrodes of different Fermi levels. Here, IGFETs A, B and C have a gate electrode which is made of P-type silicon 7, a gate electrode whose ends are made of P-type silicon 7 and whose central part is made of intrinsic silicon 4 and a gate electrode whose ends are made of P-type silicon 7 and whose central part is made of aluminium 12, respectively. These gate electrodes lie on the gate oxide films (SiO2) 3 which are formed on different surface areas of an identical N-type silicon body 1 under substantially the same conditions. Further, the IGFETs have source and drain layers 8.When the threshold voltage VTH of the IGFETA is made -0.8 V, that of the IGFET B becomes approximately~1.40 V, and that of the IGFET C becomes approximately~1.95 V. They produce differences which are substantially equal to the differences of the Fermi levels of the Si and Al materials at the central parts of the gate electrodes.
This embodiment makes use of the fact that the temperature-dependence of the difference of approximately 1.15 eV between the Fermi levels of the high concentration P-type silicon and the aluminium or the difference of approximately 0.60 eV between the Fermi levels of the intrinsic silicon and the aluminium is low.
Figures 80(a) to 80(d) illustrate an embodiment of a method of manufacturing a P-channel IGFET integrated circuit which includes all the IGFETs A, B and C shown in Figure 64.
The method has stages as described below.
(a) Athickfield oxide film (SiO2) 2 having recesses is formed on the surface of an N-type silicon body 1, a gate oxide film 3 is formed in the recesses, and a polycrystalline silicon layer 4 is deposited by chemical vapour deposition. The polycrystalline silicon layer 4 is of the intrinsic semiconductor. Further, a mask oxide film 6 is formed on a part of the layer 4 by chemical vapour deposition.
(b) The polycrystalline silicon layer is selectively removed by the conventional photoetching process, and a P-type impurity such as boron is thermally diffused, to form source and drain layers 8 and P-type polycrystalline silicon layers 7. At this time, the part of the polycrystalline silicon layer 4 covered with the oxide film 6 remains an intrinsic semiconductor.
(c) An insulating film 9 such as phosphosilicate glass film is deposited by chemical vapour deposition, and in which contact holes are formed. At this time, a contact hole 10 is also formed in the central part of a gate electrode in an area to become an IG FET C.
(d) Aluminium electrodes 11 and 12 are formed, and a heat treatment is conducted at 380 to 540"C for 30 minutes to 3 hours. Then, the polycrystalline silicon at the contact hole 10 diffuses towards the upper surface of the aluminium layer owing to its alloying reaction with the aluminium, and a structure in which the aluminium and the gate oxide film lie in direct contact is established. The method of manufacturing the P-channel IGFET integrated circuit as illustrated in Figures 80(a) to 80(d) is also applicable to the manufacture of a complementary MIS integrated circuit substantially unchanged.
The alloying reaction may be replaced with an alternative in which the central part of the gate electrode is removed by photoetching, whereupon aluminium is brought into direct contact with the gate insulating film.
The reference voltage generating device based on such a construction exhibits a small temperaturedependence and small manufacturing deviations, so that it can be utilized for various electronic circuits.
Figure 81 (d) shows the structure of IGFETs A, B, C and D which have threshold voltage differences based on the Fermi level differences of gate electrodes in accordance with another embodiment of the present invention. The IG FET A is a P-channel MOSFET having a gate electrode made of P-type silicon 11, while the IGFET B is a P-channel MOSFET having a gate electrode whose both end parts are made of P-type silicon 11 and whose central part is made of N-type silicon 8. The IGFET C is an N-channel MOSFET having a gate electrode made of N-type silicon 8, while the IGFET D is an N-channel MOSFET having a gate electrode whose both end parts are made of N-type silicon 8 and whose central part is made of P-type silicon 11.A reference voltage generating device is constructed by employing a voltage based on the difference between the threshold voltages of the MOSFETs A and B or the MOSFETs C and D.
Figures 81 (a) to 81 (d) illustrate a method of fabricating a MOS integrated circuit which includes the IGFETs A, B, C and D.
The method has stages as described below.
(a) A P-type well region 2 is formed in an N-type silicon body 1, and a thick field oxide film 3 having recesses is formed. Then, a gate oxide film 4 is formed in the recesses of the oxide film 3, and a film 5 of polycrystalline silicon, being the intrinsic semiconductor, is deposited and worked by the photoetching process.
(b) A mask oxide film 6 is formed on selected areas by chemical vapour deposition. Using it as a mask, an N-type impurity such as phosphorus is diffused into selected regions, whereby N-type regions 7 to become the sources and drains of N-channel MOSFETs and N-type polycrystalline layers 8 are formed.
(c) A mask oxide film 9 is formed on selected areas by chemical vapour deposition. Using it as a mask, a P-type impurity such as boron is ion-implanted, whereby P-type regions 10 to become the sources and drains of P-channel MOSFETs and P-type polycrystalline silicon layers 11 are formed. Here, in case of using boron, the oxide film 9 is made about 3,000 A thick, and an implantation energy of 30 to 50 keV and an implantation quantity of 2 x 1015 to 1 x 1016 cm-2 may be used. The activation of the implanted ions may be achieved by a heat treatment ranging from 9000C for 10 minutes to 1,000 C for 30 minutes.
The diffusion of the N-type impurity in the step (b) may be performed after the step (c). In this case, the N-type impurity diffusion indicated in the step (b) is preferably performed by the ion implantation of phorphorus or a similar substance. In the case of using phosphorus, the oxide film 6 is made about 3,000 A thick, and an implantation energy of 60 to 100 keV and an implantation quantity of 2 x 1015 to 1 x 1016 cm~2 are appropriate. A heat treatment suitable for the activation of the implanted ions is at 9000C for 10 minutes to at 1 ,000"C for 30 minutes.By carrying out the doping with the P-type impurity in this manner, the heat treatment after the doping with the P-type impurity can be eliminated, so that the channel portions can be prevented from being doped with the P-type impurity.
(d) After depositing a phosphosilicate glass film 12 by the chemical vapour deposition, contact holes are formed, and aluminium electrodes 13 are formed, the device is then complete.
Referring again to Figure 58, another embodiment of the present invention will now be described. In the Figure, a P-channel MOSFET Qs has a gate electrode made of N-type polycrystalline silicon 6', and a P-channel MOSFETQ2 has a gate electrode made of P-type polycrystalline silicon 6.
Since these FETs are manufactured under substantially the same conditions except for the conductivity types of the gate electrodes, the difference of the threshold voltages Vth of both the FETs becomes substantially equal to the difference of the Fermi levels of the P-type silicon and the N-type silicon. The gate electrodes are doped with respective impurities near the saturation densities, and the difference becomes substantially equal to the energy gap Eg of silicon (approximately 1.1 V). The Vt#-difference can be obtained with high precision by making the channel dimensions of both the FETs equal, and it is utilized as a reference voltage source.
Since a reference voltage generating device based on such a construction exhibits a small temperaturedependence and small manufacturing variations, it can be used for various electronic circuits.
In Figure 58, is shown an N-type silicon body 1, a thick field oxide film 1, a gate oxide film 2, a P-type source region 4, and a P-type drain region 5. Here, the N-type polycrystalline silicon gate 6' has a structure which is doped with both an N-type impurity and a P-type impurity, the density of the N-type impurity being 1.5 times or more higher than the density of the P-type impurity. Alternatively, it has a structure which is doped with an N-type impurity, almost no P-type impurity being contained, and nevertheless, which is self-aligned with the source and drain.
The reason why the density of the N-type impurity needs to be 1.5 times or more higher than the density of the P-type impurity is as follows. In the ordinary high-density impurity doping techniques, the control of a density is subject to variations of about + 20% of the set value. Hence, the ratio between the variations of the N-type impurity density and the P-type impurity density becomes (1.51 0.3)/(1.1 1 0.2). Since the minimum value of this ratio becomes 1/1, the Fermi level of the polycrystalline silicon doped with both the N-type and P-type impurities varies greatly.
In order to allow some manufacturing variation, the ratio of the impurity densities needs to be always 1.5 or greater.
Figures 82(a) and 82(b) illustrate a method of manufacturing IGFETs for setting the ratio of the impurity densities at 1.5 or greater. The method has stages as described below.
(a) An N-type silicon body 1 at a comparatively low impurity density (for example, below 5 x 1016 cm~3) is oxidized to form a thick oxide film 2 for isolating elements. After forming a gate oxide film 3 in recesses of the film 2, an intrinsic semiconductor polycrystalline silicon film at 6 and 6' is deposited by chemical vapour deposition. Then, a mask oxide film 7 is formed on a selected area by chemical vapour deposition. Using the oxide film 7 as a mask, the polycrystalline silicon film 6' is selectively doped with an N-type impurity such as phosphorus or arsenic and at a high density (for example, above 5 x 1018 cm~3). Thus, the N-type polycrystalline silicon film 6' is obtained.
(b) After removing the mask oxide film 7, the working of a polycrystalline silicon gate electrode is performed by photoetching, and source and drain impurity layers 4 and 5 are formed at a low density (for example, below 3.3 x 1018 cm-3) by the thermal diffusion of a P-type impurity such as boron. Here, the density of the N-type impurity with which the polycrystalline film 6' is doped in the stage (a) is made 1.5 times or more higher than the density ofthe P-type impurity with which the polycrystalline silicon film 6' is doped at the time of the P-type impurity diffusion in the stage (b), and hence the polycrystalline silicon gate 6' is held at the N-type.
Figures 83(a) to 83(d) illustrate another method of manufacture according to this invention. Figure 83(a) shows the same manufacturing step as in Figure 82(a). The subsequent stages are described below.
(b) After removing the mask oxide film 7, the processing of a polycrystalline silicon gate electrode is performed by photoetching. Subsequently, using the polycrystalline silicon gates 6 and 6' as a mask, the gate oxide film, which lies on parts corresponding to sources and drains to be formed, is removed, the resultant silicon body is then subjected to an oxidation in steam at 750"C to 9000C for 60 seconds to 600 seconds. In the oxidation, the oxide film-growth rate of the silicon surface depends upon the density of an impurity contained in the silicon. Especially when the impurity density is at least 5 x 1018 cm-3, preferably 1020 cm-3 or higher, the oxide film-growth rate becomes large.Therefore, comparatively thin oxide films 8 and 10 of 20 to 40 A are formed on the surfaces of the parts corresponding to the source and drain and having the comparatively low impurity density and on the surface of the intrinsic polycrystalline silicon 6, respectively. Also, a comparatively thick oxide film 9 of 70 to 200 A is formed on the surface of the N-type polycrystalline silicon gate 6' having the comparatively high impurity density.
(c) Boron can pass through an oxide film of a thickness of at most 40 A by thermal diffusion, and cannot pass through an oxide film of a thickness of at least 70 A. Therefore, boron is subsequently thermally diffused at 950 to 1,000 C for about 20 minutes. Thus, the boron penetrate through the comparatively thin oxide films 8 and 10 to form the P-type impurity layers 4 and 5 and the P-type polycrystalline silicon layer 6.
At this time, the N-type polycrystalline silicon layer 6' is protected by the comparatively thick oxide film 9, and it is not doped with the boron. As an alternative method, the oxide films are etched with an etchant of HF: H2O = 1: 99 to 60 seconds before the thermal diffusion of boron to remove the oxide films 8 and 10 and to leave the oxide film 9 with a thickness of 40 - 150 A. Thermal diffusion of boron is then performed. Thus, a similar structure is obtained.
(d) Subsequently, a phosphosilicate glass film 11 is formed, contact holes are formed, and aluminium electrodes 12 are formed. The fabrication of the device is then complete.
Although the present method of manufacture has been explained referring to the example of silicon gate P-channel MOSFETs, the same method applies in the case of P-channel MOSFETs in a silicon gate CMOSIC.
Circuits according to embodiments of the present invention for obtaining the difference of the threshold voltages Vth of the MOS transistors will now be explained.
Although the circuits described below can be used to obtain the differences of the Fermi levels (Efn -Efp), (Efn - Ej) and (Ej - Efp), they are further applicable as reference voltage generating devices which, in general utilize as a reference voltage a voltage based on the difference of the threshold voltages Vth of FETs having unequal threshold voltage values.
Figure 6(b) shows a circuit which generates voltages corresponding to threshold voltages of MOS transistors. Transistors T1 and T2 form the so-called MOS diodes in which drains and gates are connected together.
1o designates a constant-current source, and T1 and T2 indicate MOSFETs which have unequal threshold voltages Vtha and Vth2 as indicated in Figure 6(a) and substantially equal mutual conductances p. Letting the drain voltages of the respective transistors be V1 and V2, the following equations hold; 1o = 1/2P(Vl-Vthi)2 = 1/2 ss (V2 - Vth2)2 (21) Therefore,
By taking the difference of the drain voltages, the difference of the threshold voltages can be derived.
Sufficiently high resistances may be used as the constant-current source. If their characteristics are uniform, there can be used diffusion resistances, polycrystalline Si resistances, resistances formed by the ion implantation, or high resistances formed from MOS transistors.
When, in this circuit, the N+ gate P-channel MOS and the P+ gate P-channel MOS, previously explained with reference to Figures 58 and 59 respectively, are used as the transistors Ta and T2, that difference (Efn Efp) of the Fermi levels of the N-type semiconductor and the P-type semiconductor which is a value substantially equal to the difference of the threshold voltages can be obtained.
In addition to making the compositions of the gate electrodes different, it is possible to create unequal threshold voltages by, for example, implanting ions into the channels, altering the thicknesses of a doped gate oxide or gate insulating films, etc. When such a measure is applied to the circuit of Figure 6(b), the difference of the threshold voltages, corresponding to the implanted quantities of the ions or the difference of threshold voltages, corresponding to the quantities of an impurity with which the gate insulating films are doped, or corresponding to the thicknesses of the gate insulating films, can be similarly obtained as the reference voltage.
For example, the ion implantation method can achieve a higher precision of impurity concentration than the convention diffusion because the quantity of implantation can be monitored in the form of current.
Figure 7 illustrates this situation. Letting T1 denote the characteristics of MOS transistors before the implantation of ions, if they have been individually dispersed at the manufacture and the threshold values are individually shifted by AVth due to the ion implantation, the magnitude EVth, being the difference of both the threshold voltages, is determined by the quantity of the ion implantation and therefore only varies to a small extent. It can accordingly be similarly used as a reference voltage with only small variations of manufacture.More specifically, letting Vth1 indicate the threshold voltage of the MOS transistor T1 which is not subjected to the ion implantation, similarly to Equation (15): Vth1 = Qs 2 Of COX COX (23) #Ms#2##COX#COX Letting EQB indicate the increment of fixed changes in the substrate due to the ion implantation, the threshold voltage Vth2 of the MOS transistor T2 subjected to the ion implantation becomes: Vth2 = ~MS~2Ms2FCOX COX Thus Vthl - Vth2 = ..... (25) COX The temperature variation of this difference voltage between the threshold voltages is extremely small because Qs is almost invariable under temperature changes.
Also advantageous is that the reference voltage can be freely set by the quantity of ion implantation and that the device can be easily constructed, even by the single-channel MOS manufacturing process.
Figures 8 and 9 show examples of circuits in which an N±gate and FET T1 and a P±gate FETT2 having unequal threshold voltages, as in the case of Figures 6(a) and 6(b), are used, and the FET T1 is connected in the MOS diode form and is connected in series with the FET T2, to obtain the difference of the threshold voltages. It is supposed that the FET T1 has a threshold voltage Vth1, while the FET T2 has a threshold voltage Vth2.
Under the condition that the resistance R1 is sufficiently large when compared with the impedance of T1 and that the resistance R2 is sufficiently large when compared with the impedance ofT2, V1-V2 . Vth1 .: (26) V1 6 Vth2 ..... (27) Therefore, V2 6 Vthl - Vth2 (28) Figure 11 (a) shows a device in which voltages corresponding to the threshold voltages of an N±gate MOS T1 and a P±gate MOS T2 are applied to both terminals of a capacitor C1 connected to the MOS transistors, and a voltage across the capacitor is obtained as a difference voltage. Figure 11 (b) shows the operating timings.MOS FETs T5 and T6 are turned "on" by a clock pulse prl, to charge the difference voltage of the threshold voltages Vthl and Vth2 of the MOS FET T1 and T2 in a capacitor C1.
After turning the MOS FETs T5 and 18 "off" by the pulse ~, a MOS FET is turned "on" by a clock 82 SO as to ground a node 0 of the capacitor C1. Since, at this time, the difference voltage of the threshold voltages is stored in the capacitor C1, the difference potential appears at a node (2) of the capacitor C, unchanged. In the case of use for a voltage detector circuit to be described later, the potential of the node (2) at this time can be employed as a reference voltage.In order to permit the use in a more general form, however, transmission gates T8 and T7 are turned "on" by a clock m3 within a period of time during which the high level signal of the clock 82 iS applied, the potential is stored across a capacitor C2 connected to the non-inverting input (+) of an operational amplifier 5, and the potential is received by the voltage follower in which 100 % of an output is negatively fed back to the inverting input (-) of the operating amplifier 5. Then, the output of the voltage follower, the difference of the threshold voltages of T, and T2, is obtained as a reference voltage when the internal impedance is sufficiently low.
Figure 10(a) is a circuit diagram showing an embodiment of a dynamic type difference voltage output circuit which uses the difference of the threshold voltages of an N±gate N-channel MOS Q1 and a P±gate N-channel MOS 02.
In this circuit, the gates and drains of the MISFETs Qi, O2 are interconnected, and they are connected to a bias power supply VDD through load resistors (R1, R2). A capacitor C is situated between the gate and drain terminals, and the difference component between the threshold voltages of the MISFETs 01, 02 iS stored in the capacitor so as to provide an output. A P-channel MISFET Q3 which is driven by a clock pulse ~ is incorporated between the gate and source of the MISFET Qi with smaller threshold voltage.The respective load resistances of the MISFETs Q1, Q2, and on the "on" resistance of the MISFET is made sufficiently smaller than the "on" resistances of the MISFETs Q1, Q2. In such a circuit arrangement, as shown in an operating waveform diagram of Figure 10(b), when the clock pulse ~ has reached a low level, to turn the MISFET Q3 "on", the difference -(V2 - V1) between the drain voltages (threshold voltages V1, V2) of both the MlSFETs 01, 02 iS provided from the drain of the MISFET Q2 or the terminal of the capacitor C remote from the MISFET 03. The difference voltage output similar to those of the foregoing circuits is obtained by sampling it at a pulse time ~.
Figure 12 shows a reference voltage generating device which utlizes an N±gate MOS Ti, a P±gate MOS T2 and a capacitance C2 in a similar way. MOS FElT8 is turned "on" by a clock prl. At this time, a MOS FElTs is in the "off" state due to the output of a clock ag. The potential of a node (g3 becomes lower than that of a node~ by the threshold voltage Vthl of the MOS FElT1, and the potential of a node(2) becomes lower than that of the node~ by the threshold voltage Vth2 of the MOS FElT2. Hence, the difference voltage of both the threshold voltages Vth, and Vth2 is applied across the capacitance C2.Subsequently, the MOS FET If is turned "off" by ~ and the MOS FET Tg is turned "on" by m,. Then, the difference voltage of the threshold voltages is provided atthe node 0.
Figure 13 shows an operational amplifier according to the present invention. A differential pair Ii and T2 constitute a differential amplifier circuit, and 112 and 113 designate active loads of the differential amplifier. A transistor T forms a constant-current circuit with transistors 114 and 116. Transistors T,5 and 116 form a level shift output buffer circuit whose constant-current source load is the transistor 116. Although the example of a circuit arrangement based on C-MOS is shown in the Figure, the circuit can of course be constructed of single-channel MOS.
In this operational amplifier, the differential pair transistors T, and T2 forming the differential amplifier circuit are provided with unequal threshold voltages Vth, and Vth2 on the basis of the Fermi level difference of the gate electrodes as described previously, the difference of the threshold voltages can be utilized or obtained as a reference voltage. This is a new application of an operational amplifier.
Figure 14 shows schematically an ordinary operational amplifier, showing only the features that make it a differential amplifier. It is here assumed that MOS transistors Ta and T2 have unequal threshold voltages Vth, and Vth2 respectively and that the other characteristics such as mutual conductances are equal. Signs (-) and (+) appearing on the input side signify the inverting and non-inverting inputs, respectively.
Letting V1 denote an input voltage of the transistor T, and V2 an input voltage of the transistor 12, V1 - Vthl = V2 - Vth2 that is, V1 - V2 = Vth, ~Vth2 (29) The output level changes with this input voltage condition as the boundary.
The operational amplifier is provided with an input offset corresponding to the difference voltage of the threshold voltages. Therefore, when either the inverting input (-) or the non-inverting input (+) is earthed or connected to a reference potential of a power supply, it can be operated as a voltage comparator whose reference voltage is the offset voltage. Alternatively, when the output is connected to the inverting input terminal (-) to construct a voltage follower circuit and the non-inverting input terminal (+) is earthed as shown in Figure 14, the difference of the threshold voltages is obtained at the output 'Out'. In this example, in order to operate the operational amplifier, the transistor T2 needs to be a depletion mode MOS FET.For example, if a P±gate MOS is used for Ta and an N±gate MOS is used for T2, they may be made the depletion type by subjecting the channel portions of both the MOSFETs to the ion implantation under the same conditions.
Figure 15 shows a device which can arbitrarily set a reference voltage by the use of the operational amplifier in Figure 14. An output is fed back to the inverting input (-) through voltage divider means R5 and R6. Thus, letting r denote the voltage division ratio R6/R8+R6, the output voltage VO becomes: V - Vtha Vth2 (30) r The voltage divider means R8 and R6 should preferably be linear resistances, but any resistances may be adopted provided that their characteristics are sufficiently uniform.
The circuits of Figures 14 and 15 assume the use of the depletion type MOS, but the circuits in Figures 16 and 17 operate with enhancement type MOS. Of course, the depletion type MOS may be used.
Similarly, to the example of Figure 14, the example of Figure 16 directly feeds an output back to an inverting input (-). Letting VDD denote a supply voltage, the output VO becomes: VO = VDD~ (Vth. ~Vth2) ,,,..
With the circuits of Figures 14 and 15, at least one of the differential pair transistors needs to be put into the depletion mode, which necessitiates an increase in the number of manufacturing steps in some cases.
However, they can obtain the difference voltage of the threshold voltage Vth with reference to the earth potential.
Conversely, with the circuits of Figures 16 and 17 the reference of the difference voltage to be obtained is not the earth potential. However, the condition of the operating mode of the FET is not imposed.
The circuit form which is adopted may be decided by the feature to which most importance is attached.
Similarly to the example of Figure 15, the example of Figure 17 feeds an output back to an inverting input (-) through voltage divider means R7 and R8. The output becomes: V = VDD - Vth1 - Vth2 (32) Figure 18 shows a voltage detector circuit in which a reference voltage VR from a reference voltage generating device RVG according to the present invention, which uses the difference of the threshold voltages Vth, is applied to one input of a conventional voltage comparator VC and a voltage VD to be detected is applied to the other input, the height of the voltage to-be-detected VD relative to the reference voltage VR can hence be discriminated.
Shown as an example in Figure 19 is a voltage detector circuit wherein a reference voltage VR from a reference voltage generating device RVG which utilizes the difference of threshold voltages Vth, corresponding to the Fermi level difference of gate electrodes in accordance with the present invention, is applied to one input of a voltage comparator VC and a voltage obtained by dividing a voltage to-be-detected VD by voltage divider means R9 and and Rio, is applied to the other input. Letting r denote the voltage division ratio, Vref denote the reference voltage and Vsense the detection level.
Vsense = r The detection level Vsense can be arbitrarily set by controlling the voltage division ratio r.
Shown, as an example, in Figure 20 is a voltage detector circuit which uses the operational amplifier with the offset corresponding to the difference of the threshold voltages Vth as described with reference to Figure 13 and uses the offset voltage as a reference voltage as explained previously. R11 and R12 indicate voltage divider means similarly to the example of Figure 19.
If the voltage to-be-detected VD is a battery supply voltage, in the example of Figure 18, 19 or 20, the voltage detector circuit can be used as a battery checker in a system which uses a battery as a power supply.
An example in which the voltage detector circuit of Figure 20 is applied to the battery checker of an electronic timepiece is shown in Figure 54, and will be described in detail later.
Figure 21 shows another embodiment of an operational amplifier circuit which is constructed by connecting, in the differential form, N-channel MOS FETs Q1 and Q2 having unequal threshold voltages Vth on the basis of the difference of the Fermi levels of gate electrodes in accordance with the present invention.
MOS FETs Q3 and Q4 operate as load FETs of the differential pair of MOS FETs Q1 and Q2, and a MOS FET Of operates as a constant-current source of the differential pair of MOS FETs Q1 and Q2- Figure 22 shows a differential amplifier circuit which has as its offset voltage, the difference of the threshold voltages Vth of MOS transistors Q1 and Q2 according to the present invention.
Figure 23 shows the drain current-versus-gate voltage characteristics of the MOS transistors Q1 and Q2 in Figure 22.
In this embodiment, the mutual conductances of the MOS transistors Q1 and Q2 constituting the Zdifferential pair are designed so as to become equal. As the current of a constant-current source CS of the differential circuit changes to be lot loB and iol their points of intersection with the VGS - Scharacteristic of the transistor Q1 vary to be points 1, 1' and 1" respectively, and their points of intersection with the VGS scharacteristics of the transistor Q2 vary to be points 2, 2' and 2" respectively. Initially, voltages VG1 and VG2 are applied to the gates of the respective transistors Qi and Q2 in order to bring the differential circuit into the balanced state.Hence, even when the current of the constant-current source CS has changed from lo to lot or io in dependence on the temperature, the difference of the voltages VG1 and VG2 which balance the differential circuit are held substantially constant.The difference voltage reflects the difference (Vthl - Vth2) of the threshold voltages of the transistors Q1 and 02. Hence, the temperature characteristic of the difference (Vthl - Vth2) of the threshold voltages of the transistors Q1 and Q2 appears unchanged as the difference (VGl - - VG2) of the voltages to be applied to the gates of the transistors Q, and Q2 in order to put these transistors into the balanced state.
When the P±gate and N±gate N-channel MOS transistors previously described are used as the transistors Q, and Q2 respectively, a voltage of approximately 1.1 V corresponding to the band gap is obtained. In the case of using a silicon semiconductor, this difference voltage has a temperature dependence with a gradient of -0.24 mV K-1.
The temperature dependence of the difference voltage of the gate voltages can be nullified by making the values of the conductances of the transistors QR and Q2 unequal.
Suppose, for example, that the temperature dependence of the constant-current source CS of the differential circuit has a positive gradient, while the difference (Vthl - Vth2) of the threshold voltages of the transistors Q, and Q2" exhibits a temperature dependence with a negative gradient.As indicated at Q1 and Q2" in Figure 23, the conductance of the transistor Q2D is made smaller than the conductance of the transistor Q1, hence, the gate voltage of the transistor Q2 under the balanced state varies as indicated at 3, 3' and 3" in dependence on the temperature, and the temperature dependence of the difference of the gate voltages of the transistors Q1 and Q2" as based on the difference of the conductances of the transistors Q1 and Q2" has a positive gradient. By suitably combining the magnitudes of the conductances, the total temperature dependence can be made zero or, at least, can be improved.
In the case where the temperature dependence of the constant-current source of the differential circuit has a negative gradient, the conductance of the transistor 021 iS made greater than the conductance of the transistor Q1, conversely to the above, and hence the temperature dependency can be improved.
In the balanced state, the following relations hold between the current lo of the constant-current source, and the threshold voltages Vthl and Vth2, mutual conductances ss1 and 02 and gate voltages VG1 and VG2 of the respective transistors Q1 and Q2: 10 = p1 (VG1 ~Vth1) = 2 (VG2 - Vth2)2 .....
In Equation (37), when ss1 > ss2, 1 P2 < 0, and when Pi < P2, ss - 1 > 0.
Therefore, the temperature gradient of the second term of Equation (37) can become either positive or negative.
Figures 24 and 25 show application circuits of voltage comparators each being another embodiment which can reduce the temperature dependence on the basis of the concept described above.
In Figure 24, MOS FETs Q1 and Q2 whose threshold voltages Vth are unequal owing to the difference of the Fermi levels of gate electrodes in accordance with the present invention are operated as source followers.
The balances state corresponds to the time when the differential input voltage of a voltage comparator circuit or operational amplifier circuit CM P1 is zero. In the balanced state, the following relations hold between the threshold voltages Vth1 and Vth2, mutual conductances ss1 and ss2, gate voltages VG1 and VG2 source voltages V1 and V2 and drain currents I1 and 12 of the respective MOS FETs Q1 and Q2:: I1 = ss1 (VG1 - Vthl - V1)2 12 = ss2 -21P2 (V52 - Vth2 - V2)2 (38) V1 = V2 ..... (39) Hence,
Thus, assuming that I1 = 12 = I, the temperature dependency of (VG1 - VG2) can be made zero by appropriately setting ss1 and P2 to conform with the temperature dependence of I and the temperature dependence of (Vth, - Vth2) similarly to the case of the differential circuit.
Further, in this example of the circuit, assuming that ss1 = P2 = P, Equation (42) becomes:
Therefore, even when the currents 1 and 12 are set at unequal values, the temperature dependence of the difference (VG1 - VG2) can be similarly made zero.
Figure 26 shows an embodiment of a constant-current circuit. When the conductances of FETs Q2 and Q3 are made 1 : n, a current flowing through the FET Q3 can be made n.l relative to a current I flowing through FETs Q1 and Q2- Accordingly, I1 and 12 in Equation (43) can be readily achieved by changing the ration in the above constant-current circuit.
Figure 27 shows an embodiment of a reference voltage generating circuit based on the differential circuit of Figure 22.
Transistors Q1,Q2,Q3 and Of enclosed with dotted lines in Figure 27 form a constant-current circuit similar to that in Figure 26, while transistors 04, Of, Of, Q7 and Q3 form a differential circuit similar to that in Figure 22. The transistor Of is a P±gate N-channel MOS transistor, and the transistor 07 is an N±gate N-channel MOS transistor.
Arrow symbols of gates represent the N±gate and the P±gate discriminatingly.
The MOS transistors Og and Q7 have their threshold voltages shifted by equal values by means of ion implantation or a similar process, and the MOS transistor 07 is a depletion MOS transistor.
An output based on transistors Q8 and Of is negatively fed back to the gate of the transistor Of. For an output voltage, the offset voltage of the transistors Qf and 07 can be used as a reference voltage. Letting Vo denote the output voltage and letting in Equation (37) VG1 = Vo, VG2 = 0, Vthl = Vthn+ Vth2 = Vthp+ ss1 = p6 and P2 = P7, then:
In this case, (Vth1 - Vth2) is the difference between the threshold voltages of the P±gate N-channel MOS transistor and the N±gate N-channel MOS transistor and become substantially equal to the band gap voltage of 1.1 V. The output voltage Vo is formed by adding the correction voltage of the second term to the band gap voltage.
Letting the mutual conductance of the transistor Q1 be Pi, and supposing the drain voltage of the transistor Q2 to be substantially equal to the threshold voltage Vthn Ic = Pi [(VDD - Vthn) (VDD - Vthp) -1(VDD - Vthp)2j (45)
In addition, ss1 = Pop (W/L)1 Pf = ssON (W/L)6 ss7 = PON (W/L)6 where Pop and PoN denote the mutual conductances per unit area of the N-MOS and P-MOS transistors, respectively. Hence, the output voltage is given by the equation
Differentiating Equation (46) as to the temperature T,
(VDD~VthP)~2 2(VDD-vthP)2 ] (47) (W/L)6 and (W/L)7 can be set so that the condition 5V0 6 maybe achieved.
Figure 28 shows an embodiment of a reference voltage generating circuit which is based on the construction of Figure 24. A circuit within dotted lines in Figure 28 forms the comparator circuit CMP1 shown in Figure 24.
Transistors Q1,Q2,Q4 and Q6 constitute a constant-current circuit. Currents flowing through transistors Q3 and Of can also be made unequal by making the ratios of the conductances of the transistors Q4 and QÔ different relative to the conductance of the transistor Q2 In this example the transistors Q3 and Q5 are an N±gate N-channel MOS transistor and a P±gate N-channel MOS transistor respectively.
As in previous examples, the output voltage VO is negatively fed back to the gate of the transistor Q3 so as to construct the voltage follower, and the earth potential is applied to the transistor Q5.
The temperature dependence of the output voltage can be made zero by making the conductances of the transistors Q3 and Q5 or the conductances of the transistors Q4 and Of unequal in accordance with Equation (42) or (43), or by combining both these measures.
Suppose, for example that the conductances of the transistors 03 and Q5 are equal at p, that the current to flow through the transistor 01 is I,, and that the ratio of the conductances of the transistors Q2 and 04 is 1 : while the ratio of the conductances of the transistors Q2 and Of is 1: n'. Then, the output voltage VO becomes:
By adjusting the values of n' and n, the temperature dependence of the output voltage VO can be made substantially zero. As a circuit arrangement which generates a reference voltage and which can make zero or improve the temperature dependency of the reference voltage, the circuit arrangement shown in Figure 25 may be used or circuit arrangements described previously.This circuit is operated with the sources of transistors Q, and Q2 earthed.
Figure 29 shows an embodiment of a circuit having a constant current which is determined by the difference of the threshold voltages of MOS FETs T, and T2 in accordance with the present invention.
The MOS FETs Ta and T2 have equal mutual conductances p, and their threshold voltages have values Vthl and Vth2 different from each other due to the difference between the Fermi levels of gate electrodes in accordance with the present invention. If a resistance R20 is sufficiently high, when compared with the impedance of T1, the drain voltage (= gate voltage) V1 of T1 becomes substantially equal to Vth1.
When T2 is in the saturation region, the current 12 flowing through 12 is: IOUT = 2 (Vth1 ~Vth2) " (49) Shown in Figure 30 is an embodiment of a constant-current circuit employing a reference voltage generating device RVG which generates a reference voltage VREF (= Vth1 - Vth2) determined by the difference voltage of the threshold voltages of MOS FETs corresponding to the difference between the Fermi levels of the gate electrodes in accordance with the present invention, and an ordinary operational amplifier VC.In the constant-current circuit, a voltage drop IouTR21 based on a current I flowing through a MOS FET T22 is compared with a reference voltage VREF, and the gate voltage of T1 is controlled so that both may be equal at all times.
From louts1 = VREF, lout = VREF ..... (50) In this case, the reference voltage may be obtained by providing the operational amplifier VC with an offset and earthing the non-inverting input (+ ) of the operational amplifier VC as in the previous example in Figures 13 and 14.
Figure 31 shows an embodiment of a constant-current circuit wherein the so-called current mirror circuit in which MOS transistors T31 and T33 have the same characteristics.
Figure 32 shows an example of an application in which a reference voltage VREF which is determined by the difference voltage of the threshold voltages of MOSFETs corresponding to the difference of the Fermi levels of the gate electrodes of the MOS FETs in accordance with the present invention is used for a stabilized power supply circuit. A reference voltage generating device RVG is constructed by any of the above-stated several methods according to the principle of the present invention. A divided voltage of a stabilized output due to voltage divider means R13 and R14 and a reference voltage are compared, and the gate voltage of a controlling MOSFET 120 is controlled so as to bring them into agreement, to stabilize the output voltage Vout.
Any operational amplifier may be used provided that its characteristics are suitable.
In an embodiment shown in Figure 33, the MOS transistor used for T20 in the example of Figure 32 is replaced with a bipolar transistor iR1.
The embodiment shown in Figure 34 uses the operational amplifier VC as shown in the example of Figures 13 and 14, which has the offset voltage based on the difference voltage of the threshold voltage Vth of MOSFETs and whose non-inverting input (+) is earthed. T21 may be a MOS transistor, a bipolar transistor or a junction field-effect transistor.
Figure 35(a) shows a voltage regulator according to the present invention which is a further improvement on the stabilized power supply circuits illustrated in Figures 32, 33 and 34, and Figure 35(b) is a characteristic diagram ofthevoltage regulator.
The circuit arrangement in Figure 35(a) is constructed as a comparing voltage regulator. It differs from a conventional voltage comparator in that the input characteristics of an operational amplifier VC being a voltage comparator are asymmetric at the input terminals of a non-inverting input (+) and an inverting input (-). Thus, this voltage comparator does not balance when the voltage levels of the non-inverting input (+) and the inverting input (-) are equal to each other, but balances when a predetermined high input voltage (in the absolute value) is applied on the inverting input (-). Hence, in this voltage comparator, the input levels of the non-inverting input (+) and the inverting input (-) have an offset with respect to the balance point.
Alternatively, in a conventional voltage regulating where the input voltage Vjn is high, the output voltage Vout depends upon a reference voltage Vref generated from the reference voltage generator RVC and the difference of Vault - Vjn is made large, whereas in the case where the input voltage Vjn is low, Vout depends solely upon Vi and the difference of t Vjn - Vauti is made small.According to the present invention, the changing point P between both the cases is set at a point of Vjn = V1 with respect to the input voltage Vjn (V, indicates the lowest operating voltage of a regulator load L).
In the voltage regulator of the present invention constructed in this way, when the input voltage Vjn is higher than the lowest operating voltage V1, the load L is controlled by the output voltage VoUtwhich is higher than the lowest operating voltage V1 but lower than the input voltage V10, and hence, the power dissipation is reduced while maintaining suitable operation. When the input voltage Vjn is low, the load L is controlled by the output voltage which is substantially equal to the input voltage Vjn or somewhat smaller than it, and hence, a voltage near the lowest operating voltage V1 of the load L for the input voltage Vin is supplied.Since the output voltage Vout is reduced to a voltage suited to the load L for the high input voltage Vjn, this voltage regulator can provide the load L with a low power dissipation and a wide range of input voltages Vjn.
This feature of the present invention will be described in detail with reference to the graph of Figure 35(b) by comparison with the prior-art voltage comparing regulator having no offset.
In the Figure, the axis of the abscissa represents the input voltage Vjn, while the axis of the ordinate represents the output Vout and the reference voltage Vref. Straight line a1 indicates Volt, equal to Vjn, hence, a virtual curve in the case where the load L is operated directly by the input voltage Vjn without employing the voltage generator.
Curve c indicates a reference voltage Vrefi generated from any of the reference voltage generating devices in various forms. Depending on the form of the device, the reference voltage generating circuit device RVG uses parameters of semiconductor devices such as the threshold voltage Vth of a MOSFET, the mutual conductance g,, the forward voltage VF or backward Zener voltage Vz of a PN-junction, and the current gain hfe of a bipolar transistor. Therefore, the reference voltage Vrefi depends upn the supply voltage Vin according to the voltage dependence of the parameter [ Vref, = f (Vjn) ] .
In the case where such a reference voltage Vrefr is used as the reference voltage of the voltage comparator circuit VC and where the comparator circuit VC is not provided with the offset as previously stated, the output voltage Vault becomes equal to the reference voltage Vrefi and agrees with the curve c. Since the reference voltage Vrefi does not become higher than the input voltage Vjn,the output voltage Vout becomes lower than the input voltage Vjn in any range. As a result, the input voltage Vjn at the time when the output voltage Vout becomes equal to the lowest operating voltage V1 of the load (point R) becomes V2 (V2 > V1).
Hence, the usable range of input voltages Vjn as viewed from the load L suffers a loss of a voltage component corresponding to I V2 - V1 In order to make this loss small, in the voltage regulator of Figure 35(a) according to the present invention the operational amplifier VC making up the voltage comparator balances when the inverting input (-) has become higher than the non-inverting input (+) by the offset voltage AVoff.
Due to the offset voltage AVoff of the operational amplifier VC, a reference voltage Vref2 (curve d) which is smaller than the virtual reference voltage Vref1 and which has a similar characteristic is employed as an actual reference voltage Vref. The values of Vref2 and EVoff are set so that a substantial comparison voltage (Vref2 + AVoff) at an input voltage V3 in the normal operation may become equal to the virtual reference voltage Vref1, so that it may agree with a desired operation point S.
With such a construction, the voltage comparator VC formed into the voltage follower balances under the condition of Vout = Vref2 + AVoff. Since input voltages Vjn satisfying the balance condition are only Vin > Vref2+ AVoff.
In case where the input voltage Vjn is smaller than (Vref2 + AVoff), the output voltage Vout also becomes smaller than it, so that the voltage comparator VC functions to raise the output voltage Volt. This feedback control, however, is limited when the output voltage Vout has become equal to the input voltage Vjn.
Accordingly, with the inflexion point P at Vjn = Vref2 + AVoff, the output voltage Vout is reduced (limited) to Vref2 + AV0ff (curve b1) when the i nput voltage Vi, is higher than the inflexion point P, and it is made substantially equal to the input voltage Vjn (curve a2) when Vin is lower than the inflexion point.
If the inflexion point P is the same as or higher than the lowest operating voltage V1 (point 0) with respect to the input voltage Vjn (on the axis of abscissas), the foregoing loss can be avoided. This is because the curve b1 has a point of intersection with the straight line a1 due to EVoff. In the case where the operational amplifier does not have the offset voltage AV0ff and where there is no point of intersection with the straight line a1 as in the curve d, such an effect is not achieved.
Although a MOS FET Tc in Figure 35(a) functions as a source follower, it is a depletion mode N-channel FET, so that it makes Vault = Vjn possible when Vjn S Vref2+ AVoff and that its threshold voltage Vth has no loss.
Hence, this applies when the input voltage Vjn is small.
This, however, does not prevent the use of a source follower FET of the enhancement type. The enhancement type FET is effective in the case where the input voltage is large, the Vth loss is not a serious problem and where the adoption of a depletion mode FET manufacturing process is difficult. In this case, curve a2(VOut = v10) which determines lower output voltages Vout (below the changing point P) merely shifts downwards by Vth(Vout = Vjn - Vth), and it is similarly possible to produce the effect on the output voltage Vout as previously stated.
In the Figure, the N-channel FET can be replaced with a P-channel FET. In this case, the P-channel FET functions with the source earthed, and the loss of Vth above described is not involved.
Whether the source earthing or the source follower is adopted as the controlling FET does not produce any essential differences. However, in the case of the source earthing, any special accounting for the loss of the threshold voltage Vth as in the case of a depletion mode FET is not necessary. In the case of the source follower, when the operation of the voltage comparison needs to be cyclically sampled (for example, when the comparator is subjected to the clock drive in order to render the power dissipation low), this FET is convenient as it functions as a voltage follower. This is because the output voltage is determined by the gate voltage if the mutual conductance 9m of the FET is sufficiently high.
It is also possible to use a bipolar transistor as the controlling transistor.
It is possible that the offset AV0ff becomes a function of the input voltage Vjn. In setting the inflexion point P, however, it is desirable that is constant with respect to Vn.
If a reference voltage which has a fluctuating factor similar to that of the load L is used as the reference voltage Vref2, output voltages Vout corresponding to the characteristic of the load L can be obtained. If, in that case, Vref2 is set in advance to the lowest voltage at which the load L can operate AV0ff can be used as means of a safety margin.
While a construction for providing the offset AV0ff, and an application circuit use the difference of the threshold voltages of two MOS FETs according to the principle of the present invention, to be described later, another method for providing the output voltage Volt with an inflexion point will be explained herewith reference to the circuit diagram of Figure 36(a) and the graph of Figure 36(b).
In the following description and the graph of Figure 36(b), all the voltage values shall be absolute values.
In Figure 36(a) is shown a controlling transistor Q107 which is made of an N-channel depletion mode FET.
N-channel FETs Qioi and 0102r and P-channel FETs Q104 and Q106 construct current mirror circuits. A drain current approximately equal to the drain current of 0103 flows through a diode-connected P-channel FET 0104 and a diode-connected N-channel FET 0108. The source-drain voltage drops VDS of the diode-connected P-channel FET Q104 and N-channel FET Q105 become approximately equal to respective threshold voltages Vthp and Vthn due to the high impedance loads 0102 and 0108. Hence, voltages Vthp and (V tout - Vthn) are applied to the non-inverting input (+) and the inverting input (-) of an operational amplifier VC constructing a voltage comparator (curves dand b in Figure 36(b)).
If the operational amplifier VC has no offset, it balances when both the inputs of the non-inverting input (+) and the inverting input (-) are equal. Hence, the equilibrium condition is (Vout - Vthn) = Vthp, or tout = Vthp + Vthn. The output voltage Vout is limited to (Vthp + Vthn) where Vjn 3 Vthn, and it becomes substantially equal to Vin when Vjn ffi Vthp + Vthn.Thus in the case where the load L is constructed of a complementary MOS integrated circuit (CMOSIC), the operating lower-limit voltage of the CMOS circuit usually becomes (Vthp + Vthn) and the output voltage Vout can compensate for it.
Although the threshold voltage to be derived by the diode-connected MOS Q104 and Q105 is close to the inherent threshold voltage, it is not equal to it and follows up the drain current of the circuit. It is favourable to make the output voltage Vout of the equilibrium point somewhat greater than the inherent value (Vthp + Vthn). To achieve this, the mutual conductance of the FET Q103 may be made small so that the current to flow through each MOS diode Q104 or Q105 is small.
The approximate threshold voltage to be derived by the MOS diode requires the flow of the drain current.
Therefore, the circuit must be constructed so that the currents may flow through both the diodes even when the input voltage Vjn becomes low.
The reference voltage generating device constructed according to the present invention can generate the difference voltage of the threshold voltages of MOS as the reference voltage, and can therefore be constructed as MISFETs. Hence, it can be used extensively as various constant-voltage sources in monolithic integrated circuits for an electronic desk top calculator, an electronic timepiece etc. made up of MlSFETs. As illustrated by way of example, in Figure 37, a lifetime detector circuit for a battery can be contained by applying the output of the reference voltage generating device (N±gate N-channel MOS QA, P±gate, N-channel MOS 02, resistor R1) as shown in the foregoing embodiment to one input of a voltage comparator circuit 7 as a reference voltage and a voltage obtained by dividing a battery voltage VDD by means of divider resistors R10, R11 is applied to the other input.
In this case, since the battery voltage does not lower suddenly, it is desirable to drive the constant-voltage generator circuit, the voltage divider circuit and the voltage comparator circuit with clock pulses, to achieve reduction of current consumption. Similarly, in the case where the constant-voltage output is not required at all times, the constant-voltage generator circuit may be clock driven as stated above.
The circuit for obtaining the difference of the threshold voltages of the MISFETs Oi, O2 is not restricted to the construction of the above embodiment, but it can be modified variously and any suitable circuit arrangement may be used.
Figure 38 shows another embodiment in which this invention is applied to a battery checker.
FETs Qi, 02,07 and Of constitute a constant-current circuit. FETs 03, Of, 04, Of and 07 constitute a differential circuit. Qii and Qlo provide the clock drive to achieve a reduction in the power dissipation.
Resistors R, and R2 constitute a battery voltage divider circuit for setting the detection level of a battery voltage. Logic elements G1 and G2 function to latch an output owing to Q8 and Of.
Q4 and Os are an N±gate P-channel MOS and a P±gate N-channel MOS, respectively. By ion implantation of equal quantities, Of is operated in the depletion mode.
The embodiment shown in Figure 38 is a battery checker for a timepiece. In the case where the detection level is set between 1.3 v and 1.5 V, a current flowing through Q7 has a positive gradient of temperature variation, and the difference ( band gap voltage = 1.1 V) of the threshold voltages of Q4 and Of has a negative gradient of temperature variation. Therefore, the dimensional ratio of the MOSFETs is set so that the conductance of Of may become smaller than the conductance of 04.
Figure 39 shows a high-precision reference voltage generating circuit of the voltage follower type utilizing an operational amplifier. N-channel MOSFETs of the P±gate and N±gate are used for Q4 and Of, respectively. Also, the conductances of the FETs are made different to produce an offset voltage. By adjusting a resistor R, outside an IC, a constant current flowing through a constant-current source Or is adjusted, to adjust the offset voltage. Thus, the fine adjustment of a reference voltage is made possible.
Alternatively, a Schmitt trigger circuit composed of MISFETs as shown in Figure 40(a) which has reduced the number of constituent elements has been proposed by one of the inventors (Japanese Patent Application No.52-147085 entitled "Schmitt Trigger Circuit" filed December9,1977).
The circuit shown in Figure 40(a) is such that two inverters are connected in cascade and that a MISFET (T3) forming a positive feedback circuit is provided between the input and output of the inverter on the output side. With this circuit, the width of a hysteresis curve (the difference of two logic threshold values VTL1 and VTL2) deviates due to variations in the supply voltage (VDD), the threshold voltages (Vth) of MlSFETs, etc.
Therefore, in such a case, where the circuit is applied to an oscillator whose output oscillates within the voltage width, there is the disadvantage that the frequency deviates.
The present invention employs MlSFETs formed by a method in which the threshold voltage of one (T2) of MISFETs constituting the first-stage inverter in Figure 40(a) is made higher than that of the other MISFET having the same conductivity type channel by a voltage component based on the difference of Fermi levels.
In this way, it is intended that the width of the hysteresis curve of the Schmitt trigger circuit (the difference of two logic threshold voltages) assumes a fixed voltage (a voltage substantially equal to the Fermi level difference) fluctuating little against the supply voltage, the manufacturing deviations of the MISFETs, temperature changes, etc.
This feature of the present invention will now be described using one embodiment as an example.
Referring to Figure 40(a), the Schmitt trigger circuit is constructed of an inverter 1 to which an input signal V is applied, an inverter 2 which receives an output of the inverter 1 as its input and which forms an output signal VOT and a MISFET T3 which is situated between an input terminal and a ground terminal of the inverter 2 and which is controlled by the output signal VO.
The MISFET T3 acts as positive feedback means of the output side inverter 2. The operation of positively feeding the input signal of the inverter 2 to the output signal is inseparable from the operation of the inverter 1 forming the input signal. The circuit operation is more easily understood when explained in terms of the input side inverter 1.
When the input signal Vj is at a high level (earth potential) the output of the input side inverter 1 is at a low level (-VDD) because the N-channel MISFET T, is "on" and the P-channel MISFET T2 is "off". The N-channel MISFET T4 of the output side inverter 2 receives this output of the input side inverter 1 and turns "off" and the P-channel MISFET If turns "on", so that the output of the output side inverter 2 is at the high level (earth potential). For this reason, the P-channel MISFET T3 drops into the "off" state.
When, in this condition, the input signal Vj is going to change to the low level, the output of the inverter 1 forms an output signal which is dependent upon the level of the input signal Vj and which is determined by the impedance ratio of the MlSFETs Ta, Tlr because the MISFET T3 is "off". The input level of the output side inverter 2 is changed from the low level to the high level.
Hence, when the output of the output side inverter 2 is changed from the high level to the low level and this output signal VO has exceeded the threshold voltage of the MISFET T3, the MISFET T3 starts the "on" operation. Due to the "on" operation of the MISFET 13, the output level of the input side inverter 1 is determined by the impedance ratio between the MISFET T and the parallel MISFETs 12,13, and it is shifted onto a higher level state. Thus the "on" operation of the MISFET T3, which is controlled by the output of the output side inverter 2, causes positive feedback, in which the input level of the output side inverter 2 is changed into the high level state, is applied to the input of the output side inverter 2.Then, the output signal VO changes abruptly. Hence, the logic threshold value VTL2 in Figure 40(b) is determined by the threshold voltage Vthn and Vth2 and mutual conductances p1 and P2 of the MISFETs Ti, T2 in Figure 40(a). That is,
Alternatively, when the input signal Vj is at a low level, the N-channel MISFET Ta of the input side inverter 1 is "off" and the P-channel MISFET T2 is "on", the H-channel MISFET Tq of the output side inverter is "on" and the P-channel MISFET T5 is "off", and the P-channel MISFET T3 is "on" due to the low level of the output signal VOI so that the output signal of the input side inverter 1 is determined by the impedance ratio between the MISFET T1 and the parallel MlSFEIsT2,I3.
Hence, in the period in which the input signal Vj changes from the low level to the high level, unless the input signal Vj becomes higher than the logic threshold voltage VTL2 in the preceding operation, the output signal of the input side inverter 1 does not change to the low level. However, once this output (the input signal for the output side inverter 2) has begun to change towards the low level and to change the output of the output side inverter 2 into the high level state, the impedance of the MISFET T3 changes to increase.
Therefore, the positive feedback in which the change of the output of the input side inverter 1, i.e. the input signal of the output side inverter 2 is promoted is applied, and the output signal VO changes abruptly. Hence, when the P-channel M ISFET 12 has its gate electrode formed of a semiconductor of the opposite conductivity type (N-type) to the conducitivty type (P-type) of the gate of the conventional P-channel MISFET T3 or formed of an intrinsic (i-type) semiconductor, it has a threshold voltage which is higher than the threshold voltage VTH of the ordinary MISFET T3 by a voltage corresponding to the difference of Fermi levels e.g. to the difference of the intrinsic level and the Fermi level, respectively.
Hence, the logic threshold voltage (VTL1) in Figure 40(b) is approximately expressed as follows:
62 = 3 is held by making the sizes of the MISFET T, and the MISFET T2 equal. Therefore, the difference (VTL2 - VTLi) of the two logic threshold values becomes:
Hence, the difference (VTL1 - VTL1) of the logic threshold values in Figure 40(b) assumes a fixed voltage which is proportional to the difference (Vth2 - Vth3) of the threshold voltages of the MISFET 2 and the MISFET 3, i.e. the difference of the Fermi levels of the gate electrodes of these MlSFETs 2 and 3.
One example of obtaining the voltage corresponding to the difference of the Fermi levels is to utilize the difference of the threshold voltages Vth of two MOSFETs having semiconductor gate electrodes which have different conductivity types and which are formed on gate insulating films formed on an identical semiconductor substrate by an identical process.
Figure 59 previously referred to represents conceptually the sectional structure of the respective FETs, and the structure can be fabricated by the MOS manufacturing process illustrated in Figures 73(a) - 73(f).
Subsequently for the sake of brevity, the MOS transistor whose gate electrode is made of a P±type semiconductor shall be called the "P+ gate MOS", and the MOS transistor whose gate electrode is made of an N±type semiconductor shall be called the "N+ gate MOS".
The difference (Vthp+ - VthN+) of the threshold voltages of the P+ gate MOS and the N+ gate MOS is the difference of the Fermi potentials of semiconductors making the gate electrodes as seen from Equation (16).
While the above description has been made by taking the P±channel MOS transistor as an example, the same applies in the case of an N±channel MOS transistor. Also, the same applies to the i-type gate MOS whose gate electrode is made of an intrinsic semiconductor.
Figure 41 shows a Schmitt trigger circuit according to another embodiment of the present invention. The difference between this and the embodiment of Figure 40(a) is that an input inverter 11 includes a P±gate P-channel depletion type MOS transistor 111 as a load, a P±gate P-channel enhancement type MOS transistor 112 as drive and an N±gate P-channel enhancement type MOS transistor 113 for feedback, and that an output inverter 12 includes a P±gate P-channel depletion type MOS transistor 114 as a load and a P±gate P-channel enhancement type MOS transistor 118 for drive.The embodiments both ensure that the difference of logic threshold values becomes a constant voltage proportional to the difference of the Fermi levels of the gate electrodes of the MISFET 12 and MISFET 13.
An oscillator will now be described as an example of an application of the Schmitt trigger circuit of the present invention.
Figure 42 is a circuit diagram of an oscillator to which the Schmitt trigger circuit of this invention is applied.
A part enclosed within dotted lines in Figure 42 is the Schmitt trigger circuit. An output of the Schmitt trigger circuit SIC becomes an input of an inverter 3, an output of which becomes an input of the Schmitt trigger circuit SIC.
When a supply voltage is closed, the potential of the point d approaches the potential -VDD gradually.
When it has exceeded the threshold voltage VTL2 of the Schmitt trigger circuit SIC, the potential of the point f changes to the earth potential, and the potential of a point g changes to the supply voltages -VDD~ Then, as the point g is the input of the inverter 3, a MISFET T4 turns "on", and the potential of the point d approaches the earth potential immediately. When the potential of the point d is below the logic threshold voltage VTL1 of the Schmitt trigger circuit SIC, the potential of the point f changes to the earth potential, and the voltage of the point g changes to the supply voltage -VDD.Therefore, the MISFET T4 of the succeeding inverter 3 turns "off", and the potential of the point d is charged according to a time constant CR which is determined by a resistor R and a capacitor C connected to the point d. When the potential of the point d gradually approaches the supply voltage -VDD and has exceeded the threshold voltage VTL2 of the Schmitt trigger circuit SIC, the potential of the point f changes to the earth potential, and the potential of the point g changes to the supply voltage -VDD. Subsequently, the inversions are similarly repeated to cause oscillation.Since the potential of the point d alternates between the two logic threshold voltages VTL1, VTL2 of the Schmitt trigger circuit SIC, the oscillation frequency of the oscillator is determined by the speed at which charges are stored into or discharged from the capacitor C by the resistor R or the MISFET 14. Assuming that the resistance R is sufficiently greater than the impedance of the MISFETT4, the oscillation frequency of the oscillator circuit is determined by only R and C, and the oscillation has a frequency which is stable against fluctuations in the supply voltage, temperature changes, manufacturing deviations, etc.
When the resistor R is mounted outside the integrated circuit, only one terminal suffices for the integrated circuit of the oscillator circuit, and stable oscillation can be achieved under such a condition.
The resistor R may be any of, a diffusion resistor, a resistor owing to a MISFET, etc. However, when a resistor of sufficiently small variation is formed in an integration circuit, the oscillator circuit can be entirely contained within such a circuit.
Figure 43 is a circuit diagram showing an example of an oscillator circuit using the Schmitt trigger circuit SIC as shown in Figure 41 in which the width of hysteresis is constant according to the present invention. A third inverter 3 is connected to the input of the Schmitt trigger circuit SIC, a fourth inverter 4 is connected to the output of the Schmitt trigger circuit SIC, and a resistor R and a coupling capacitor C for determining the oscillation frequency are connected to the input of the third inverter 3.
The threshold voltage Vth of MOSFETs which are discrete elements in a MOS integrated circuit form an important parameter which determines the characteristics of a Large Scale Integration device (herein referred to as LSI). The threshold voltage Vth shows large variations due to the manufacturing process and exhibits a large variation due to temperature changes, and the control of Vth is difficult in the manufacture of a Metal Oxide Semiconductor Large Scale Integrator (herein referred to as a MOSLSI).
According to the present invention, as shown by way of example in Figure 50, a bias voltage VBB is applied to the silicon substrate of a MOS memory IC to reduce parasitic capacitances. In order to obtain the bias voltage VBB, a substrate bias generating circuit SBGC is employed. The substrate bias generating circuit SBGC has an arrangement which is illustrated in Figure 47.
In the present invention, the comparator employing the difference of the work functions of the gate electrodes of MIS FETs as previously discussed is used in the substrate bias generating circuit SBGC to control Vth SO that it is a constant voltage.
Vth changes in dependence on the substrate bias VBB, and is expressed by the following equation: Vth = Vtho + K (2KF + V88! - 2 ##) where Vtho denotes Vth when the substrate bias voltage VBB is zero, K denotes the substrate effect constant, and pF denotes the Fermi level. Therefore, Vth may be controlled by varying the substrate bias VBB. The substrate bias voltage generating circuit SBGC shown in Figure 47, has a Vth sensing circuit 471, a comparator 472, an oscillator circuit 473 and a waveform shaping circuit 474. The oscillator circuit 473 may be replaced with a different oscillator circuit.The waveform shaping circuit 474 is composed of two MOS diodes Qq and Q2 and a capacitor C1, and it functions to drawing out charges of VBB to the earth point by a pumping action. Owing to the pumping action, VBB is drawn towards a negative voltage. The maximum voltage VBBM of IVBBI is determined by the point at which the drawing-out voltage owing to the pumping action and the substrate leakage current are stabilized. Provided the oscillation circuit is operating, VBB is held at the stable point VBBM. After the oscillation ceases, however, the charges of the substrate leak due to the substrate leakage current and V88 approaches the earth potential.When VBB has become close to the earth potential, Vth lowers.
The comparator circuit 472 shown in Figure 47, exploits the difference of the Fermi levels of the gate electrodes, and an example in the N-channel process is shown in Figure 21. The comparator circuit 472 employs an intrinsic silicon gate MOS as Qn in Figure 21, and an N gate MOS as 02. These are depletion type MOS. Therefore, this comparator inverts when a voltage of Eg/2 = 0.55 V has been put into an inverting input (-). The Vth sensing circuit 471 in Figure 47 is composed of a resistance and a diode-connected MOSFET 03.
The resistance may be either a polycrystalline silicon diffused layer resistance or a MOS resistance, and the resistance value is set so that an output may become 0.55 V when Vth of Q3 has become 0.55 V. When the substrate bias voltage V88 is close to the earth potential and Vth of Q3 is below 0.55 V, the (-) input voltage of the comparator circuit falls below 0.55 V, the output of the comparator becomes "1" and the oscillation circuit continues to operate. When the substrate bias voltage V88 approaches VBBM and Vth rises and exceeds 0.55 V, the comparator output becomes "0", the oscillation ceases and the substrate bias voltage V88 becomes close to earth potential due to the leakage.Hence, since a feedback loop is formed, Vth is controlled at the stable point by this substrate bias generator circuit SBGC. The voltage 0.55 V obtained in the comparator portion 472 is 1/2 of the energy gap, which fluctuates little with temperature changes, manufacturing dispersions and supply voltage fluctuations. Therefore, it becomes possible to control Vth with a very high precision, and a MOSLSI with a wide temperature margin, manufacturing process margin and power supply margin is obtained. As will be discussed later, the intrinsic silicon gate MOS Q1 of the comparator portion 472 can be obtained by an identical process to that for obtaining a high resistance load R in a memory cell shown in Figure 51,so that the control of Vth can be readily achieved with the prior-art process.
In an embodiment where a 5 V power supply is employed as a power source in a MOSLSI and where signals from a TTL logic circuit are employed as inputs, the outputs of the TTL logic circuit become 2.0 V as a high level and 0.8 V as a low level. In converting the TTL signals into the MOS levels, it has previously been necessary to take the ratios of inverts in an input portion and to convert them into the MOS levels. However, there is the problem that the input level margin becomes small due to the variation of Vth and temperature changes.
Figure 45 shows a TTLX -, MOS signal level converter circuit which employs the reference voltage Vref generated from the reference voltage generating circuit utilizing the difference of the Fermi levels of the gate electrodes as previously described. The signal level converter circuit in Figure 45 is preferably applied to the address buffer circuits XAB and YAB of the MOS memory shown in Figure 50. As the reference voltage Vref, a reference voltage of 1.4 V is generated by the previously discussed reference voltage generating circuit of Figure 15. A differential amplifier employing MOSFETs in Figure 44 is employed as an amplifier, AMP in Figure 45, and an input buffer in which the logic threshold voltage of an input is 1.4 V equal to the reference voltage Vref is prepared.With this method, a TTLe MOS signal level converter circuit may be obtained.
Alternatively, a signal level converter circuit which has the logic threshold voltage of 1.4 V can be obtained by employing the circuit shown in Figure 13 as the amplifier, AMP in Figure 45. The inphase input (+) O is earthed as shown in Figure 14, and an address signal Ao - A4 is applied to the antiphase input (-). Depletion type MOS FETs are used for the transistors T, and 12. By making the threshold voltages Vth, and Vth2 of the respective FETs unequal, the operational amplifier is provided with an input offset voltage of 1.4 V.
The circuit in Figure 46 is intended to hold the logic threshold voltages of logical circuits, such as an inverter, constant against changes in the serve supply voltage, the threshold voltages of MOS transistors, temperature changes, etc.
An inverter 1 composed of FETs Q2 and Q3 and an inverter 2 composed of Of and Of are provided with MOS FETs Q, and Q4 respectively for controlling the logic thresholds.
A logic threshold detector circuit 3 which is composed of a controlling MOSFET Q7 and an inverter Of, Of with its input and output coupled is constructed to be similar to the inverters 1 and 2 described above (the pattern size ratios of MOSFETs are equal). Due to the coupling of the input and output of the inverter Of, Of, the logic threshold voltage is obtained.
CMP1 indicates the comparators circuit previously discussed with reference to Figures 13 and 14 which has the reference voltage Vref as the offset of the differential circuit. The comparator circuit CMP1 compares the logic threshold and the reference voltage and controls the gate voltage of the controlling MOSFET 07 SO that the difference of both the voltages may become substantially zero.
Thus, if the logic threshold is greater than the reference voltage Vrn', the output of CMP1 is at a high level, and the equivalent resistance of Q7 increases and this transistor functions to lower the logic threshold. In case where the logic threshold is less than the reference voltage Vref, the converse is true. Both the voltages fall into the equilibrium state when they are equal.
The gate voltages of the controlling MOSFETs Q, and Q4 are connected to the gate voltage of the controlling MOSFET 07, and the former transistors and the latter transistors have a similar relationship.
Thus, the logic thresholds of the inverts 1 and 2 become equal to the reference voltage, and very stable inverter characteristics are exhibited.
This is not restricted only to inverters, but is similarly applicable to the other logical circuits such as NAND and NOR.
It is readily applicable to the case of inverters and the like logical circuits of ordinary single-channel types, not the CMOS construction.
These circuits are useful as input interface circuits which can digitally process signals reliably especially when the ranges of input levels and logic amplitudes are narrow.
Examples in which the reference voltage generator means according to the present invention is applied to a status setting circuit (an auto-clear circuit) for electronic devices will now be discussed.
Figure 48 is a circuit diagram showing an example of a status setting circuit, which is a flip-flop circuit constructed of two inverters each including two MOSFETs. Referring to the Figure, in case where potentials at points a and b are zero, both the MOSFETs T, and T3 change to the "ON" state when a power supply -VDD is applied because they are N-channel MOSFETs. Simultaneously with the application of the supply voltage, the potential points a and b changes towards the supply voltage -VDD. At this time, the Fermi levels of the gate semiconductors of the N-channel MOSFETs Tq and T2 differ from each other, and the threshold voltage Vth3 of the MOSFET T3 is about three times greater than that Vtha of the MOSFETT, (for example: Vtha = 0.45 V, Vth3 = 1.25 V).Therefore, during a drop in the supply voltage, the MOSFET 13 turns "OFF". Since the MOSFET T continues to be in the "ON" state, the points b and a are respectively stabilized at -VDD and the earth potential.
In the case where, with the power supply -VDD disconnected, the potential of the point a is zero and charges remain at about 1 V at the point b, T3 is in the "OFF" state till VDD equals Vth3 during the drop in the supply voltage, and the MOSFET T1 changes to the "ON" state at VDD equals Vth. Therefore, even when the potential of the point a has been zero and the potential of the point b has been about one volt (or up to VthN of T3) in the initial state, the potential of the point b becomes VDD and the potential of the point a becomes zero in the stable state. Also, since all the FETs are constructed of E(enhancement)-MOSFETs in the present circuit, the current consumption in the stable state is almost zero.
Figure 49 is a circuit diagram which shows an embodiment of a status setting circuit which has been proposed in the prior art. Referring to the Figure, the threshold voltage Vth of MOSFETs T2 and T4 are equal to each other, and an N-channel D (depletion)-MOSFET T, is inserted to increase the stability of a latch circuit.
Due to the D-MOSFET, when the power supply -VoD is applied, the potential of the point a falls simultaneously with the power supply without exception, and the point b does not turn "ON" unless the supply voltage falls to Vth of the MOSFET T4,SO so that the potential of the point a and the potential of the point b become -VDD and zero respectively in the stable state. Since, however, the D-MOSFET is inserted between the point a and -VDD in the present circuit, the P-MOSFET T3 turns "ON" when the state in which the potential of the point b is -VDD and the potential of the point a is zero (RESET) is subsequently established and a D.C. path due to Ti and T3 arises to cause a high current consumption.In contrast, with the status setting circuit of the present invention as shown in Figure 48, the status setting can be achieved reliably and the current consumption is very low as described above, and hence, effective status setting means can be provided.
An embodiment in which the present invention is applied to a semiconductor random access memory (RAM) will now be described.
In general, in a storage device constructed of a static RAM, voltage control to lower a supply voltage is performed in order to reduce power dissipation at the time when the storage device is not used (stand-by status). This is called the data retention mode.
In this case, a signal voltage is lowered simultaneously with the supply voltage. Since a power supply line has a greater time constant than a signal line, the signal voltage lowers to a predetermined value more rapidly. Usually, in a semiconductor RAM, a store control signal is set at a supply voltage level, a recall control signal at a reference voltage level, and a chip select signal at a reference potential level.
In the data retention mode, therefore, the level of the control signal lowers faster than the supply voltage, so that the store control signal becomes the recall control signal level instantaneously and that the chip select signal is formed. For this reason, the recall operation is effected instantaneously, and the information of a bit selected at that time is destroyed.
In order to solve this problem, in a RAM constructed of field-effect transistors of a single channel, it is possible to provide a time constant circuit to make the time constant of the signal line greater. With this measure, however, an external circuit is required, and the control signals are adversely affected.
In a C-MOS (complementary MOS) integrated circuit, a p-n-p-n element is frequently formed due to its structure. Therefore, when the signal voltage is made greater than the supply voltage, such a p-n-p-n element operates, and a large current flows between the supply voltage and the reference potential. For this reason, a time constant circuit in which the signal voltage and the supply voltage are lowered at the same time must be used for the C-MOS memory.
These facts are serious problems in the design and manufacture of storage devices when considering the use of memory chips.
It is therefore desirable that a circuit for sensing the lowering of the supply voltage is contained in the same chip as that of the RAM. However, MOSFETs on the semiconductor chip have temperature dependence of threshold voltage Vth, manufacturing variations, etc., and it has been difficult to obtain a detection voltage necessary for sensing with high precision.
This aspect of the present invention will be described below.
Figure 52 is a block diagram of a static type semiconductor memory integrated circuit device showing an embodiment of the present invention.
In the Figure, there is shown a memory matrix (64 x 64 bits) circuit 1 which is constructed of static memory cells. An X-decoder circuit 2 discerns an information pattern assigned by a row select signal (Ao - A4) and applied through a buffer circuit BX, to assign a row (X) line of 1/64. A Y-decoder and input/output circuit 3 discerns an information pattern assigned by a column select signal (A8 - Af) and applied through a buffer circuit BY, to assign a column (Y) line of 1/64. It also gives the assigned column line of the memory matrix 1 an input data applied through gates WB. It also provides an output data from the assigned column line to terminals (1/01 - 1/04) through gates RB. An input data control circuit 4 gives the input/output circuit the input data to-be-recalled.Also shown are input/output terminals (1/01 to 1/04) and a chip select signal CS, which indicates the selection of this chip by the "0" level i.e. reference potential level. A store/recall control signal WE controls the recall operation when it is at the "0" level i.e. the reference potential level, and the store Operation when it is at the "1" level i.e. supply voltage level. Gate circuits 5, 6 are alternately controlled by the control signals. Thus only when the CS is "0", are the gate circuits controlled by either "0" or "1" of WE, to execute the store or recall operation.
A voltage detector circuit 7 detects the data retention mode when the supply voltage has fallen below a predetermined voltage, and it controls the gate circuit 5 to inhibit the signal WE at that time. Thus, the malfunction as previously described is prevented. An example of the arrangement of the voltage detector circuit 7 is shown in Figure 53(a).
Resistors R1, R2 connected in series form a circuit for dividing a supply voltage Vc. The voltage divider circuit applies a divided voltage a to the gate of an N-channel MISFET Q2 The supply voltage Vcc is applied to the gate of an N-channel MISFET 04.
A MISFET Q5 has its gate supplied with a suitable bias voltage from d, and constructs a constant-current source. It forms an operational amplifier, together with load MISFETS Q1 and Q3 and the two differential input MISFETs Q2 and 04.
The differential input MISFETs Q1 and O4 are formed on, for example, N-type silicon layers of equal conductivities, and the respective gate electrodes are made of different materials so that the threshold voltages may become unequal. The gate electrodes of the two MISFETS Q2 and Q4 are made of, for example, silicon, and their conductivity types are made different. The MISFET Q2 has an N-type silicon gate, whereas the MISFET 04 has a P-type silicon gate. As a result, the threshold voltage Vth4 of the MISFET O4 becomes greater than the threshold voltage Vth2 of the MISFET Q2 by the difference between the Fermi levels of the P-type and N-type silicon gates.
Hence, the operation amplifier has an offset voltage equal to the difference of the threshold voltages.
If the supply voltage Vcc is comparatively large in the circuit of Figure 53(a), the MISFET 04 iS in the "on" state and 02 iS in the "off" state, and the potential of a point c is at a low level. Due to lowering of the supply voltage Vct, the potential of the point a changes as indicated by a curve a in Figure 53(b). When, due to the lowering of the supply voltage Vcc, the potential difference between the supply voltage Vcc and the potential of the point a has become smaller than the offset voltage, the MISFET 04, changes to the "off" state and Q2 changes to the "on" state. In consequence, the potentials of the points b and c in the circuit of Figure 53(a) change as indicated by curves band c respectively in Figure 53(b).Thus, the potential of the point c is at a high level when the supply voltage Vcc has lowered to a predetermined value.
As described above, the detection level of the circuit of Figure 53(a) is determined by the offset voltage created by the MISFETs Q2 and Q4 and the divided voltage created by the resistors R1 and R2. It is not affected by the threshold voltages of the respective M ISFETs.
The offset voltage is known with a comparatively high precision because it is determined by the difference between the Fermi levels of the gate electrodes of the two MISFETs Q2 and O4 as discussed previously.
Since, in a semiconductor integrated circuit, the relative values of the resistances of resistor elements are known with a comparatively high precision, the voltage division ratio created by the resistors R1 and R2 is known with a comparatively high precision.
As a result, the detection level of the circuit of Figure 53(a) can be set comparatively accurately.
In Figure 53(b), a waveform d' indicates the output of the gate circuit 5 during the data retention mode during which the gate circuit 5 is not controlled by the detection output.
In the data retention mode, the input control signals CS and WE lower faster than the supply voltage Vcc of the gate circuit 5. Therefore, when the difference of both the voltages has become above the logic threshold, the output waveform d' is generated as stated above. This is the cause of the malfunction explained previously.
According to the circuit of the present embodiment, however, the control signal c is applied to the input of the gate circuit 5, so that the waveform d' is inhibited from being provided. Thus, erroneous recall in the data retention mode can be prevented, and data stored in the matrix memory are not destroyed.
In accordance with the embodiment described above, erroneous recall in the data retention mode can be prevented. Moreover, the detector circuit can be constructed with a simple circuit arrangement and can be contained in the memory chip. It is therefore unnecessary to care for the prevention of malfunctions on the side of the user of the semiconductor memory device.
For example, the gate circuit which is controlled by the voltage detection output may obtain the chip select signal. All the memory cell select signals may be inhibited so as to select no memory cell.
This is because erroneous recall can be prevented when one of conditions necessary for the execution of the recall operation is inhibited.
The voltage divider circuit which constitutes the voltage detector circuit in the previous embodiment may utilize resistance by means of MISFETs instead of the resistor elements. Preferably, the resistance of this voltage divider circuit is made large to make the power dissipation low.
The two MISFETs of the foregoing embodiment which have silicon gate electrodes of conductivity types opposite to each other are fabricated within a silicon monolithic semiconductor integrated circuit chip. Since these FETs are manufactured under substantially the same conditions except the conductivity types of the gate electrodes, the difference of the threshold voltages Vth of both the FETs becomes approximately equal to the difference between the Fermi levels of P-type silicon and N-type silicon. The P-type and N-type gate electrodes are doped with respective impurities to the vicinities of the saturation densities, and the difference becomes approximately equal to the energy gap Eg of silicon (about 1.1 V), which is used as a reference voltage source.
The reference voltage generating device based on such a construction has a low temperature dependence and the manufacturing deviations are small.
The voltage detector circuit 7 can be modified in several ways.
The reference voltage sources which uses the difference between the Fermi levels of semiconductors forming the gate electrodes of two MOS FETs as shown in Figure 6(b), Figure 8, Figure 9, Figure 10(a), Figure 11(a), Figure 12, Figure 13, Figure 14, Figure 15, Figure 16 and Figure 17 can be used as the reference voltage source for the voltage detector circuit of the present invention.
To achieve this two FETs can be used which have semiconductor gate electrodes of different conductivity types as already explained with reference to Figure 59, for example, a MOS transistor with its gate electrode made of a P+ -type semiconductor or a P -gate MOS transistor and a MOS transistor with its gate electrode made of an N+ -type semiconductor or an N + -gate MOS transistor. As already described with reference to Figures 73(a) to 73(f), the above two FETs can be manufactured, without the change or addition of any step by the conventional CMOS manufacturing process.
If the conventional CMOS manufacturing process is used, the self-alignment structure as shown in Figures 65(a) and 65(b) and Figures 66(a) and 66(b) is obtained as discussed below. Since the MOS transistors are of the P-channel type in this case, a P-type impurity is diffused into both end parts of a gate electrode adjoining the source and drain in both the P±gate MOS and the N±gate MOS. In a central part of the gate electrode, a P-type impurity is diffused for the P±gate MOS, and an N-type impurity is diffused for the N±gate MOS.
Between the central region and both the end parts adjoining the source and drain, there are regions i in which no impurity is diffused. Thus, the difference of the P±gate MOS and the N±gate MOS is only the conductivity type (P or N) of the semiconductor forming the central region of the gate.
Also, in order to reduce the deviation (difference) of the effective channel lengths of the MOS transistors due to the fact that the regions of the gates which are formed for the self-alignment and in which the P-type impurity is diffued, shift onto either the left or right side (source side or drain side) during manufacture due to an error in the mask alignment, the columns of the source regions and the drain regions are alternately arranged, and the left half and the right half are in a linear symmetry with respect to the channel direction as a whole. Hence, even when the misregistration of the mask alignment with respect to the channel direction (leftward or rightward shifting) changes the effective channel lengths of the FETs in the respective columns, the average effective channel lengths of the P±gate MOS and the N±gate MOS in the respective columns connected in parallel have the shifting cancelled out overall and become substantially constant.
Besides by making the compositions of the gate electrodes different, unequal threshold voltages are achieved by ion implantation into channels as described with reference to Figure 7, by utilizing a doped gate oxide, by changing the thickness of gate insulating films, etc.
Figure 54 shows an embodiment in which the battery checker of the example of Figure 20 is applied to an electronic timepiece.
Tq, 12,141 to T49 and R41 and R42 form a circuit which checks the voltage level of a mercury battery E1 having a nominal voltage of 1. 5 V. A transistor pair Ta, T2 in a differential portion is constructed from a gate N-channel MOS Tq and an N+ gate N-channel MOS T2, the channel portions of which are subjected to ion implantation so that the threshold voltages of both the transistors lie within 1.0 V to 1.5 V, being the operating power supply range of the electronic timepiece.
The difference of the threshold voltages to serve as a reference voltage is about 1. 1 V in the case of a silicon semiconductor. In order to set a level for detecting that the voltage of the battery E1 has lowered at about 1.4 V, an adjustment is made by altering the resistance ratio of the resistance means R41 and R42.
In order to make the current consumption negligible in practical use, the battery checker is intermittently operated by a clock signal ~ which is obtained from a frequency divider circuit FD and a timing circuit TM.
An output of the battery checker is held stable by a latch which is composed of NAND gates NA1 and NA2.
The timing circuit TM is controlled by the logic level of an output from the latch circuit, the driving output of a motor is changed and the method of moving a hand of the timepiece is changed so as to indicate the lowering of the battery voltage. The lowering of the battery voltage can also be indicated without changing the movements of the hand, for example, by flickering of an electrooptic device such as a liquid crystal or light emitting diode.
As shown in Figure 54 a crystal oscillator circuit OSC is constructed of a CMOS inverter and also includes components outside the IC, a crystal Metal and capacitors CG and CD. A waveform shaping circuit WS converts the oscillation output from a sinusoidal wave into a rectangular wave. Also shown an excitation coil CM of a step motor for driving the second hand and buffers BF1 and BF2 which are constructed of CMOS inverters and which serve to drive the excitation coil CM whilst inverting the polarities every second.
All the circuits within the IC are operated by the mercury battery E1 of nominal 1. 5 V. TM is the timing pulse generator circuit which receives a plurality of frequency division outputs of different frequencies from the frequency divider circuit FD and the control output of the latch composed of NA1 and NA2 and which generates pulses having any desired period and pulse width. The IC is a monolithic Si semiconductor chip for a hand-type electronic wrist watch which is constructed by the Si gate CMOS process already explained with reference to Figures 73(a) - 73(f).
Figure 55 shows another embodiment of the construction of a circuit system for an electronic wrist watch containing a battery checker. In this embodiment, the conductances of FETs Q4 and Of of a differential circuit are made unequal as in Figure 39, and the detection level can be finely adjusted by means of an adjusting resistor Rj outside the IC.
Due to the resistor RJ, variations in manufacture can be avoided in use.
An embodiment in which the voltage regulator as shown in Figure 36(a) is applied to an electronic timepiece will now be explained with reference to Figure 56.
In Figure 56, there is shown a crystal oscillator OSC, a waveform shaping circuit WS which converts a sinusoidal wave oscillation output into a rectangular wave, a frequency divider circuit FD, a timing pulse generator circuit TM which prepared pulse of predetermined period and width from frequency division outputs, a level shift circuit LF which converts a signal of low level into a signal of high level, a battery lifetime detector BC, a voltage comparator VC, a voltage regulator VR which uses the voltage comparator VC, a hold circuit H, an oscillation state detector DT, and an excitation coil of a step motor LM for driving a second hand.
The detector DT detects that the oscillator OSC has oscillated through the frequency divider FD and the timing circuit TM. If oscillation has occurred the detector DT actuates the voltage regulator VR to lower the operating voltage Vop of the oscillator OSC and WS, FD, TM etc. to a value below the battery voltage (-1 .5V).
The moment the battery E is turned "on", the input node of an inverter 17 has earth potential (logic "0") due to a discharging resistor R104, so that an N-channel FET Q201 is brought into the "ON" state and the output of the regulator is made -1.5 V, being the battery voltage. At this time, a FET Q203 is also turned "ON", and the gate node of a FET 0202 is charged. This makes the negative feedback loop of the regulator active to prevent the regulator output dropping the moment the FET Q201 is subsequently switched "OFF".
When the oscillator has started operating, the other logical circuits are already in the operative state, so that a pulse ~B is supplied from the timing circuit TM to the detector DT. An exclusive OR circuit EX, detects the generation of the pulse ~B One input of the OR circuit EX1 receives the pulse ~B delayed by inverters 14 and 15 and an integration circuit C101 and R103. When the pulse ~B is generated, a pulse of a width corresponding to the delay time is generated at the output of the gate EX,.This pulse is integrated by a rectifier circuit made up of a FET Q225, an inverter 16 and a capacitor C102, and turns "OFF" the N-channel FETs 0201 and Q203 after a short time from the generation of ~B Thus, the regulator VR generates a predetermined voltage (less than 1.5 V) at the source electrode of the controlling P-channel FET 0202 by the negative feedback control loop, and it contributes to reduce the power dissipation of the electronic timepiece.
The operation of the regulator, especially the voltage comparator VC, will now be explained. Since this comparator VC effects an operation similar to that of the comparator CP described with reference to the principle diagram of Figure 35(a) and the characteristic diagram of Figure 35(b), only a brief explanation will be given.
Considering the P-channel MOSFETs Q206 and 0207r in order to obtain the offset voltage V0ff, the gate of Q206 is P-type as in Q1 of Figure 60 and Figures 67(a) and 67(b), and the gate of Q207 is i-type (intrinsic semiconductor) as in Q2 of Figure 60 and Figures 68(a) and 68(b).Hence, the threshold voltage Vth of Q207 becomes higher than that of Q206 by about 0.55 V, which provides offset voltage Voff. However, since both an N-channel FET Q208 and a P-channel FET Q209 are diode-connected, the sum of both the threshold voltages Vth i.e. (Vthp,, + Vthn208) is applied to the gate of Q207 being the non-inverting input (+) of the comparator VC, and the sum serves as the voltage Vref2 as indicated in the curve din Figure 35(b). Also the gate of the FET Q206 being the inverting input (-) of the comparator is connected to the source of the controlling P-channel FET Q202 of f e the source-follower type.
Hence, the output voltage Vout of the voltage regulator VR which is generated at the source of the controlling FET Q202 under the control action of this controlling FET Q202 driven by the comparator VC, becomes Vout = Vthp,, + Vthn2aa + AVoff (in case where Vjn = Vthp + Vthn + AVoff). When the input voltage Vjn is low, the output voltage becomes Vout = Vjn as previously described. Of course, the output voltage Vout of the voltage regulator VR is used as the operating voltage Vop of the oscillator OSC as well as WS, FD, TM, etc.
In order to keep the power dissipation low, this comparator has the operating time limited by a timing signal Q;A provided by the on-off operation of the driven FET 0211. This also applied to the circuit for obtaining the reference voltage Vref2. To achieve this, a capacitor C104 is connected to the gate of Q207 and a capacitor C108 is connected to the gate of Q202 to store the voltage of the reference voltage Vref2 and to store the gate voltage of 0202 respectively. These capacitors C104 and C105 are added separately from parasitic capacitances such as gate capacitances. A capacitor C103 serves to prevent any oscillation created by a phase rotation caused by the cascade connection of several FETs in the feedback loop.
Since the battery checker BC has a construction similar to that in Figure 54, the explanation of this device is omitted.
At the output stage of the IC, drivers 12 and 13 for the excitation coil use the battery of 1.5 V as a power supply to make the driving capacibility high.
Figure 57 shows an embodiment in which the voltage regulator VR and the battery checker BC according to the present invention are applied to a digital display electronic timepiece.
In Figures 57, parts OSC, WS and FD use an adjusted voltage lower than 1.5 V as a power supply similarly to the example of Figure 56, and also logical circuits within an IC such as decoder DC and time correction circuit TC use the lower voltage as a power supply.
A voltage doubler circuit DB boosts the voltage of 1.5 V to 3.0 V, which is used as a drive voltage for a liquid crystal display DP (a driver is not shown). Level shift circuits LS1, LS2 convert a low DC signal level into a high one and supply it to circuits of high supply voltages.
To render the power dissipation low and to expand the service power supply range it is necessary that the low operating power supply is used for the ordinary logical circuits within the IC which operate at low operating voltages, while the high operating power supply is used for the display driver etc. at an input/output interface of the IC which require high operating voltages.
Attention is drawn to Application No. 79.07817 (Publication No. 2,016,801) from which this application has been divided in which there is claimed a reference voltage generating device.
Attention is also drawn to the following Divisional Applications: DIV. I Application NO. 81. 19559 (Publication No.2,081,014) in which the claims relate to a method of manufacturing a semiconductor device; DIV. II Application No. 81. 19560 (Publication No. 2,081,015) in which the claims relate to a method of manufacturing a semiconductor device; DIV. IVApplication NO. 19562 (Publication No. 2,081,458) in which the claims relate to a battery checker.

Claims (10)

1. A reference voltage generating device including: an operational amplifier including first and second insulated gate field-effect transistors (IGFETs) which have a difference of threshold voltages corresponding to a difference of Fermi levels of gate electrodes thereof, both said gate electrodes of said first and second IGFETs being made of an identical semiconductor material but having different conductivity types, a gate of said first IGFET being used as an inverting input of said operational amplifier whilst a gate of said second IGFET is used as a non-inverting input of said operational amplifier, an output terminal for delivering an output signal in response to a potential difference between said inverting and non-inverting inputs, and an input which is offset corresponding to said difference of threshold voltages;; a feedback connection means connected between said inverting input and output terminals of said operational amplifier for applying an output signal at said output terminal of the operational amplifier to said inverting input terminal thereof; and a reference connection means for applying a reference potential to said non-inverting input terminal of the operational amplifier, whereby the reference voltage based on the difference of said threshold voltages of said first and second insulated gate field-effect transistors is derived between said output terminal of said operational amplifier and said reference potential.
2. A reference voltage generating device according to Claim 1, wherein said feedback connection means includes a controlling amplifier element having its control electrode coupled to said output terminal of said operational amplifier, its first output electrode, coupled to a power supply terminal, and its second output electrode coupled to said inverting input of said operational amplifier.
3. A reference voltage generating device according to Claim 2, wherein said second output electrode of said controlling amplifier element is coupled to said inverting input of said operational amplifier through a voltage divider means which is connected to said output electrode of said controlling amplifier element.
4. A reference voltage generating device according to Claim 1, whrein said feedback connection means includes a voltage divider connected between said output terminal of said operational amplifier and said reference potential for applying a divided voltage of the output voltage appearing at said output terminal to said inverting input terminal.
5. A reference voltage generating device according to Claim 1 or 2, wherein said second insulated gate field-effect transistor is of the depletion type.
6. A reference voltage generating device according to any one of the preceding claims, wherein said operational amplifier includes a third insulated gate field-effect transistor (IGFET) which is commonly coupled in series with drain-source paths of said first and second IGFETs, said third IGFET being driven by a timing signal, whereby during the conductive state of said third IGFET a stabilized output voltage is derived from said output terminal of said operational amplifier.
7. A reference voltage generating device according to any one of the preceding Claims 1 to 5, further including: a first constant current source connected in series with the source-drain path of said first insulated gate field-effect transistor; and a a second constant current source connected in series with the source-drain path of said second insulated gate field-effect transistor.
8. A reference voltage generating device according to any one of Claims 2, 3, 5 and 6, wherein said controlling amplifier element is a fourth insulated gate field-effect transistor (IGFET).
9. A reference voltage generating device according to any one of Claims 2, 3, 5 and 6, wherein said controlling amplifier element is a bipolar transistor.
10. A reference voltage generating device constructed substantially as herein described with reference to and as shown in Figures 14, 15, 16, 17,27, 28,34, 35a, 39 and 56 of the accompanying drawings.
10. A reference voltage generating device constructed substantially as herein described with reference to and as shown in Figures 14, 15, 16, 17,27,28,32,33,34, 35a, 39 and 56 of the accompanying drawings.
New claims or amendments to claims filed on 26th July, 1982 Superseded claims 1 and 8 New or amended claims :-
1. A reference voltage generating device including: an operational amplifier including first and second insulated gate field-effect transistors (lGFEIs) of the same conductivity type which have a difference of threshold voltages corresponding to a difference of Fermi levels of gate electrodes thereof, both said gate electrodes of said first and second IGFETs being made of an identical semiconductor material and having a threshold determining portion of types selected from P, N and intrinsic, so as to provide said difference of Fermi levels thereof, the impurity concentrations of the semiconductor material of said P and N types being higher than 1018 cm-3 respectively, a gate of said first IGFET being used as an inverting input of said operational amplifier whilst a gate of said second IGFET is used as a non-inverting input of said operational amplifier, an output terminal for delivering an output signal in response to a potential difference between said inverting and non-inverting inputs, and an input which is offset corresponding to said difference of threshold voltages: a feedback connection means connected between said inverting input and output terminals of said operational amplifier for applying an output signal at said output terminal of the operational amplifier to said inverting input terminal thereof; and a reference connection means for applying a reference potential to said non-inverting input terminal of the operational amplifier, whereby the reference voltage based on the difference of said threshold voltages of said first and second insulated gate field-effect transistors is derived between said output terminal of said operational amplifier and said reference potential.
GB8119561A 1978-03-08 1979-03-06 Reference voltage generators Expired GB2100540B (en)

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Application Number Priority Date Filing Date Title
GB8119561A GB2100540B (en) 1978-03-08 1979-03-06 Reference voltage generators

Applications Claiming Priority (12)

Application Number Priority Date Filing Date Title
JP2544478A JPS54119653A (en) 1978-03-08 1978-03-08 Constant voltage generating circuit
JP3554578A JPS54129348A (en) 1978-03-29 1978-03-29 Constant voltage output circuit
JP3924278A JPS54132753A (en) 1978-04-05 1978-04-05 Referential voltage generator and its application
JP11171778A JPS5539605A (en) 1978-09-13 1978-09-13 Reference voltage generation device
JP11172078A JPS5539608A (en) 1978-09-13 1978-09-13 Reference voltage generation device
JP11171978A JPS5539607A (en) 1978-09-13 1978-09-13 Reference voltage generation device
JP11171878A JPS5539606A (en) 1978-09-13 1978-09-13 Reference voltage generation device
JP11172278A JPS5539411A (en) 1978-09-13 1978-09-13 Reference voltage generator
JP11172578A JPS5539413A (en) 1978-09-13 1978-09-13 Schmitt trigger circuit
JP11172478A JPS5539412A (en) 1978-09-13 1978-09-13 Insulating gate field effect transistor integrated circuit and its manufacture
JP11172378A JPS5538677A (en) 1978-09-13 1978-09-13 Semiconductor memory with function of detecting power failure
GB8119561A GB2100540B (en) 1978-03-08 1979-03-06 Reference voltage generators

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GB2100540A true GB2100540A (en) 1982-12-22
GB2100540B GB2100540B (en) 1983-06-02

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2543363A1 (en) * 1983-03-25 1984-09-28 Efcis Analog integrated circuit with MOS transistors with electrical adjustment of the threshold voltage of at least one transistor
EP0154337A2 (en) * 1984-03-06 1985-09-11 Kabushiki Kaisha Toshiba Transistor circuit for semiconductor device with hysteresis operation and manufacturing method therefor
EP0367707A2 (en) * 1988-10-31 1990-05-09 International Business Machines Corporation A circuit arrangement for adjusting offset voltages associates with operational amplifiers
EP0452675A2 (en) * 1990-03-15 1991-10-23 Fujitsu Limited Buffer circuit for logic level conversion
EP1515433A1 (en) * 2003-09-05 2005-03-16 Monolithic Power Systems, Inc. Controlled offset amplifier
CN114217661A (en) * 2021-11-02 2022-03-22 深圳市创芯微微电子有限公司 Ultralow-power-consumption voltage reference circuit and electronic equipment

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2543363A1 (en) * 1983-03-25 1984-09-28 Efcis Analog integrated circuit with MOS transistors with electrical adjustment of the threshold voltage of at least one transistor
EP0154337A2 (en) * 1984-03-06 1985-09-11 Kabushiki Kaisha Toshiba Transistor circuit for semiconductor device with hysteresis operation and manufacturing method therefor
EP0154337A3 (en) * 1984-03-06 1987-11-11 Kabushiki Kaisha Toshiba Transistor circuit for semiconductor device with hysteresis operation and manufacturing method therefor
EP0367707A2 (en) * 1988-10-31 1990-05-09 International Business Machines Corporation A circuit arrangement for adjusting offset voltages associates with operational amplifiers
EP0367707A3 (en) * 1988-10-31 1991-03-20 International Business Machines Corporation A circuit arrangement for adjusting offset voltages associates with operational amplifiers
EP0452675A2 (en) * 1990-03-15 1991-10-23 Fujitsu Limited Buffer circuit for logic level conversion
EP0452675A3 (en) * 1990-03-15 1992-01-08 Fujitsu Limited Buffer circuit for logic level conversion
EP1515433A1 (en) * 2003-09-05 2005-03-16 Monolithic Power Systems, Inc. Controlled offset amplifier
CN114217661A (en) * 2021-11-02 2022-03-22 深圳市创芯微微电子有限公司 Ultralow-power-consumption voltage reference circuit and electronic equipment

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