JPS6121515A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To attain generation of a reference voltage with less fluctuation due to temperature change by constituting an MOS diode where a drain and a gate are connected in common by an MISFET so as to attain ease of design and mass- production of an electronic circuit. CONSTITUTION:T1, T2 are MISFETs to constitute the MOS diode where the drain and gate are connected in common. Further, the T1, T2 have different threshold voltages and nearly equal mutual conductances and a difference of the threshold voltage is extracted by taking the difference of drain voltages V1, V2. Moreover, the difference of the Fermi level of N and P channel semiconductors nearly equal to the difference of the threshold voltages is extracted by using an N gate MOS and a P gate MOS. Thus, the design and mass-production of the electronic circuit is attained easily and a reference voltage where the fluctuation of voltage and temperature change is small is generated.

Description

[Detailed description of the invention] The present invention relates to a semiconductor integrated circuit device.

In various semiconductor electronic circuits, in order to generate a reference voltage, it is essential to use a physical quantity that has the dimension of voltage. Until now, the physical quantities have mainly been the forward voltage drop VF and reverse breakdown voltage (Zena voltage) of PN junction diodes, and insulated gate field effect transistors (IG, FET, MO, 5FE).
(often represented by T) 9 threshold degrees C. value voltage Vth, etc. are used.

These physical quantities do not indicate absolute voltage values, and the voltage values are subject to fluctuations depending on various factors. Therefore, in order to utilize these physical quantities as a reference voltage generating device for various electronic circuits, it is necessary to pay attention to the fluctuation factors of the obtained voltage value and the permissible fluctuation range.

First, regarding the temperature characteristics of these physical quantities, the above v
F and vth usually have a temperature dependence of about 2 to 3 nV/C, and the temperature change in the reference voltage that accompanies this temperature change can be so large that it has to be abandoned for practical use depending on the application. Extends.

For example, if you want to create a battery checker for an electronic watch that uses a nominal 1.5-inch silver oxide battery to warn that the battery voltage has dropped,
It is necessary to judge whether the battery voltage is high or low, with the boundary (detection level) being about 1.4V.

This is the MOSFET threshold voltage Vt of approximately 0.6V.
If you try to configure it using the diode's forward drop voltage, the detection level with a target of 1.4V will have a temperature dependence, and the practical operating temperature range will be OC to 50C.
Even if we make a narrow estimate, the voltage will fluctuate widely between 1.23V and 1.57V, so it cannot be used as a practical battery checker.

Next, regarding manufacturing variations in these physical quantities, MQS
The threshold voltage Vth of I"ET has a variation of about ±0°2V, and this variation is larger than the temperature change. Therefore, the above-mentioned battery checker was made into an IC (integrated circuit) using Vth. In this case, not only external parts and connection pins (terminals) for correcting the reference voltage but also adjustment after the IC is manufactured are required.

In addition, the Zener voltage (2) has a low voltage limit of about 3V, which is inappropriate as a reference voltage for use in the low voltage range of about 1 to 3V. To use as a voltage, the number
It is necessary to flow a current of about mA to several tens of mA, which is inappropriate in terms of reducing power consumption.

As is clear from the above explanation, conventional reference voltage generators using vth y VF and In many cases, practical application and mass production had to be abandoned for applications requiring extremely strict characteristics.

Note that a reference voltage generating circuit using MOSFETs with different electrode materials is disclosed in Japanese Patent Laid-Open No. 149780/1983.

The inventors of the present invention learned from the above studies that there are physical limits to the improvement of conventional reference voltage generators, and decided to research and develop a reference voltage generator with new ideas and ideas.

The purpose of the present invention is to provide a reference voltage generation circuit based on a completely new idea not seen in the past, and to provide a reference voltage generation circuit based on a completely new idea that has not been seen before.
The aim is to facilitate industrialization.

Another object of the present invention is to provide a reference voltage generator with small temperature changes.

Another object of the present invention is to keep fluctuations in the obtained voltage values small with respect to fluctuations in manufacturing conditions, such as manufacturing variations between lots (
It is an object of the present invention to provide a reference voltage generating device with a small deviation).

Another object of the present invention is to provide an integrated circuit reference generator that can reduce manufacturing variations to the extent that post-manufacturing adjustments are not required.

Another object of the present invention is to provide an integrated electronic circuit device including a reference voltage generating device that can be manufactured with a large margin of tolerance to target specifications.

Another object of the present invention is to provide an integrated electronic circuit device including a reference voltage generator with high manufacturing yield.

Another object of the present invention is to provide a reference voltage generator suitable for IGFET integrated circuits.

Still another object of the present invention is to provide a reference voltage generator and a voltage comparator that consume less power.

Another object of the present invention is to provide a reference voltage generator capable of obtaining a low voltage (1.1 V or less) with excellent accuracy.

Another object of the invention is that it is compatible with relatively low voltage power supplies (approximately 1 to 3 cm), such as 1.5 cm silver oxide cells and 1.3 cm mercury cells. An object of the present invention is to provide a reference voltage generator.

Another object of the present invention is to provide a reference voltage generator suitable for semiconductor integrated circuits.

Another object of the present invention is to provide a highly accurate voltage comparator, regulated power supply, constant current line, and battery checker.

Another object of the present invention is to provide a semiconductor integrated circuit device for an electronic watch that has a built-in highly accurate battery checker and has a small number of external terminals.

Another object of the present invention is to provide a reference voltage generator compatible with a complementary insulated gate field effect transistor integrated circuit (CMO8IC) and a method for manufacturing the same.

The present invention has been made by going back to the origins of semiconductor physical properties, and paying particular attention to the energy gap Eg, Fermi level Ef, etc.

That is, the semiconductor has an energy gap Eg, a donor,
It is well known that semiconductors have various levels such as acceptor and Fermi levels, but since the discovery of semiconductors, a reference voltage generator has been developed that focuses on the physical properties of these semiconductors, especially the energy gap Eg and Fermi level Ef. Until now, it has made remarkable progress in a wide range of fields, and has never been seen before.

In terms of results, the present inventors considered using this energy gap Eg, Fermi level Bf, etc. as a reference voltage source, and succeeded in realizing it. Using energy gap Eg, Fermi level Ef, etc. as a reference voltage source is not a difficult theory in itself, and the results are easy to understand and accept. However, in the field of the semiconductor industry, which no longer has a short history, this successful example, which is believed to be unprecedented, brought about by the present inventors, returning to the origins of semiconductor physical properties, is original and groundbreaking, and will continue to be used in the future. It is expected that this technology will greatly contribute to the further development of the electronic circuit and semiconductor industries.

According to one embodiment of the present invention, two IGFEs, T, with different conductive particles of silicon gate electrodes are fabricated within a silicon monolithic semiconductor integrated circuit chip. These FEs
Since T is manufactured under almost the same conditions except for conductive dust on the gate electrode, the difference in VthO between the two is approximately equal to the difference in Fermi level between P-type silicon and N-type silicon. Each gate electrode is doped with each impurity near the saturation concentration,
This difference is the energy gap Eg of silicon (approximately 1,
IV), which is used as a reference voltage source.

A reference voltage generating device based on such a configuration has low temperature dependence and small manufacturing deviation, so it can be used as a reference voltage generating device for various electronic circuits.

The present invention and further objects thereof will be more clearly understood from the following description with reference to the drawings.

Numerous documents explain the physical properties of semiconductors, starting from the crystal structure of semiconductors and extending to the energy band of semiconductors and the phenomena caused by donor and acceptor impurities in semiconductors.

It is of course well known that semiconductors of different compositions each have a specific energy gap E8, and that the energy gap Eg, expressed in eV, has the dimension of voltage. However, as mentioned above, there has never been an example in which a semiconductor has an inherent energy gap E8 and this temperature dependence is small, and this is used as a reference voltage source.

Since this embodiment was developed starting from the basics of semiconductor physical properties, a detailed explanation of the present invention will first start from the fundamentals of the present invention with reference to the physical properties of semiconductors. The physical properties of semiconductors are explained in detail in many documents, and the following is one of them, S.

“Physics of Sem1” by MIISZE
conductorDevices”, 1969Jo
Published by hn Wiley & 5ons, especially Cha
pter 2″Physics and Prop6r
tiesof Sem1conductors-A
A brief explanation will be provided with the help of "Resume" page 11' page 65.

There are various compositions of semiconductors, but among them, the typical semiconductors currently used industrially are germanium (Ge) and silicon (Sl). These are non-compound semiconductors and galycum arsenic (GaAs) compound semiconductors. The relationship between the energy gap Eg and temperature is explained on page 24 of the aforementioned book, and is reproduced in FIG. 1.

As understood from Fig. 1, the Eg of Ge, Si and GaAs is 0.80 (eV), tt2 (eV) and 1.43 (at room temperature (3000K), respectively).
eV). Moreover, the temperature dependence is 0.
39 (m e VloK), o, 24 (m e V
/K) and 0.43 (m e V/'K). Therefore, by extracting a voltage corresponding to or close to these energies + 0 gap Eg, the temperature dependence of the forward voltage drop VF of the PN junction diode and the threshold voltage Vth of the IGFET described above can be reduced by one order of magnitude. Thus, a reference voltage generator having a small temperature dependence can be obtained. Furthermore, the voltage obtained is determined by the energy gap Eg specific to the semiconductor; for example, in the case of Si, it is approximately 1.
12 (V) and is determined almost independently of other factors, making it possible to obtain a reference voltage that is not easily affected by variations in manufacturing conditions and the like.

Now, an example will be explained based on which principle the voltage corresponding to the energy gap Eg of this semiconductor can be extracted.

The state of energy levels when a semiconductor is doped with donor and acceptor impurities is well known. In particular, what we have focused on in this invention is that the Fermi energies of N-type and P-type semiconductors are located at 2 points toward the conduction band and valence band, respectively, based on the Fermi energy level E1 of the intrinsic semiconductor. It is a physical property of being separated. The higher the concentration of acceptor and donor impurities, the higher the Fermi level Ei of the intrinsic semiconductor.
The Fermi level Ef of the P-type semiconductor tends to be further away from
p approaches the highest level Ev of the valence band, and the Fermi level Efn of the N-type semiconductor approaches the lowest level Ec of the conduction band, and if we take the difference between both Fermi levels (Efn - Efp), we get this. becomes closer to the energy gap Eg of the semiconductor, and its temperature dependence also becomes closer to that of the energy gap Eg. Although the details will be described later, the higher the impurity concentration, the smaller the temperature dependence of (Efn''fp), and it is preferable to set the concentration as close to the saturation concentration as possible.

The Fermi level Efo* Efp is related not only to the concentration of donor and acceptor impurities but also to the donor and acceptor units Ed and Ea, and this level Ed, Ea
varies depending on the impurity material. The closer the levels Ed and Ea are to the conduction band and valence band, respectively, the lower the Fermi level E
fd and Efa also approach each other. In other words,
The shallower the impurity levels Ed and Ef of the donor and acceptor, the closer the Fermi level difference (Efn-Efp) becomes to the energy gap E8 of the semiconductor.

Donor and acceptor impurity levels Ed.

The closer Ef is to the Fermi level E1 of the intrinsic semiconductor, that is, the deeper it is, the farther the Fermi level difference (Efn-Efp) is from the semiconductor's energy gap Eg. However, this does not necessarily mean that the temperature dependence becomes worse, but rather the Fermi level difference (Ef
This means that the absolute value of n - Efp becomes smaller. Therefore, the Fermi level difference (Efn-Efp)
is unique to semiconductor materials and impurity materials, and from another perspective, it can serve as a reference voltage source along with the gap E2, which is in a different category from the semiconductor energy gap E8. In other words, the Fermi level difference (Efn-Efp
) itself is the forward voltage drop vF and I of the PN junction.
It has less temperature dependence than the threshold voltage Vth of a GFET, and can serve as a reference voltage source that is less affected by manufacturing variations. (Efn −Ef
p ) can be one way to extract a voltage that is approximately close to the energy gap °Eg of the semiconductor. On the other hand, when it comes to setting the voltage value to be obtained, if the purpose is to obtain a relatively large reference voltage equivalent to the energy gap of a semiconductor, an impurity exhibiting a shallow level is used, and a relatively large reference voltage is used. If the purpose is to obtain a small reference voltage, an impurity exhibiting a deep level may be used.

Fermi level Ef, donor level Ed, acceptor level E
. , donor concentration 1'td, acceptor concentration Na, and temperature T will be explained in more detail with reference to Figs. 2 and 3. In order to understand what level each impurity exhibits and how to utilize these impurities in the present invention, the above-mentioned document No.
The data on the page is reproduced as Figure 4 and an explanation is added.

FIGS. 3(a), Φ) and (C) are Ge.

It is a figure showing the energy distribution of various impurities with respect to Si and GaAs, and the numbers in each figure are the lowest level E of the conduction band for the level located above the center E1 of the gap represented by the broken line. The energy difference between (
Eo-Ed), and for the lower level, the energy difference from the uppermost level Ev of the valence band (Ea-E
V), and the unit is (eV).

Therefore, the unit of impurity materials indicated by small numbers in the figure is the lowest level E of the conduction band. Alternatively, it indicates that it is close to the uppermost level Ev of the valence band, and is suitable as an impurity that obtains a voltage close to the energy gear E8. For example, for Si, which is currently widely used, the level difference (Eo-Ed) of donor impurities of Li, Sb, P, As, and B1 and acceptor impurities of B, A, 6, and Ga is , (Ea-Ev) is the smallest, and each level difference is the energy of Si.
It is about 6% or less of the gap Eg.

The Fermi level difference (Efd ``'fa) between N-type Si and P-type Si using these impurities is approximately 94% to 97% of the energy gap Eg of Si, if the temperature change from OK is ignored. %, which is approximately equal to Eg.Also, the next smallest level difference ("c") of the above impurity is
The donor impurity exhibiting S(Ed) and (Ea-Ev) is S(E
(approximately 16% of g), and the acceptor impurity is In(E',
(approximately 14% of O
It is about 0.85E at K, and the energy of Sl is
It can be seen that the deviation of the gap E8 is as much as about 15%, and the deviation becomes extremely wide due to the above-mentioned impurities.

Margin below i/ Therefore, one donor impurity selected from the group of Li+Sb, P*As and Bi is used as the impurity material for P-type and N-type Si to obtain a voltage approximately equal to the 8-dish energy gear knob E8. One acceptor impurity selected from the group B, A[ and Ga is preferred; other impurities would be suitable for the purpose of obtaining voltages significantly smaller than the energy gap E8 of Si.

Physical Properties of Fermi Level Ef Next, the physical properties of the Fenopé level difference (Efn-Ef, ) will be explained with reference to FIG. Figure 2 is a diagram showing the energy levels of semiconductors; Figures (a) and (b) respectively show the energy level model of an N-type semiconductor and its temperature characteristics; Figures (c) and (d) Each shows an energy level model of a P-type semiconductor and its temperature characteristics.

Carriers in a semiconductor are generated from electrons nd generated by ionization of the donor impurity Nd and the valence band.
1515(6) is an excited electron and hole pair. Impurity Nd
When is large enough, the excited electron and hole pairs can be ignored, and the number of conduction electrons n is n * n d
・It becomes (1). nd is determined from the probability of being trapped in the donor level, and n is determined from the number of electrons existing in the conduction band, respectively. Here, h' h: Blank constant, m*: Effective mass of electron From this, it becomes...(5).

Here, since the Fermi level is determined to be at a position close to EC, the first term of equation (5) can be ignored.

This equation shows that when the temperature is low, the temperature dependence is approximately equal to the temperature characteristic of Eo.

However, when the temperature is high enough, the number of pairs of electrons and holes excited from the valence band becomes large, and the influence of impurities becomes small, and the Fermi level becomes the level E of an intrinsic semiconductor. The above relationship is shown in FIG. 1(b).

The same is true for a P-type semiconductor containing only acceptor impurities as shown in Figure 1(c); at low temperatures and when the acceptor impurity concentration is high, the Fermi level is
It is located approximately between the top of the valence band and the acceptor level, and as the temperature increases, it approaches the Fermi level of an intrinsic semiconductor.

This relationship is shown in FIG. 1(d).

The relationship between the temperature characteristics of the Fermi level Ef and the impurity concentration - Specific examples We have explained the physical properties of the relationship between the temperature dependence of the Fermi level Efp j Efn and the impurity concentration. As a specific example of 81 semiconductors,
The Fermi level difference (Efn-Efp) and its temperature dependence in practical use will be explained with reference to the data on page 37 of the aforementioned book. The data is reproduced in Figure 3.

In the normal SJ semiconductor integrated circuit manufacturing process, boron B and phosphorus P are mostly used as impurity materials, and in areas where the impurity concentration is high, 101020 (ato/
m3), but the impurity concentration is two orders of magnitude lower than that of 101.
8 (atoms10rn3), as can be read from FIG. 3, the Fermi level difference (Efn-Efp) between the N-type semiconductor and the P-type semiconductor is 0.8 at 300'K.
5-(-□, 5)-1.0 (eV), which is a value relatively close to the energy gap Egsu1.1 eV at the same temperature. The change with temperature is 4 from 200'K.
Approximately 1.0 in the range of 00°K (-70°C to 130°C)
4 (eV) to 0.86 (eV), and the rate of change is 0.9 (mV/'C). This is the I mentioned earlier
The rate of change of GFET threshold voltage th and diode forward drop voltage vF with respect to temperature is 2 to 3 mV/℃
This is a small value of about 1/3 compared to .

If the impurity concentration is 1020 cyx-3 or higher, the silicon energy gap (Eg) is approximately equal to Si = 1.1 (v), and the rate of change in temperature is approximately 0.2 in V /
”C, which is a sufficiently small value.

Therefore, if the impurity concentration is about IQ18 (1 m-3 or more), it is possible to obtain a temperature dependence that is 1/2 to 1/3 smaller than the conventional one, and more preferably 1020 m-3 or more.
or higher (improved to about 1/10), and most preferably saturation concentration.

In Zen and the actual example, on what principle can the voltage corresponding to the Fermi level difference (Efn-Efp) be extracted? Two MOSs with semiconductor gate electrodes
This method utilizes the difference in threshold voltage Vth of the FETs. A specific example will be explained below. .

FIG. 5 shows a conceptual cross-sectional structure of each FET. Hereinafter, for the sake of simplicity, a MOS transistor with a gate electrode of a P+ type semiconductor will be referred to as a P+ MOS transistor, and an MQS transistor with a gate electrode of an N+ type semiconductor will be referred to as an N+ gate MO8. Figure 6 shows the above P+Goo) MOS and N+Dag-MOS in the general CMOS manufacturing process.
MOS does not require any changes or additions to the final process (,
FIG. 2 is a cross-sectional view of the main steps that demonstrate what can be manufactured.

This figure shows the cross-sectional structure of a P-channel MO8) transistor.

In Fig. 7, in order to obtain a self-aligned structure,
At both ends of the gate electrode in contact with the source and drain, there is a P+ gate MOS because it is a P-channel MOS transistor in this case.

P impurities are diffused into both N+Ga and MOS transistors. In the center of the gate electrode, a P-type impurity is diffused for a P+GMOS and an N-type impurity is diffused for an N+GMOS. A region (2) in which no impurity is diffused is provided between the central region and both ends in contact with the source and drain, and the difference between P+GMOS and N+GMOS is simply the region at the center of the gate. Care has been taken to ensure that the semiconductor is only a P-type semiconductor and an N-type semiconductor.

Furthermore, the P-type impurity diffusion region of the gate, which was taken for self-alignment, was biased to one side (source side or drain side) during manufacturing due to mask alignment errors. The rows of source and drain regions are arranged alternately so that the deviation (change) in the effective channel length is minimized, and the left and right halves are symmetrical with respect to the channel direction. It is arranged like this. Therefore, even if the mask alignment (left and right) deviations in the channel direction change the effective channel length of the FETs in each column, the average effective channel length of the parallel-connected P+ gate MOS and N+ gate MOS in each column The channel length becomes almost constant as the deviations are canceled out as a whole.

Figure 6 shows how P+1-MOS and N+
This also shows how MO8 is configured.

(In figure a1, 101 is N for specific resistance 1Ω bacteria to 8Ω melting.
type silicon semiconductor, with a thermal oxide film 102 on it at 40°C.
It is grown to about 0x to 16,000x, and windows for diffusion are selectively opened using photoetching technology. Boron, which becomes a P-type impurity, is implanted at 50 K e V to 200 I (eV energy in an amount of about 1011 to 1010 l3'-2, and then thermally diffused for about 8 to 20 hours to form an N-channel MOS) transistor. The substrate P-
A well 103 is formed.

(b) In the figure, the thermal oxide film 102 is removed, a thermal oxide film 104 is formed with a thickness of about 1 μm to 2 μm, and the regions that will become the source, drain, and gate of a MOS transistor are removed by etching. Thereafter, a gate oxide film 105 of about 3008 to 1500 Å is formed.

On top of that, polycrystalline Si 106 is placed at 2000A~600(1
It is then removed by etching, leaving only the gate portion of the MOS transistor.

(In Figure c1, an oxide film 107 is formed by vapor phase growth, and a region where P-type impurities are diffused is removed by photoetching. Then, 1020 to 102101n-3
Boron, which becomes a P-type impurity, is diffused at a high concentration to form the source of a P-channel MO8) transistor.

A drain region 108 is formed, and at the same time a gate electrode of a P-type semiconductor' is formed.

(d) In the figure, an oxide film 1 is formed by vapor phase growth as before.
09 is formed, and the region in which the N-type impurity is diffused is removed by photoetching. After that, 1020~IQ”0
Phosphorus serving as an N-type impurity with a high concentration of about 171-3 is diffused to form the source and drain regions 110 of the N-channel MOS transistor, and at the same time form the gate electrode of the N-type semiconductor.

(e) In the figure, the oxide film 109 is removed, an oxide film 111 of about 4000A to 8000A is formed by vapor phase growth, and the electrode lead portion is removed by photoetching. Thereafter, a metal (A[) is deposited, and electrode wiring portion molecules 12 are formed by photoetching.

(f) In the figure, 1 μrrL to 2 μm by vapor phase growth.
covered with an oxide film.

Next, the gate uses a semiconductor as an electrode. The threshold voltage of the MOS transistor will be explained with reference to FIG. First, in the case of a P+ gate MOS, the energy band diagram of FIG. 8(a) shows that φM φ5.

However, here ■. ; Potential difference X between the semiconductor substrate and the gate electrode (p+ semiconductor); Electron affinity, E8; Energy gap φ5; Surface potential of the N-type semiconductor substrate φF'P"; P-type semiconductor based on the Fermi potential of an intrinsic semiconductor Fermi potential φF; Fermi potential q of the N-type semiconductor substrate based on the Fermi potential of the intrinsic semiconductor; unit charge of an electron ■o; potential difference Eo applied to the insulator; lower limit Ev of the energy level of the conduction band; Upper limit El of the energy level of the valence band: Fermi level of the intrinsic semiconductor (in the method, the work function of the gate electrode is expressed as a potential and is φMP0, and the work function of the semiconductor is similarly φ81. , Vo=-V, +φyaφ8□-φ3...(
10).

Also, from the charge relationship shown in Figure 8(b), COX ・Vo + Qss +Q 1 +QB =
O-・, -01).゛Here, co'x; capacitance of the insulator per unit area Qssv fixed charge in the insulator QB; fixed charge Qi due to ionization of impurities in the semiconductor substrate; carriers formed as a channel α0), (from +11 -COX( 'Vc+φMP+-φ8-φ5.f)+Q
s B + Q i +QD= O...(l).

Gate voltage when channel Qi is formed■. is the threshold voltage, so in this case, φ8-
=2φ.

Similarly, in the N+ gate MOS transistors, the only difference is the work function φMN+ of the gate electrode. Therefore, its threshold voltage VthN+ is now φ
It becomes 8-2φF.

From this, the difference between the threshold voltages of P+ gate MO8 and N+ gate MO8, vthp'''thN+, is vthp+V
ilIN"'l'MP"-φMN""φFP"-φFN
+...06) ・This is the difference in the Fermi potential of the semiconductors forming the gate electrode. This is shown in Figure 8 (a
) and (c), it can be easily understood that the gate voltage when the charge distribution is the same is the difference in the work function of the gate electrodes, which is the difference in the Fermi level.

The above explanation is based on the example of a P-channel type MO8) transistor, but the same applies to the case of an N-channel type MO8) transistor.

Next, a circuit for extracting the difference in Vth of MO8) transistors will be explained.

The circuit explained below is based on the Fermi level difference (Ef) mentioned above.
This can be one way to extract n-Efp), but other methods generally include FETs with different Vth (7)
It can be applied as a reference voltage generator that uses the voltage as a reference voltage based on the difference in vth.

FIG. 9(b) shows a circuit that generates a voltage corresponding to the threshold voltage of the MO8 transistor. T, IT2 is a so-called MOS whose drain and gate are connected in common.
It constitutes a diode.

1 is a constant current source, T, , T2 is a different threshold voltage t
h1. ■It is a MOS FET with mutual conductance β almost equal to th2, and each drain voltage is set to V,
, V2 is 1, = -β(V+ -■th+)2, so V+ = vthx + firy5te (181
V2 = Vthz + J'2〒, /I'
-(I'll, and if we take the difference in drain voltage,
The difference in threshold voltage can be extracted.

As a constant current source, you can use a sufficiently large resistor, and as long as it has the same characteristics, you can use a diffused resistor.

Polycrystalline Si resistor, resistor made by ion implantation,
MO3) A resistor based on a transistor can be used.

In this circuit, if the N+Ge) MO8 and P+Ge1-MO8 explained earlier as TI and T2 are used, the Fermi level of the N-type semiconductor and the P-type semiconductor will be approximately equal to the difference in threshold voltage. The difference (Efn - Efp) can be extracted.

In addition to changing the composition of the gate electrode, it is also possible to create a different threshold voltage by, for example, implanting ions into the channel, doping the gate oxide, changing the thickness of the gate insulating film, etc. , if this is applied to the circuit shown in Figure 9, the difference in threshold voltage corresponding to the amount of ion implantation, the threshold voltage depending on the amount of impurity doped into the gate insulating film and the thickness of the gate insulating film. The difference between can be similarly extracted as a reference voltage.

For example, it is well known that in the ion implantation method, the implantation amount can be monitored in the form of current, so the accuracy of impurity concentration is extremely good compared to normal diffusion. Figure 10 shows this situation. It is. M before ion implantation
Assuming that the characteristics of an OS transistor is T, there are individual variations during manufacturing, the threshold value changes by △Vth after ion implantation, and even if each individual is balanced, the difference in threshold voltage between the two is ΔVth has extremely little variation because it is determined by the amount of ion implantation (and can also be used as a reference voltage with little manufacturing variation; in other words, a MOS without ion implantation). 151, and if the increment in the defined charge of the substrate due to ion implantation is ΔQB, then the threshold voltage Vthz of the ion implanted MOS range metal T2 is as follows. The temperature change in this threshold voltage difference voltage is ΔQ
B is extremely small because it remains constant against temperature changes.

Another great advantage is that the reference voltage can be freely changed depending on the amount of ion implantation, and that it can be easily realized even in a single channel MOS manufacturing process.

Below is the margin ~ Ma
9 Figure 11 and Figure 1
Figure 2 shows the MOS FE'P with different threshold 1 direct voltages.
This is an example of a circuit that connects a diode in series and extracts the difference in threshold voltage. T is the threshold voltage ■tl
, 1. It is assumed that T2 has a threshold voltage Vth2.

Resistor R2 is sufficiently thick compared to the impedance of T (
, under the condition that the resistance R2 is sufficiently large compared to the impedance of T2, "-■2÷■tht',""'f2
3) V1÷v1h2 (2
4) Therefore, ■2 ÷” t h 2 ... group (20 hl).

Figure 13 (al) applies a voltage corresponding to the threshold voltage to both terminals of the capacitor and extracts the voltage held in the capacitor as a differential voltage. Figure 13 (tht) shows the operation timing. The clock pulse φ turns on T, , T, and charges the capacitor C1 with the difference voltage between the threshold voltages Vthl and th2 of T1 and T2.

After φ1 is cut off, T3 is turned on by clock φ2 and C
Ground the node ■ of I. At this time, since the differential voltage between the threshold voltages is held in C1, that potential is output as is to the node (2). When used in a voltage detection circuit as described later, the potential of node (2) at this time can be used as it is as a reference voltage. In order for T
6. If T7 is turned on, the potential is taken into the capacitor C2, and the output is fully fed back to the negative phase input (-) of the operational amplifier 5, so-called a voltage follower. In the low state, T1
, T2 is obtained as a reference voltage.

FIG. 14 shows a reference voltage generating device that similarly utilizes the capacitor C2. T is turned on by clock φ1. At this time, T9 is in an off state due to clock φ2. The potential of node ■ is T, the threshold voltage of ■th□ is higher than the potential of node ■.
The potential of node ■ is T2 lower than the potential of node ■.
is lowered by the threshold voltage ■th, and the difference voltage between the two is charged across the capacitor C. Next, φ, T8
When T9 is turned off and T9 is turned on by φ2, a voltage difference between the threshold voltages is obtained at node (2).

FIG. 15 shows a known operational amplifier used in the circuit of FIG. 13. T, , T2 are a differential pair constituting a differential amplifier circuit, and T5+T6 is an active load thereof. T7 constitutes a constant current circuit together with a bias circuit formed by T3 and T4. T6 and T7 are level conversion/cover sofa circuits in which T is a constant current source load. The figure shows an example of a C-MOS circuit configuration,
Single gear 1. It goes without saying that it can also be configured with MO8.In this operational amplifier, the differential pairs T, , T2 that make up the differential amplifier circuit are given different threshold voltages by the method described above. By having thl th2 , the difference between the threshold voltages can be used or extracted as a reference voltage, and this is an application of an operational amplifier that has not been seen in the past.

FIG. 16 schematically represents a general operational amplifier by taking only its differential part.
S) The transistors T, , T2 each have a different threshold voltage v.
thl, ■th2, and other characteristics are assumed to be equal. Further, the signs (-) and (+) appearing on the input side mean that the output is in opposite phase and in phase with the output, respectively.

If the input of T is V, and the input of T2 is v2, then ■, -
■th1-■2-■th2 That is, ■1-■2: ■th1
-■th2...The output level changes after the condition (26) is reached.

'An operational amplifier has an input offset equal to the difference between the threshold voltages, and if either two of its inputs are connected to ground or the power supply, it operates as a comparator using this offset voltage as the reference voltage. can be done. Therefore, as shown in FIG. 16, if the output is connected to the (-) input terminal and the +) input terminal is grounded, a difference in threshold voltage can be obtained at the output (out). In this case, in order to operate the operational amplifier, T2 must be in depletion mode. For example, when using P+Ge) MOS for T, and N+Ge) MOS for T2, both MO8F
It is sufficient to implant the molten metal into the channel part of 'ET under the same conditions to make it a depression type.

In FIG. 17, the reference voltage can be arbitrarily set using the operational amplifier in FIG. 16. If the output is fed back to the (-) input through the voltage dividing means R, , R6, and the voltage dividing ratio is r, the output voltage will be V. Hato becomes. The voltage dividing means R,,R, is preferably a linear resistance, but
Any resistor may be used as long as it has sufficiently uniform characteristics to be acceptable.

The circuits shown in Figures 16 and 17 are based on the use of a depletion type MO3, whereas the circuits shown in Figures 18 and 19 can also operate with an enhancement type MO8. . Of course, it is okay to be a depression type.

The example shown in FIG. 18 is similar to the example shown in FIG. 16, in which the output is directly fed back to the (-) input, and the output is ■. is the power supply voltage ■D
If D, ■. =■DD-(Vthyo-■th2) ・・・・・・-
(28). In the circuit shown in Figure 16.17, it is necessary to set one of the differential pairs to depletion mode, and depending on the case, the number of manufacturing steps may have to be increased. You can take it out.

On the contrary, the 18th. In the circuit shown in Figure 19, the reference for the obtained differential voltage is the power supply voltage that is not the ground potential, but there are no particular conditions for the operating mode of the FET.

Deciding which circuit type to adopt depends on its merits and demerits.

The example in FIG. 19 is the same as the example in FIG.
The output is fed back to the (-) input through the circuit, and the output is r.

Figure 20 shows how the reference voltage from a reference voltage generator that uses the difference in Vth is added to one input of the comparator, and the detected voltage is added to the other input, and the level of the detected voltage with respect to the reference voltage is distinguished. This is a voltage detection circuit that makes it possible to

In the example shown in FIG. 21, a reference voltage from a reference voltage generator using the difference in Vth is added to one comparator, and the detected voltage is divided into the other input by voltage dividing means Ro and R6. This is a voltage detection circuit that applies the same voltage.

Voltage division ratio is r, reference voltage is ref + detection level is Vse
nse, and the detection level 5ense can be arbitrarily set by the partial pressure ratio r.

The example in FIG. 22 uses an operational amplifier with a main off-set corresponding to the difference in Vth, and uses an off-off set as described above.
This is a voltage detection circuit that uses a set voltage as a reference voltage. Also R1. +R,2 is the same pressure dividing means as in the example of FIG.

In the example of Figures 20, 21, and 22, if the voltage to be detected is the power supply voltage, it can be used as a battery checker in a system that uses a battery as the power supply. 29 shows a specific example in which the voltage detection circuit shown in FIG. 22 is applied to a battery checker for an electronic watch, and a detailed explanation will be given later.

The example shown in FIG. 23 is applied to a stabilized power supply circuit. The reference voltage generation circuit is constructed using the several methods described above, and R1, R14 compares a part of the stabilized output with the reference voltage, and controls the gate voltage of T20 so that they match. , stabilize the output voltage. Any operational amplifier may be used as long as its characteristics are acceptable.

The example in FIG. 24 is T, in the example in FIG. A bipolar transistor TR1 is used in place of the MO8I-transistor used in the first embodiment.

The example shown in FIG. 25 uses an operational amplifier having the offset voltage shown in the example shown in FIG. T2. Of course, it may be a MO, S) transistor, a bipolar transistor, or a junction field effect transistor.

The example in FIG. 26 is a constant current circuit determined by the difference in threshold voltage between T and T.

T, , T2 have the same transconductance β, and have different threshold voltages vthl e Vth2.

If the resistance R20 is sufficiently high compared to the impedance of T1, the drain voltage (=gate voltage) of T1 is Vt
It becomes almost equal to hl.

When T2 is in the saturation region, the current I2 flowing through T2 is 1-1β(Vtht Vthz)'' --=
(31J, becomes 2.

In the example of FIG. 27, the voltage drop I due to the current I flowing through T22. This is a constant current circuit that compares ujR2 with a reference voltage Vref and controls the gate voltage of T1 so that both are always equal.

t ······Country becomes.

Here, the reference voltage may be obtained by providing an operational amplifier with an offset, as in the previous example.
28 is a constant current circuit using a so-called current mirror circuit in which T, , T, are the same transistors.

The example shown in FIG. 29 is an example in which the battery checker shown in FIG. 22 is applied to an electronic watch.

TI + T2 + T41 T49 and R4, and R4
2 constitutes a circuit for checking the voltage level of the mercury battery E1, which has a nominal capacity of 1.5 cm. The transistor pair in the differential section is set to P+
Gate/N channel-MOS, N+ gate/N channel-MO8T, 8. Ions are implanted into the channel portion so that the threshold voltages of both are within 1.0V to 1.5V, which is the operating power supply range of electronic watches.

The difference between the threshold voltages that serve as reference voltages is approximately 1.1V in the case of silicon semiconductors, and the resistance means R, , R2.

This battery checker operates intermittently using a clock signal φ obtained from the frequency divider circuit I''D through the timing circuit TM in order to reduce the current consumption to a practically negligible level.

The output of pantry checker is NAND gate NA,,
It is held statically by a latch composed of NA2, and the logic level of this latch circuit output controls the timing circuit TM, thereby changing the drive output of the motor, changing the method of hand movement, and changing the battery voltage. Show decline. A decrease in battery voltage can be indicated without changing the movement of the pointer, by blinking an electro-optical element such as a liquid crystal or a light emitting diode.

In the same figure, O8C is composed of a CMOS inverter, and components outside the IC include a crystal Xtal and a capacitor CG I C.
WS is a waveform shaping circuit that converts the oscillation output from a sine wave to a rectangular wave, CM is an exciting Koinope for the step motor that drives the second hand, BF, BF
2 is composed of a CMOS inverter and the excitation coil CM is
This is a buffer for driving by reversing the polarity every second.

All circuits in the IC are mercury batteries E with a nominal capacity of 1.5 .

It works. TM is a timing pulse generation circuit that generates pulses with arbitrary periods and pulse widths by inputting the divided outputs of the frequency dividing circuit FD with a plurality of different frequencies and the control output of the latch composed of NA, , NA2. be. The IC is a monolithic 81 semiconductor chip for a pointer type electronic wristwatch manufactured by the S1 game) CMO'S process shown in FIG.

The present invention has been described above based on various embodiments, but
The technical idea described herein is not limited to this, and may be applied to electronic devices for various other uses.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the energy gap E3 of GaAs, Si, and Ge semiconductors and its temperature dependence. The second part A is a diagram showing the band structure of the semiconductor and the Fermi level Ef.
l, (di indicates an example of a P-type semiconductor. Figure 3 is a diagram showing the temperature characteristics of the Fermi level of N-type and P-type Si with impurity concentration as a parameter. Figure 4 (al,
tbl and (C1 are diagrams showing the distribution of energy levels of Ge, Si, and GaAs semiconductors, and various donor and acceptor impurities, respectively. Figure 5 shows the difference in the Fermi level of N-type and P-type semiconductors ( E
fn-Efp), which can be used to retrieve P
The cross-sectional structures of + gate and N+ gate MO8FETs are schematically shown, with the left half being a P channel FET and the right half being an N channel FET.
A channel FET is shown. Figure 6 1al to 1(f) are P-channel FEs in which N+gate (B part) and bigate (A part) P-channel MO8FETs constitute a normal complementary MO8'.
T (C part) and N channel nasal FET (D part) and -
This indicates that they are manufactured together. It is a sectional view in a main process. Figure 7 shows a plan view and a cross-sectional view of a P-channel MO8FET.
+td+ shows a plan view and a cross-sectional view of a P+ gate P-channel MO8FET, and the line indicated by the arrow in each plan view is assumed to be the cutting line of the cross-sectional view. Figure 8 (al, (bl are respectively P+ type semiconductors -
The energy state and charge state of an insulator-N-type semiconductor structure are shown, and fcl and +dl in the figure are diagrams showing the energy state and charge state of an N+-type semiconductor-insulator-N-type semiconductor structure, respectively. Fig. 9 1al and tbl are a characteristic diagram of a MOS diode circuit for extracting the difference in Vth of two FETs having different threshold/value voltages Vth, and a diagram showing the circuit. FIG. 3 is a characteristic diagram showing how Vth changes. 11 and 12 each show an example of a reference voltage generation circuit that utilizes the difference in Vth, FIG. 13 1al shows an example of another reference voltage generation circuit, and +bl in the figure shows the timing signal waveform. show. 14 to 19 are based on other embodiments (reference voltage generation circuits are shown). The figure shows an example of application to a voltage regulator.
Figures 26 to 28 show examples of applications to constant current circuits.
Figure 9 shows an example of application to a battery checker for electronic wristwatches. T...MOSFET, R...Resistor, C...Capacitor Xta1...Crystal resonator, O20...Crystal oscillation circuit, WS...Sine wave-square wave conversion waveform shaping circuit,
FD...Binary power counter multi-stage connection frequency divider circuit, TM...
Timing circuit, CM...excitation coil for the step motor for driving the second hand, BF...buffer for driving the CM, N
A...NAND gate, IC...monolithic Si
Semiconductor integrated circuit chip, φ...clock pulse, Eg
...Energy gap of the semiconductor, Ev...The upper limit level of the valence band, EC...The lower limit level of the conduction band, E
i...Fermi level of intrinsic semiconductor, Efn, Efp・
・Fermi level of N-type and P-type semiconductors, Ed, Ea・
...Donor acceptor level. Fig. 1 Fig. 3 Fig. 9/I') Fig. 9 (tl-) (b) Fig. 11, Fig. 12 Fig. 13 Fig. 14 Fig. 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25

Claims (1)

[Claims] 1, T_1 and T_2 are MISFETs having gate electrodes made of different conductive particles, the sources of T_1 and T_2 are respectively connected to a first reference potential, and the gates of T_1 and T_2 are connected to their respective drains. 1. A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is connected to a second reference potential via a load means that is connected and switch-controlled by a clock, and further, the drains of T_1 and T_2 are connected to each other via a capacitor. 2. The gate electrodes of MISFET T_1 and T_2 are:
The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is of P (or N) type and N (or P) type. 3. The gate electrodes of MISFET T_1 and T_2 are P
The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is of the (or i) type and the i (or P) type. 4. The gate electrodes of MISFET T_1 and T_2 are N
The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is of the (or i) type and the i (or N) type.