JPS60252927A - Reference voltage generator and electronic device using said voltage generator - Google Patents

Abstract

PURPOSE:To obtain the reference voltage by connecting in a pair the 1st and 2nd insulated gate type field effect transistors having threshold voltages corresponding to the Fermi level difference of a gate electrode and supplying an output and a prescribed potential to the reverse input and the non-reverse input respectively. CONSTITUTION:MOS transistors T1 and T2 constituting a differential amplifier of an operational amplifier shown in a rough diagram have threshold voltage levels Vth1 and Vth2 according to the ion implanting amount, the amount of impurities doped into said gate insulated film and the thickness of said insulated film respectively. Both transistors T1 and T2 have the same characteristics excluding said threshold voltage levels. The output level changes centering on V1- Vth1=V2-Vth2, i.e., V1-V2=Vth1-Vth2, where V1 and V2 mean the input voltages V1 and V2 of reverse and non-reverse input T1 and T2 respectively. Therefore, the difference between both threshold levels is obtained at the output ''out'' by connecting the output to a reverse input terminal with the non-reverse input grounded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to electronic devices, and in particular to a reference voltage generator and its applications, as well as an insulated gate field effect transistor and its manufacturing method.

In various semiconductor electronic circuits, in order to generate a reference voltage, it is essential to use a physical quantity having the dimension of voltage. Until now, physical quantities such as the forward voltage drop vP of a PN junction diode, the reverse breakdown voltage (Zener voltage) Vz, and the threshold of an insulated gate field effect transistor (often represented by an IGFET or MOSFET) have been used. Value voltage Vth etc. are used.

These physical quantities do not indicate absolute voltage values, and the voltage values are subject to fluctuations depending on various factors. Therefore, in order to utilize these physical quantities as a reference voltage generating device for various electronic circuits, attention must be paid to the fluctuation factor and allowable fluctuation range of the obtained voltage value.

First, regarding the temperature characteristics of these physical quantities, the above v
F and Vth usually have a temperature dependence of about 2 to 3 nV/C, and the temperature change in the reference voltage that accompanies this temperature change is so large that it may be necessary to give up on practical use depending on the application. .

For example, if you want to create a battery checker for an electronic watch that uses a nominal 1.5-inch silver oxide battery to warn that the battery voltage has dropped,
It is necessary to judge whether the battery voltage is high or low with the boundary (detection level) at about 1.4■.

This is the threshold voltage Vt of MOSFET of about 0.6■
Or, if you try to configure it using the diode's forward drop voltage (2), the detection level targeted at 1.4 (2) will have a temperature dependence of 1.4 (2), and the practical operating temperature range will be OC~50C.
Even if we make a narrow estimate, the voltage will fluctuate widely between 1.23V and 1.57V, so it cannot be used as a practical battery checker.

Next, regarding manufacturing variations in these physical quantities, MOS
FET L threshold [pressure Vth)l: There is a variation of about 0.2 V, and this variation is larger than the temperature change. Therefore, when the above-mentioned battery checker is made into an IC (integrated circuit) using Vth, not only external parts and connection bins (terminals) for reference voltage correction but also the effort of p+ adjustment after IC manufacture are required. Become.

In addition, the Zener voltage v2 has a limit of about 3■ at low voltages, which is inappropriate as a deposition rate voltage used in the low voltage and pressure range of about 1 to 3■. In order to use the voltage drop as a reference voltage, it is necessary to flow a current of several mA to several tens of mA, which is inappropriate in terms of reducing power consumption.

As is clear from the above explanation, conventional reference voltage generators using Vth t VF and ■z are not necessarily suitable for all uses, considering variations in temperature characteristics, power consumption, voltage levels, etc. In many cases, it was necessary to give up on commercialization and mass production for applications that required extremely strict palatability.

From the above studies, the inventors of the present invention learned that there is a physical 'YC limit' to improving the conventional reference voltage generator, and decided to start researching a reference voltage generator with new ideas and ideas. Ta.

Regarding the voltage adjustment circuit, please refer to Japanese Patent Application Laid-open No. 48-63'25.
What is shown in Publication No. 7 is publicly known.

An object of the present invention is to provide a reference voltage generation circuit based on a completely new concept not seen in the past, and to facilitate the design and mass production of electronic circuits.

Another object of the present invention is to provide a reference voltage generator with small temperature changes.

Another object of the present invention is to keep fluctuations in the obtained voltage values small with respect to fluctuations in manufacturing conditions, such as manufacturing variations between lots (
It is an object of the present invention to provide a reference voltage generating device with a small deviation).

Another object of the present invention is to provide an integrated circuit reference generator that can reduce manufacturing variations to the extent that post-manufacturing adjustments are not required.

Another object of the present invention is to provide an integrated electronic circuit device including a reference voltage generating device that can be manufactured with a large margin of tolerance to target specifications.

Another object of the present invention is to provide an integrated electronic circuit device including a base voltage generator with high manufacturing yield.

Another object of the present invention is to provide a reference voltage generator suitable for IGFET integrated circuits.

Still another object of the present invention is to provide a reference voltage generator and a voltage comparator that consume less power.

Another object of the present invention is to obtain a base ffA1! that can obtain a low voltage (1.IV or less) with excellent accuracy. An object of the present invention is to provide a pressure generating device.

Another object of the present invention is to provide a reference voltage generator that is compatible with relatively low voltage (approximately 1 to 3 cm) power supplies, such as 1.5V silver oxide batteries and 1.3V mercury batteries.

Another object of the present invention is to provide a reference voltage generator suitable for semiconductor integrated circuits.

Another object of the present invention is to provide a highly accurate voltage ratio meter, stable specific gravity source device, constant current circuit, and battery checker.

Another object of the present invention is to provide a semiconductor integrated circuit device for an electronic watch that has a built-in highly accurate battery checker and has a small number of external terminals.

Another object of the present invention is to provide a reference voltage generator compatible with a complementary insulated gate field effect transistor integrated circuit (0MO8IC) and a method for manufacturing the same.

The present invention has been made by returning to the origin of semiconductor physical properties and focusing on the energy gap Eg e 7, the lumi level Ef, etc. in %.

In other words, it is well known that semiconductors have an energy gear of 2p, but the physical properties of these semiconductors, especially the energy
A reference voltage generator that focuses on the gap Eg or the Fermi level Efk has never been seen before, even though it has made remarkable progress in a wide range of fields since the invention of semiconductors.

In terms of results, the present inventors considered using this energy gap Eg, 7 Hermi level Ef, etc. as a base aX voltage source, and succeeded in realizing it. Using the energy e gap Eg, Fermi level Ef, etc. as a reference voltage source is not a difficult theory in itself, and the result is (
I hope it's something you can understand and agree with.5. However, in the field of the semiconductor industry, which no longer has a short history, this successful example, which is believed to be unprecedented, brought about by the present inventors, returning to the origins of semiconductor physical properties, is original and groundbreaking, and will continue to be used in the future. It is expected that this technology will greatly contribute to the further development of the electronic circuit and semiconductor industries.

According to one embodiment of the invention, two IGFETs with different conductivity types of silicon gate electrodes are fabricated within a silicon monolithic semiconductor integrated circuit chip. These FETs
are manufactured under almost the same conditions except for the conductivity type of the gate electrode, so the difference in Vth between the two is approximately equal to the difference in pressure between the Fermi levels of P-type silicon and NW silicon. Each gate electrode is doped with a respective impurity near the saturated acidity, and this difference is the energy gap of silicon E, (approximately 1, I
V) Kfi[, which is used as a reference voltage source.

A reference voltage generator based on such a configuration has a small temperature dependence and a manufacturing deviation of 71%, so it can be used as a reference voltage generator for various electronic circuits.

The present invention and other objects thereof will become more clearly understood from the following description with reference to the drawings.

Numerous documents explain the physical properties of semiconductors, starting from the crystal structure of semiconductors and extending to the energy-dependent band of semiconductors and the phenomena caused by donor and acceptor impurities in semiconductors.

Semiconductors with different compositions each have a unique energy gap Eg, which is an energy gear 2 expressed in eV.
P8 Needless to say, this is well known. however.

As mentioned above, semiconductors have an inherent energy gap E
There has never been an example of using this as a reference voltage source, focusing on the fact that it has a small temperature dependence.

Since this embodiment was developed starting from the basics of semiconductor physical properties, a detailed explanation of the present invention will first start from the fundamentals of the present invention by referring to the physical properties of semiconductors. The physical properties of semiconductors are explained in detail in many documents, and the following is one of them, S.

M. “Physics of Sem1co” by SZE
1969 John
Published by n Weye & 5ons, Special K Chapter
er 2″Physics and Property
esof Sem1 conductors - A R
A brief explanation will be given with the help of esume' I pages 1 to 65.

There are various compositions of semiconductors, including germaniecum (Ge>1'/Si), which is representative of the semiconductors currently used industrially. ) non-compound semiconductors and GaI) spm arsenic (GaAs) compound semiconductors. The relationship between these energy gaps Eg and temperature is explained on page 24 of the above-mentioned book, and this is shown in Figure 1.

As understood from Figure 1, Ge, Si and GaA
The Eg of s is 0°80(
eV), 1.12 (eV) Oyohi 1.43 (eV)
It is. In addition, the temperature dependence is 0.39(
meV/K), 0.24 (men/K) and 0.4
3 (meV/K). Therefore, by extracting a voltage corresponding to or close to the energy gap EgK, the forward voltage drop of the PN junction diode described above can be calculated. and IGFET threshold voltage Vth
A reference voltage generator can be obtained that has a temperature dependence that is one order of magnitude smaller than that of the standard voltage generator. Furthermore, the voltage obtained is determined by the energy gap Eg specific to the semiconductor, for example, in the case of Sl, it is approximately 1.12 (V) at room temperature, which is determined almost independently of other factors, and is not easily influenced by variations in manufacturing conditions, etc. It is possible to obtain a reference voltage.

Now, an example will be explained based on which principle the voltage corresponding to the energy gap Eg of the semiconductor can be extracted.

The energy unit state when a semiconductor is doped with donor and acceptor impurities is well known. In particular, what we have focused on in this invention is that the Fermi energies of NW and P-type semiconductors are located 2 minutes toward the conduction band and valence band, respectively, based on the Fermi energy level Ei of the intrinsic semiconductor. It is a physical property that The higher the concentration of acceptor and donor impurities, the higher the phase, the 7-luminium level Ei of the intrinsic semiconductor.
The tendency is for the P-type semiconductor to move further away from Ef
p approaches the upper limit level Ev of the valence band, and the Fermi level "fn" of the N-type semiconductor approaches the lower limit level Ec6C of the conduction band. If the difference between both Fermi units (Efn - Bfp) is taken,
When it approaches the energy gap EgK of the semiconductor, it becomes K, and its temperature dependence also becomes close to that of the energy gap Eg. As will be described in detail later, the higher the impurity concentration, the smaller the temperature dependence (Efn-Efp), and it is preferable to keep the concentration as close to the saturation concentration as possible.

7 The lumi level Efnt Efp is related not only to the concentration of donor and acceptor impurities, but also to the donor and acceptor levels Ed and B, and this unit Ed,
Ea varies depending on the impurity material. Levels Ed and Ea
The closer to the conduction band and the valence band, respectively, the closer the 7-factor lumi levels Efd and ``fa'' are to the respective ones. In other words, the shallower the donor and acceptor impurity levels Ed, J, the Fermi unit difference (Efn- Ef, ) is close to the semiconductor energy gap E1.

Donor and acceptor impurity levels Ed.

E f The closer the Fermi level EiK of the intrinsic semiconductor is, that is, the deeper the Fermi level difference (Efn −E
fp> is further away from the semiconductor energy m-gap Eg. However, this does not necessarily mean that the temperature dependence becomes worse, but it means that the absolute value of the difference in the 7-cup lumen point (Efn-Bfp) becomes smaller. Therefore, the difference between the 7-Eluminum levels CEfn−Ef
p') is specific to the semiconductor material and impurity material, and from another perspective, it is the energy gap E of the semiconductor.
It can serve as a base voltage source similar to the gap Eg, which is in a different category from the gap Eg. That is, the difference in Fermi units (Efo−
Efp) is itself the forward voltage drop of the PN junction.
It has less temperature dependence than r and the threshold voltage Vth of IGFET, and can be used as a reference voltage source with low K depending on manufacturing variations, and has shallow donor and acceptor levels Ed, Ef.
Using an impurity material that shows a difference of 7 lumi units (Efn
“fp)” is the energy of the semiconductor.
Gap Ec! This can be one way to extract a voltage that is approximately close to . On the other hand, when it comes to setting the voltage value to be obtained, if the purpose is to obtain a relatively large differential voltage corresponding to the energy m-gap of a semiconductor, an impurity exhibiting a shallow level is used. If the purpose is to obtain a relatively small differential voltage, an impurity exhibiting a deep level may be used.

Specific examples of selection of impurity materials Fermi level Ef, donor level Ed, acceptor fishing level E
. , donor concentration Nd, acceptor concentration Na and temperature T
We will explain the relationship in more detail with reference to Figures 2 and 3, but first, we will understand what units each impurity represents for Ge, Si, and GaAs semiconductors, and In order to understand how these impurities are utilized in the invention, the data on page 30 of the above-mentioned document is elevated as Figure 4 and an explanation is added7. ) are respectively,
Qe.

It is a diagram showing the energy distribution of various impurities for Si and GJIA8, and the numbers in each diagram indicate the energy distribution from the lowest level of the conduction band EC for the level located above the center Ei of the gap represented by the broken line. Energy difference (E
C-Ed), and for the lower level, the energy difference from the uppermost @ level Ey of the valence band (Ea-Ev
), and their units are (e, V).

Therefore, the unit of the impurity material indicated by a small value in the figure is the lowest unit of the conduction band, E. Alternatively, it indicates that it is close to the uppermost level EvK of the valence band, and is suitable as an impurity for obtaining a voltage close to the energy gap Eg. For example, SiK, which is currently most commonly used
On the other hand, the donor impurities of Li, Sb, P, As, and Bj and the acceptor impurities of B, A4, and Ga have the smallest chiseling differences (E("d), (Ea-Ev), and the respective levels Both differences are about 6% or less of the energy gap Eg of Sl.

The Fermi unit difference CEfd −Efa) between N-type Si and P-type Si using these impurities is equal to the energy gap E of Si, if the temperature change from θ°K is ignored.
It is about 94% to 97% of g, which is a value equal to Eg. In addition, it has the second smallest china difference (EC-Ed) of the above impurities.
), (E, -Ev) is 8 (approximately 16% of Eg), and the acceptor impurity is In (approximately 1 of Eg).
4%).

Fell ξ of N-type Si and P-type Si using each impurity
The difference in tiger position (Efd E(B)) is approximately 0.0 at O'K.
85Eg, and the deviation in the energy gap Eg of Si is as much as about 15%, and it can be seen that the deviation becomes extremely wide with respect to the above-mentioned impurities.

Margin below Therefore, as an impurity material for Pm and N-type Si to obtain a voltage approximately equal to the energy gap E of St, one selected from the group of LL, Sb, P, As, and Bi is used. A donor impurity and one acceptor impurity selected from the group B, A7 and Ga are preferred, the other impurities depending on the energy of the Sl.
It would be suitable for the purpose of obtaining a considerably smaller voltage than the gear and Eg.

Next, regarding the Fermi level difference (E(n-Efp)),
The physical properties will be explained with reference to FIG. The m2 diagram is a diagram showing the energy levels of a semiconductor, and (a) and (
(b) shows an energy level model of an N-type semiconductor and its temperature characteristics, and (c) and (dl) show an energy level model of a P-type semiconductor and its temperature characteristics, respectively.

The intermediate particles in the semiconductor are the ionized and resident electrons nd of the donor impurity Nd, and the bears of electrons and holes excited from the valence band. When the impurity Nd is sufficiently large, the excited electrons and holes can be ignored, and the number n of conduction electrons is n+nd (1). nd is the probability of being trapped by one donor,
Further, n is determined from the number of electrons present in the conduction band, and is determined by the number of electrons present in the conduction band. Here, h: Blank constant 1m*: Effective mass of electrons From this, it becomes (5).

Here, since the Fermi level is determined to be at a position close to Eo, the first term of equation (5) can be ignored.

This equation shows that, of course, when the temperature is low, the Fermi level is located between the lower end of the conduction band and the donor level, and the temperature dependence is approximately equal to the temperature characteristic of EC.

However, if the temperature is sufficiently high, a large number of electrons and holes excited from the 5 valence band become available, the influence of impurities decreases, and the Fermi level approaches the level E of an intrinsic semiconductor. Figure 1 (
b).

The same is true for a P-type semiconductor containing only acceptor impurities as shown in Figure 1(C); at low temperatures and when the acceptor impurity concentration is large, the Fermi unit is
It is located approximately between the top of the valence band and the acceptor level, and as the temperature increases, it approaches the 7 Hermi level of an intrinsic semiconductor.

This relationship is shown in FIG. 1(d).

Relationship - Specific Example Having explained the physical properties of the relationship between the temperature dependence of the Fermi levels Efp and Efn and the impurity concentration, next we will discuss the relationship between the temperature dependence of the Fermi levels Efp and Efn and the impurity concentration as a specific example. 37 Considering the true data, we will explain the Fermi level difference (Efn-Ef, ) and its temperature dependence in practical use. The data is shown in Figure 3.

In the normal 81 semiconductor integrated circuit manufacturing process, boron B and phosphorus P are mostly used as impurity materials, and in areas where the impurity concentration is high, 10" (atoms/
/I)l! ), but even if the impurity ei is set to 10'' (atoms/?I3), which is two orders of magnitude lower than that, as can be read from Figure 3, the difference in the 7 Hermi level between the N-type semiconductor and the P-type semiconductor (Efo -Efp) is 0.5- (-0,5) -1,0 (eV) at 300'K.

Energy gap E gyl, 1 e at the same temperature
The value is relatively close to V. The change with temperature is approximately 1.04 (eV) to 0.86 (eV) in the range of 200°K to 400°K (-70°C to 130°C), and the rate of change is 0.9 (mV). /'C). This is because the rate of change of the threshold voltage Vth of the IGFET and the forward drop voltage VF of the diode with respect to temperature is 2 to 3 m.
This is a small value of about 1/3 compared to V/'C.

If the impurity concentration is IQ”m-3 or more, the silicon energy gap (Eg) Si-1,1 (V) K
are equal, and the rate of change in temperature is approximately 0.2 mV/''C, which is a sufficiently low rate.

Therefore, if the impurity concentration is about 10"Ow-' or more, it is possible to obtain a temperature dependence that is at least 1/2 to 1/3 smaller than the conventional one, and more preferably 1320m" or more (
(improvement of about 1/10), and most preferably saturation concentration.

In this example, on what principle can the voltage corresponding to the Fermi level difference (Efn - Ef) be extracted? Two MOs with different semiconductor gate electrodes
This method utilizes the difference in threshold voltage Vth of SFETs. A specific example will be explained below.

FIG. 5 shows a conceptual cross-sectional structure of each FET. Hereinafter, for the sake of simplicity, a MOS transistor with a P4 type half as a gate electrode will be referred to as a P+ MOS transistor, and a MOS transistor with an N+ type semiconductor as a gate electrode will be referred to as an N+ MOS transistor as an N+ MOS transistor. FIG. 6 shows the above P+ gate Ni o s and N+ gate in general 0MO8 manufacturing technology.
Doug-MOS does not make any changes or additions to the final process.

It is a sectional view of the main steps showing that the structure can be constructed.

Figure 7 shows the pattern actually used in the circuit structure.
- For the case of a channel MOS transistor, the figure is shown along with the cross-sectional structure.

In Fig. 7, in order to obtain a self-aligned structure,
At both ends of the gate electrode in contact with the source and drain, since it is a P-channel MOS transistor in this case, there is a P+ MOS transistor.

P impurity is diffused in both N+gegu MO3. In the center of the gate tt pole, a P-type impurity is diffused for P+GOOMOS, and an N-type impurity is diffused for N+Dag-MOS.

A region process in which no impurity is diffused is provided between the central region and both ends in contact with the source and drain, and
Care has been taken to ensure that the differences between the P+Goo (P+Goo) MOS and the N+GeGoo MO8 are simply that the gate center region is a P-type medium conductor and that it is an N-type semiconductor.

However, due to an error in mask alignment, the P-type impurity diffusion region of the gate, which was taken for self-alignment, was j!
11, the rows of source and drain regions are alternated so that the deviation (change) in the effective channel length of the MOS transistor due to biasing to one side (source tilted or drain side) is minimized. The left half and the right half are arranged symmetrically with respect to the channel direction. Therefore, the deviation (left and right) in the channel direction of mask alignment is
Even if there is a change in the effective channel length of the P+Goo 110s and N'''' game OS in each row connected in parallel, the average effective channel length of the P+Goo 110s and the N'''''' game OS will be nW
It becomes constant.

FIG. 6 shows how P+ MOS and N+ MOS are constructed in a typical silicon MOS (G) 0 MO8 manufacturing process.

(In diagram a3, lot is N with a specific resistance of 1Ω~8Ω
type silicon semiconductor, and a thermal oxide film 102 of 400 nm is applied thereon.
It is grown at 8 degrees from 0A to 16000A, and windows for diffusion are selectively opened using photoetching techniques. Boron, which will become a P-type impurity, is ion-implanted at an energy of 50 KeV to 2001 (eV) in an amount of about 10 H to x □ H-2, and then thermally diffused for about 20 hours from 8 o'clock to form the substrate of an N-channel MOS transistor. A P-well 103 is formed.

(b) In the figure, the thermal oxide film 102 is removed, a thermal oxide film 104 is formed with a thickness of about 1 μrIL to 2 μm, and the regions forming the source, drain, and gate of the MOS transistor are removed by etching. After that, gate oxidation If@105 of about 300A to 1500A is formed.

On top of that, polycrystalline Si 106 is applied at 2000A to 6000A.
It is then removed by etching, leaving only the gate portion of the MOS transistor.

In the figure (c), an oxide film 107 is formed by vapor phase growth and removed by photoetching in the region where P-type impurities are diffused. After that, boron, which becomes a P-type impurity, is expanded to a high concentration of about 10 - 10 countries - 3, and the P channel P1
10s) Ranjistor source.

A drain region 10B is formed, and at the same time a gate electrode of a P-type medium conductor is formed.

In the td1 diagram, the oxide film 1 is grown by vapor phase growth as before.
09 is formed, and the region in which the N-type impurity is diffused is removed by photoetching. after that.

Phosphorus serving as an N-type impurity is diffused at a high concentration of about 1020 to 10 - to form the source and drain regions 110 of the N-channel MO8) transistor, and at the same time form the gate electrode of the NIJ1 semiconductor.

(e) In the figure, oxidation It! 109 is removed, an oxide film 111 of approximately 4000 to 8000 A is formed by vapor phase growth, and the electrode lead portion is removed by photoetching. Thereafter, gold (An) is deposited and an electrode distribution portion 112 is formed by photo-etching.

(In the f1 diagram, a 1 μm to 2 μm oxide film is formed by vapor phase growth.

Next, the threshold voltage of a MOS transistor whose gate uses a semiconductor as an electrode will be explained according to Fig. 8. 6 First, to the P+ gate 108 In the case of 108, see Fig. 8 (from the energy band diagram of al (-r −” 4M φS.

However, here ■. ; Potential difference X between the semiconductor substrate and the gate electrode (p+ semiconductor) ; Electron affinity, Eg; Energy gap φ, ; Temporary surface potential in N-type semiconductor φyp + P-type based on Fermi potential of pA semiconductor Fermi potential of a conductor φF; Tsuborumi potential q of an N-type semiconductor substrate based on the Fermi potential of an intrinsic semiconductor; unit charge of an electron ■o; potential difference Eo applied to an insulator; lower limit of the energy level of the conduction band Ev ; Upper limit Ei of the energy level of the valence band; 7 Hermi units of an intrinsic semiconductor In equation (7), the work function of the gate electrode is expressed as a potential, and it is expressed as φ and 10, and the work function of the semiconductor is similarly expressed as If we set it to φ81, then V. −−V, +φ, −φai−φs −(IG.

Also, in Figure 8 (from the relationship of the charge of bl -COX-V6 +Qas +Q1+QB=0...
(11), where COX; per unit area, drawing room of insulation.

Qas; @l^j constant voltage in powder QB; fixed charge Qi due to ionization of impurities in semiconductor substrate; ) + Q
sa + Qi + QO-0-'J'J.

The gate when Channel Qi is created! Pressure ■. but.

Since this is the threshold voltage, if Vthp+ is the threshold voltage of P+GEGMO8L, then cox cox ""' At this time, it is φ8-2φF.

Similarly, in the N+GEGMO8) transistors, the only difference is the work function φMN+ of the gate electrode. Therefore, the threshold ak1L8EVthH+ +
Here it becomes φ8-2φF.

From this, the difference between the threshold voltages of the P+ gate MOS and the N+ gate MO8, vthp+ - thN+, is vthp" - v
thN"-φMP+-'l'MN+-d'rp"-φF
N”...θυ, and the 7-hermi
It becomes a bodential difference. This is shown in Figure 88 (at
, (Comparing cl, the gate voltage when the same 'N and load distribution are obtained is the difference between the gate and the poles,
This can be easily understood as a difference between Fermi and levels.

The above explanation is based on the case of a P-channel type MO8) transistor, but the same applies to the case of an N-channel type MO8) transistor.

Next, KMO8) A circuit for extracting the difference in Vth of transistors will be explained.

The circuit described below is based on the Fermi unit difference (Ef
This can be one method for extracting n-E(,), but other methods generally include reference voltage generation using a voltage based on the difference in Vth of FETs with different Vth as a reference voltage.
: Can be applied as a position.

FIG. 9(b) shows a circuit that generates a voltage corresponding to the threshold voltage of a MOS transistor. TI+T constitutes a so-called MOS diode whose drain and gate are commonly connected.

0 is a constant current source, T, , T are different threshold voltages Vt
It is a MOSFET with mutual conductance β almost equal to hl and Vth2, and each drain voltage is
,■! Then, 1, -1 β(V+ -vthl '', so V+ -vthl + % ``'''' Vl - V1h2 + fi -rm, and if we take the difference in drain voltage, we can extract the difference in threshold voltage. can.

As a constant current source, you can use a sufficiently large resistor, and as long as it has the same characteristics, you can use a diffused resistor.

Multi-M crystal S1 resistor, resistor made by ion implantation,
MOS) resistors can be used.

In this circuit, N+gegu M, which was explained earlier as T, ,T,
By using O8 and P+ gate MOS, it is possible to extract the Fermi level difference (E(n-Ef, )) of the Nu cow body P microscopic conductor, which is approximately equal to the difference in threshold voltage. .

In addition, goo)! In addition to changing the ffl composition, examples include ion implantation into the channel, doped gate
It is possible to have different threshold voltages by changing the oxide, the thickness of the gate insulating film, etc., but if this is applied to the circuit of FIG. 9.

The difference in threshold voltage corresponding to the amount of ion implantation, the amount of impurity doped into the gate insulating film, and the thickness of the gate insulating film can be similarly extracted as a reference voltage.

For example, it is well known that in the ion implantation method, the implantation amount can be monitored in the form of current, so the accuracy of the impurity concentration is extremely good compared to normal diffusion, and Figure 1O shows this situation. It is. M before ion implantation
OS) Assuming that the characteristic of the transistor is T, the threshold value varies by Vth after ion implantation, and even if each individual is balanced, the difference in the threshold voltage between the two varies. Since mtl, which is determined by the amount of ion implantation, has extremely little variation, it can also be used as a reference voltage with little manufacturing variation. In other words,
If thl is the threshold voltage of transistor T (MOB without ion implantation), it is the same as formula 09, and the increase in the fixed charge of the substrate due to ion implantation is Δ.
If it is QB, ion implanted MO8) transistor T
, the threshold voltage Vthdi becomes. The temperature change in this threshold voltage difference voltage is ΔQ
Since B is almost constant against temperature changes, it is extremely small.

Another great advantage is that the base *& pressure can be freely changed depending on the amount of ion implantation, and that it can be easily realized even in a single channel MO8 manufacturing process.

The following is a margin of 1 day + Amahiro 1-Mafune Usui Momo
There is one large cape and nine domains.

FIGS. 11 and 12 are examples of circuits that connect FETftMOS diode types having different threshold voltages in series to extract the difference in threshold voltage. It is assumed that T has a threshold voltage vthl #TI has a threshold voltage vths.

Under the condition that the resistance R1 is sufficiently large compared to the impedance of T, and the resistance R1 is sufficiently large compared to the impedance of T, Vl −V2 ”vthl ・+・+−CGV+ +V
1hB -...(!4 Therefore, K, vt "thl-vthl"""5.

In FIG. 13 1al, a voltage corresponding to the threshold voltage of both terminals of the capacitor is applied, and the voltage held in the capacitor is extracted as a differential voltage. FIG. 13 1all shows the operation timing. The clock pulse φ turns on Ts=To, and the capacitance C* tc T t ,
Charge the differential voltage of the threshold voltage "thl I Vthffi" of Tt.

After φ1 is cut off, T is turned on by clock φ, and C
Ground node 3. At this time, since the differential voltage between the threshold voltages is held in CI, that potential is output as is to node (2). When used in a voltage detection circuit as described later, the potential of node (2) at this time can be used as it is as a reference voltage. can be used in a more general form, so that K can be used in a more general form.
,,T, is turned on, and the capacitance C! If that potential is taken in and received by a so-called voltage follower whose output is fully fed back to the negative phase input (-) of the operational amplifier 5, the output will be T, with sufficiently low internal impedance.
The difference between the threshold voltages of T is obtained as a reference voltage.

FIG. 14 shows a reference voltage generator using the same aK capacitor C8. T is turned on by clock φ. At this time, T is in an off state due to clock φ. The potential of node ■ is lower than the potential of node ■ by the threshold MW pressure vth1 of TI.
The potential of node ■ is lower than the potential of node ■ by T,
is lowered by the threshold voltage ■tht, and the difference voltage between the two is charged across the capacitor C. Next, T is turned off by φ, and φ! When T is turned on, a voltage difference between the threshold voltages is obtained at the node (2).

FIG. 15 shows a known operational amplifier used in the circuit of FIG. 13. T, ,T, is a differential pair that constitutes a differential amplifier circuit;

T6 is its active load. T, is, T,,T.

Bias circuit based on trap and cointegration constant 'rI1. It constitutes a flow circuit. Te, Tt is a level conversion/output buffer circuit with T as a constant current source load. In the figure, C-MO
Although the circuit configuration example for S is shown, single channel MO
What you can do with 8! Not even 5.

In addition, in this operational amplifier, the differential pair T, , T, constituting the differential amplifier circuit is provided with a specific threshold voltage ■thl l vthz by the method described above. The voltage difference can be used or extracted as a reference voltage, which is an unprecedented application of operational amplifiers.

FIG. 16 schematically represents a general operational amplifier by taking only its differential part.
S) The transistors T, , Tt each have different threshold voltages■
th1#vth2, and other characteristics are assumed to be equal. Further, the signs (-) and (+) appearing on the input side mean that the output is in opposite phase and in phase with the output, respectively.

If the input of T is V+ and the input of Tt is vt, then V+
VIhI=Vl v, h, tr+■+Vt:
'” V t ht V t h z ++ ++.

The output level changes based on the following conditions.

An operational amplifier has an input offset equal to the difference between the threshold voltages, and if one of the inputs is connected to ground or the power supply, it can operate as a comparator using this offset voltage as the reference voltage. I can do it. Therefore, it is 5K as shown in Figure 16.

If the output is connected to the (-) input terminal and the +) input terminal is grounded, a difference in threshold voltage will be obtained at the output (out). In this case, in order to operate the operational amplifier, K is T! must be in debressi attack mode. For example, T
, KP+Gegoo8°T, when using N+Gegoo M08, ions may be implanted into the channel portions of both MOSFETs under the same conditions to form a dipledge type.

In FIG. 17, the reference voltage can be arbitrarily set using the operational amplifier in FIG. 16. If the output is fed back to (-) human power through the voltage dividing means Rs and Rs, and if the voltage dividing ratio is r, then the output voltage will be ■. is vthx −vthg vo= −□□ (2). The voltage dividing means Rs and Re are preferably linear resistances, but
Any resistor may be used as long as it has a sufficiently uniform IC% to an acceptable level.

The circuits in Figures 16 and 17 are based on the use of a depression type MO8, whereas the circuits in Figures 18 and 19 are designed to be able to operate with an enhancement type MO8. be. Of course, it's okay to be a Depledge adventurer.

The example shown in FIG. 18 is similar to the example shown in FIG. 16, in which the output is directly fed back to the (-) input, and the output is ■. is the power supply voltage■D
If D, V6 =■DD-(vthg "tbl)"
・(2) becomes. In the circuit shown in Figure 16.17, it is necessary to put at least one of the differential pairs into depression mode, which may require an increase in the number of manufacturing steps depending on the case, but it is possible to set the differential voltage of Vth to the ground potential. It can be extracted based on.

Conversely, in the circuit of Figures 18 and 19, the reference for the resulting differential voltage is the power supply voltage that is not the ground potential, p! -1 There are no particular conditions for the operating mode of the FET.

Which circuit format to adopt can be decided depending on which advantages and disadvantages are considered.

The example in FIG. 19 is the same as the example in FIG.
The output is fed back to the (-) input through the circuit, and the output is [.

Figure 20 shows how the reference voltage from a reference voltage generator that uses the difference in Vth is added to one input of the comparator, and the detected voltage is added to the other input, and the level of the detected voltage with respect to the reference voltage is distinguished. This is a voltage detection circuit that makes it possible to

In the example shown in Fig. 21, the reference voltage from the reference voltage generator using the difference in Vth is added to the comparator, and the detected voltage is divided into the other input by the voltage dividing means Re, R◎. This is a voltage detection circuit that applies the same voltage.

The voltage division ratio is r, the reference voltage is ref, and the detection level is vse.
nse, and the detection level 5ense can be arbitrarily set by the partial pressure ratio r.

The example in FIG. 22 uses an operational amplifier with an offset corresponding to the difference in Vth, and uses an off-set signal as described above.
This is a voltage detection circuit that uses a set voltage as a reference voltage. Further, R11-R□ is the same pressure dividing means as in the example of FIG.

In the example of Figures 20, 21, and 22, if the voltage to be detected is the power supply voltage, it can be used as a battery checker in a system that uses a battery as the power supply. A specific example in which the voltage detection circuit of FIG. 22 is applied to a battery checker for an electronic watch is shown in FIG. 29, and detailed explanation will be given later.

The example shown in FIG. 23 is applied to a stabilized power supply circuit. The reference voltage generation circuit is configured using the several methods described above, and compares a part of the stabilized output with the reference voltage using Rsa #R14, and adjusts T so that they match.

control the gate voltage and stabilize the output voltage. Any operational amplifier may be used as long as its characteristics are acceptable.

The example in FIG. 24 is T, in the example in FIG. KMO8) Instead of using a transistor, use a bipolar tube transistor T
R, is used.

The example shown in FIG. 25 uses the operational multiplier A having the offset voltage shown in the example shown in FIG. Of course, T*I may be a MOS transistor, an Ibora transistor, or a junction field effect transistor.

The example in FIG. 26 is a constant current circuit determined by the difference in threshold voltage between T and T.

'r,,T, have the same transconductance β, and have different threshold voltages Vthl t vths. If the resistance Rto is sufficiently high compared to the impedance of T, the drain voltage (=gate voltage) vl of T is V
It becomes almost equal to thl.

When T, is in the saturated region, the electric light flowing through T.

= -β(Vth□-Vthg)"...-C313
becomes.

The example in Fig. 27 is a voltage drop system using heavy lightning flowing through T□. This is a constant current circuit that compares utRll with a reference voltage vref and controls the gate voltage at 5:T so that both are always equal.

...Zeng becomes.

Here, the reference voltage may be obtained by providing an operational amplifier with an offset e-set, as in the previous example.

The example in FIG. 28 is T□, T3. This is a constant current circuit using the same transistor and using a so-called current-mirror circuit.

The example shown in FIG. 29 is an example in which the battery checker shown in FIG. 22 is applied to an electronic watch.

T,,T,,T,,%T4. and R□ and R41 constitute a circuit that checks the voltage level of the nominally 1.5V mercury battery E1. The transistor pair in the differential section is a P+ gate.
N channel - MOS, N+ Gegu/N channel - MO8
The channel portion is ion-implanted so that the threshold voltage of both T1 and T is within 1.0 V to 1.5 V, which is the operating power supply range of an electronic watch.

The difference between the threshold voltages, which serve as reference voltages, is approximately 1.1■ in the case of silicon semiconductors, and the level at which it is detected that the voltage of the It is adjusted by the resistance ratio of the means R+ and Rt.

The Kono battery checker operates intermittently using a clock signal φ obtained from the 1-frequency divider circuit FD through the timing circuit TM in order to reduce the current consumption to a practically negligible level.

The output of the battery checker is NAND gate goo I
, NA! The logic level of this latch circuit output controls the timing circuit TM, thereby changing the drive output of the motor and changing the way the hands move, thereby reducing the battery voltage. Display. A drop in battery voltage does not change the movement of the pointer, and the liquid crystal, light emitting diode, etc. It is also possible to display by blinking the pneumatic light.

In the same figure, the OSC is composed of a CMOS inverter, and includes parts outside the IC such as a crystal Xtal, a capacitor CG, and a CD.
WS is a waveform shaping circuit that converts the oscillation output from a sine wave to a rectangular wave, CM is the excitation coil of the step motor that drives the second hand, BP, *BF
, is a buffer for driving the excitation coil CM by inverting its polarity every second, which is composed of a CMOS inverter.

All circuits in the IC are nominally 1.5v mercury battery E.

It works. In addition, TM represents the divided outputs of a plurality of different frequencies of the frequency divider circuit FD and NA, , NA! This is a timing pulse generation circuit that receives the control output of a latch configured as input and generates a pulse with an arbitrary period and pulse width. The IC is a monolithic Si semiconductor chip for a pointer type electronic wristwatch manufactured by the Si CMOS process shown in FIG.

The present invention has been described above based on various embodiments, but
The technical idea described herein is not limited to this, and may be applied to electronic devices for various other uses.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the energy gap Eg of GaAs, Si and Ge semiconductors and its temperature dependence. Figure 2 is a diagram showing the band structure and Fermi level Ef of a semiconductor, where Iat and fbl are N-type semiconductors, [c
l, (dl indicates an example of a P-type semiconductor. Fig. 3 is a diagram showing the temperature characteristics of the 7-luminium level of N-type and P-type Si with impurity concentration as a parameter. Fig. 6 1al r
tbl and lcl are diagrams showing the energy level distributions of Ge, Si, and GaAs semiconductors, and the donor and acceptor impurities of each leakage, respectively. Figure 5 shows the difference in Fermi units (E
Fig. 3 schematically shows the cross-sectional structure of a P+ gate and N+ gate MO8FET that can be used to extract fn-Efp), with the left half showing the P-channel FET and the right half showing the N-channel FET. Figure 6 1al to (fl is N+ gate (B part) and P+ gate (A part) P-channel FET in which P-channel MO8FET constitutes a normal complimentary MO8
It is shown fabricated with an ET (section C) and an N-channel FET (section D). It is a sectional view in a main process. 97 Figure 181, tbl is N + goo, respectively) The top view and cross-sectional view of the P-channel MO8FET are shown in the same figure (cL
, ldl shows a plan view and a cross-sectional view of a P+gegu P-channel MO8FET, and the line indicated by the arrow in each plan view is assumed to be the cutting line of the cross-sectional view. Figure 8 1al and tbl show the energy state and charge state of the P+ type semiconductor-insulator-N type semiconductor structure, respectively; FIG. 9 shows a characteristic diagram of an MO8 diode circuit and its circuit for extracting the difference in Vth of two FETs having different threshold voltages Vth. FIG. 10 is a characteristic diagram showing how Vth changes due to ion implantation K. FIG. 11 and FIG. 13. FIG. 11+ shows an example of yet another reference voltage generation circuit, and FIG. 11+ shows the timing signal waveform thereof. FIGS. v1 voltage generation circuit. Figures 20 to 22 show examples in which they are applied to voltage detection circuits, Figures 23 to 25 show examples in which they are applied to voltage regulators, and Figures 26 to 28 show examples in which they are applied to voltage regulators. The figure shows an example applied to a constant current circuit, and Fig. 29 shows an example applied to a battery checker for an electronic wristwatch.T...MOSFET, R...resistor, C...conductor/sugar , Xtal...Crystal resonator, O20...Crystal oscillation circuit, WS...Sine wave-square wave conversion waveform shaping circuit,
FD...Binary power counter multi-stage connection frequency divider circuit, TM...
Timing circuit, CM...excitation coil for the step motor for driving the second hand, BF...buffer for driving the CM, N
A...NAND gate, IC...monolithic Si
Semiconductor integrated circuit chip, φ...clock pulse, Eg
... Energy gap of semiconductor, Ev ... Upper limit level of valence band, EC ... Lower limit level of conduction band, E
i...Fermi level of intrinsic semiconductor, Efn, Efp・
・Fermi units of N-type and P-type semiconductors, Ed, Ea・
...Donor accessor level. Figure 1 Figure 3 tct) Figure 2 Figure 4 (tL) 177-CJII-+(niKg-'"""Crt14(
J44G age 5 8 Fig. 6 Fig. 9 (ct) (b) Fig. 11 Fig. 12 Fig. 13 (+21 3-1~------- Fig. 14 Fig. 16 Fig. 17 Fig. 18 Fig. 19 Fig. 20 Fig. 21 Fig. 22 Fig. 23 Fig. 24 Fig. 25 Fig. 2 2 2.

Claims (1)

[Scope of Claims] 1. A first type having a threshold voltage difference according to the Fermi unit difference of the gate electrode. a second IGFET, an inverting input terminal,
It has a non-inverting input terminal and an output terminal; Second
The sources of each of the 7GFETs are coupled to each other, the gate of the first IGFET is coupled to the inverting input terminal, the gate of the second IGFET is coupled to the non-inverting input terminal, and at least the first or 21st CFET
includes an operational amplifier in which a signal based on a signal output from the drain of is supplied to the output terminal, a feedback voltage is supplied from the output terminal to the inverting input terminal, and a predetermined potential is supplied to the non-inverting input terminal. A reference voltage generating device characterized in that a reference voltage is taken out from the output terminal. 2. The reference voltage generating device according to claim 1, wherein the feedback voltage is generated by voltage dividing means provided at the output terminal. 3. The second IGFET mentioned above is a debressing type GFE.
The reference voltage generating device according to claim 1 or 2, characterized in that the reference voltage generating device is composed of a TK. 4. Above 1. 3. The reference voltage generating device according to claim 1, wherein each gate electrode of the second IGFET has a semiconductor layer portion having a different conductivity type. 5. The first one has a threshold voltage difference according to the Fermi level difference of the gate electrode. a second IGFET, an inverting input terminal, a non-inverting input terminal, and an output terminal;
The sources of each of the IGFETs are coupled to each other, the gate of the first IGFET is coupled to the inverting input terminal, the gate of the second IGFET is coupled to the non-inverting input terminal, and the gate of the first IGFET is coupled to the non-inverting input terminal.
includes an operational amplifier in which a signal based on a signal output from the drain of the valve is supplied to the output terminal, a feedback voltage is supplied from the output terminal to the inverting input terminal, and a predetermined potential is supplied to the inverting input terminal of the upper valve. A reference voltage generator is configured such that a reference voltage is taken out from the output terminal, the reference voltage is supplied to one input terminal thereof, and the voltage to be detected is supplied to the other input terminal. A voltage detection device comprising a comparator. 6. The voltage detection device according to claim 5, wherein the voltage to be detected is formed by voltage dividing means. 7. Above 1. 7. The voltage detection device according to claim 5, wherein each gate electrode of the second IGFET has a semiconductor layer portion having a mutually different conductivity type. 8. The first one has a threshold voltage difference according to the Fermi level difference pressure of the gate electrode. a second IGFET, an inverting input terminal,
It has a non-inverting input terminal and an output terminal; Second
The sources of each of the IGFETs are coupled to each other, the gate of the first IGFET is coupled to the inverting input terminal, the gate of the second IGFET is coupled to the non-inverting input terminal, and an output from at least the drain of the first or second IGFET is coupled. an operational amplifier to which a signal based on a signal is supplied at the output terminal voltage, a feedback voltage is supplied from the output terminal to the inverting input terminal, and a predetermined potential is supplied to the non-inverting input terminal; a reference voltage generator configured to output a reference voltage from the output terminal; a differential amplifying means having a pair of input terminals and an output terminal; and a differential amplifying means having a pair of terminals; and a control element controlled by the output of the differential amplifier, an unstable voltage is supplied to one terminal of the control element, and a voltage based on the voltage appearing at the other terminal of the control element is applied to the differential amplifier. A voltage regulator, characterized in that the reference voltage is supplied to one input terminal of the means and the reference voltage is supplied to the other input terminal of the differential amplification means. 9. A patent characterized in that the other terminal of the control element is provided with voltage dividing means, and the voltage formed by the voltage dividing means is supplied as a preload to one input terminal of the differential amplifying means. The voltage regulator according to claim 8. 10. Above 1. 10. The voltage regulator according to claim 8, wherein each gate electrode of the second IGFET has a semiconductor layer portion having a different conductivity type. Margin below