JPS6341223B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a pair of insulated gate field effect transistors, which is particularly applicable to a reference voltage generator.

In various semiconductor electronic circuits, in order to generate a reference voltage, it is essential to use a physical quantity having the dimension of voltage. Until now, physical quantities such as the forward voltage drop V _F of a PN junction diode, the reverse breakdown voltage (Zena voltage) V _Z , and the insulated gate field effect transistor (often represented by an IGFET or MOSFET) have been considered. Threshold voltage V _th etc. are used.

These physical quantities do not indicate absolute voltage values, and the voltage values are subject to fluctuations depending on various factors. Therefore, in order to utilize these physical quantities as a reference voltage generating device for various electronic circuits, it is necessary to pay attention to the fluctuation factors of the obtained voltage value and the permissible fluctuation range.

First, regarding the temperature characteristics of these physical quantities, the above V _F and V _th usually have a temperature dependence of about 2 to 3 mV/°C, and the temperature change in the reference voltage that accompanies this temperature change varies depending on the application. In some cases, the size is such that we have no choice but to give up on practical use.

Next, regarding manufacturing variations in these physical quantities, the threshold voltage V _th of the MOSFET has a variation of about ±0.2V, and this variation is larger than the temperature change. Therefore, when the battery checker described above is made into an IC (integrated circuit) using V _th , external components and connection pins (terminals) for reference voltage correction are required.
Not only that, but it also requires time and effort for adjustments after the IC is manufactured.

In addition, the Zener voltage V _Z has a low voltage limit of about 3V, which is inappropriate as a reference voltage for use in the low voltage range of about 1 to 3V. In order to use it as a voltage, it is necessary to flow a current of several mA to several tens of mA, which is also inappropriate in terms of reducing power consumption.

As is clear from the above explanation, conventional reference voltage generators using V _th , V _F , and V _Z are not necessarily suitable for all uses, considering temperature characteristics, manufacturing variations, power consumption, voltage levels, etc. In many cases, practical application or mass production had to be abandoned for applications requiring extremely strict characteristics.

From the above studies, the present inventors learned that there are physical limits to the improvement of conventional reference voltage generators, and decided to research and develop a reference voltage generator with new ideas and ideas. .

Regarding this point, the present inventor has invented a reference voltage generating device using a pair of insulated gate field effect transistors (MOSFETs) having the same channel and gate electrodes of different conductivity types. This reference voltage generator has the following advantages, as will become clear from the description below.

(a) Design and mass production of electronic circuits can be facilitated.

(b) Small temperature changes.

(c) Variations in voltage values are smaller than variations in manufacturing conditions, for example, products with small manufacturing variations (deviations) between lots can be obtained.

(d) It is possible to obtain an integrated circuit that can reduce manufacturing variations to such an extent that post-manufacturing adjustments are not required.

(e) A product that can be manufactured with a large margin for target specifications can be obtained.

(f) It is possible to obtain an integrated electronic circuit device including a reference voltage generator with a high manufacturing yield.

It is an object of the present invention to provide a method for manufacturing an insulated gate field effect transistor suitable for manufacturing a reference voltage generating device having the above-mentioned advantages. The purpose is to provide a manufacturing method.

First, a reference voltage generator constructed by the inventor of the present invention will be described. This reference voltage generator was created by going back to the origins of semiconductor physical properties and paying particular attention to the energy gap Eg, Fermi level Ef, etc.

FIG. 1 shows a P-channel MOSFET (A) with an N-type polysilicon 5 as a gate electrode and a P-type polysilicon 6, which constitute an embodiment of the reference voltage generating device of the present invention.
A P-channel MOSFET (B) is shown in which the gate electrode is .

Since these FETs are manufactured under almost the same conditions except for the conductivity type of the gate electrode, the difference in V _th between them is approximately equal to the difference in Fermi level between P-type silicon and N-type silicon. Each gate electrode is doped with each impurity near the saturation concentration, and this difference is approximately equal to the silicon energy gap E _g (approximately 1.1V), and by making both channel dimensions the same, this V It is possible to extract _{the th} difference with high precision, and this is used as a reference voltage source.

A reference voltage generating device based on such a configuration has low temperature dependence and small manufacturing deviation, so it can be used as a reference voltage generating device for various electronic circuits.

In FIG. 1, 1 is an N-type silicon substrate, 2
is a thick oxide film for FET element isolation, 3 is a gate oxide film, 4 is a P-type impurity layer for source and drain, and 5 is a thick oxide film for FET element isolation.
6 is N-type polysilicon, and 6 is P-type polysilicon. Here, the N-type polysilicon gate 5 is doped with both an N-type impurity and a P-type impurity, and has a structure in which the concentration of the N-type impurity is 1.5 times or more than the concentration of the P-type impurity, or the P-type impurity is doped. Although it contains almost no impurity and is doped with N-type impurities, it has a self-aligned structure with the source and drain.

The need for the concentration of the N-type impurity to be 1.5 times or more the concentration of the P-type impurity is as follows. In other words, in normal high-concentration impurity doping technology, the concentration control system varies by about ±20% of the set value, and therefore the above N-type impurity concentration and the above P
The ratio of type impurity concentration is (1.5±0.3)/(1.1±0.2)
Since the minimum value of this ratio is 1/1, the Fermi level of the polysilicon doped with both N-type and P-type impurities changes greatly.

Therefore, in order to allow for a certain degree of manufacturing variation, the ratio of the impurity concentrations must be 1.5/1 or more.

In order to satisfy such requirements, the present invention provides a method for manufacturing an insulated gate field effect semiconductor device including a pair of MOSFETs, which includes the following steps.

(a) A polysilicon film is formed via a gate insulating film to cover a first part and a second part of the surface of the semiconductor substrate, and the polysilicon film covering the second part is removed from the first part. (b) doping the polysilicon film covering the polysilicon film with an impurity of a first conductivity type to form a first gate electrode and a second gate electrode in the first portion and the second portion, respectively; (c) removing the polysilicon film from the first and second portions not covered by the first and second gate electrodes and the first and second gate electrodes; The first conductivity type is doped with an impurity of a second conductivity type, which is an opposite conductivity type to the first conductivity type, so that the doping amount is lower than the impurity concentration of the first conductivity type in the first gate electrode. and a step of forming source and drain regions of a second conductivity type for each of the second gate electrodes and defining the second gate electrodes as the second conductivity type. This shows a method for manufacturing an IGFET.

(a) N-type Si substrate 1 is oxidized to form a thick oxide film 2 for element isolation, and a gate oxide film 3 is placed in this opening.
After forming, an intrinsic semiconductor polysilicon film is deposited by a vapor phase growth method, and a vapor phase growth oxide film 7 is further formed partially. Using the oxide film 7 as a mask,
By selectively doping the polysilicon with impurities such as phosphorus and arsenic, N-type polysilicon 5 and intrinsic polysilicon 6 are obtained.

(b) After removing the oxide film 7, the gate polysilicon electrode is processed by photoetching, and the source and drain P-type impurity layers 4 are formed by the usual thermal diffusion method. Here, by setting the n-type impurity concentration doped into the polysilicon in (a) to be at least 1.5 times the P-type impurity concentration doped into the polysilicon in the P-type impurity diffusion in (b), the polysilicon gate 5 is kept in shape.

The manufacturing method of the present invention does not require a special mask or etching process for the gate electrode, compared to other manufacturing methods devised by the inventor, which will be described next with reference to FIG. Therefore, it is more advantageous.

3a, b, c, and d show other manufacturing methods of the reference voltage generator of the present invention, and a is the second
This figure shows the same manufacturing process as in Figure a.

(b) After removing the oxide film 7, the gate polysilicon electrode is processed by photoetching, and the gate oxide film in the portions that will become the source and drain is removed using the polysilicon gate as a mask, and then heated at 750°C.
Oxidize for 60 to 600 seconds in ~900°C steam.

As a result of this oxidation, the portions 9 that will become the source and drain, and the surface of the intrinsic polysilicon 6 have
Oxide films 8 and 10 of 20 to 40 Å are formed, and N
70 to 200 Å on the surface of the molded polysilicon gate.
An oxide film 9 is formed.

(c) After this, by thermally diffusing boron at 950 to 1000°C for about 20 minutes, the oxide films 8 and 10 are penetrated into the P-type impurity layer 4 and the P-type polysilicon layer 6.
form. At this time, N-type polysilicon layer 5 is protected by oxide film 9 and is not doped with boron. or HF: _H2O before thermal diffusion of boron
A similar structure can be obtained by removing oxide films 8 and 10 by etching for 60 seconds with an etchant of 1:99, leaving 40 to 150 Å of oxide film 9, and carrying out the thermal diffusion of boron.

(d) After this, a phosphor glass film 11 is formed, a contact hole is formed, and an Al electrode 12 is formed to complete the process.

Although this manufacturing method has been described for the case of a Si gate P-channel MOSFET, it is exactly the same for a P-channel MOSFET in the case of a Si gate CMOSIC.

Below, a method for extracting a reference voltage in a reference voltage generator using a pair of MOSFETs obtained by the manufacturing method of the present invention will be described.

Next, a circuit for extracting the difference in V _th of MOSFET transistors will be explained.

The circuit described below can be a method for extracting the above-mentioned Fermi level difference (E _fo −E _fp ), but it is also generally used for FETs with different V _th
It can be applied as a reference voltage generator that uses the voltage based on the difference in V _th as a reference voltage.

FIG. 4 shows a circuit that generates a voltage corresponding to the threshold voltage of a MOS transistor. T ₁ , T ₂
constitutes a so-called MOS diode whose drain and gate are commonly connected.

I ₀ is a constant current source, T ₁ and T ₂ are different threshold voltages
It is a MOSFET with mutual conductance β almost equal to V _th1 and V _th2 , and each drain voltage is
If V ₁ and V ₂ , then I ₀ = 1/2β (V ₁ −V _th1 ) ² = 1/2β (V ₂ −V _th2 ) ² , so V ₁ =V _th1 +√2 ₀ ...(2 ) V ₂ =V _th2 +√2 ₀ (3), and by taking the difference in drain voltage, the difference in threshold voltage can be extracted.

As a constant current source, a sufficiently large resistor may be used, and as long as it has the same characteristics, a diffused resistor,
Polycrystalline Si resistors, resistors made by ion implantation, and resistors made from MOS transistors can be used.

If the N ⁺ gate MOS and P ⁺ gate MOS described earlier are used as T ₁ and T ₂ in this circuit, the fermi quasi of the N-type semiconductor and the P-type semiconductor can be The difference in position (E _fo −E _fp ) can be extracted.

FIGS. 5 and 6 are examples of circuits in which FETs having different threshold voltages are connected in series in the form of MOS diodes to extract the difference in threshold voltage.
T ₁ is the threshold voltage V _th1 and T ₂ is the threshold voltage V _th2
Suppose you have

Under the condition that the resistance R ₁ is sufficiently large compared to the impedance of T ₁ and the resistance R ₂ is sufficiently large compared to the impedance of T ₂ , V ₁ −V ₂ ≒V _th1 ...(4) V ₁ ≒V _th2 ... …(5) Therefore, V ₂ ≒V _th1 −V _th2 …(6).

In FIG. 7a, a voltage corresponding to the threshold voltage is applied to both terminals of the capacitor, and the voltage held in the capacitor is extracted as a differential voltage. FIG. 7b shows the operation timing. T ₅ and T ₆ are turned on by clock pulse φ ₁ , and T _{1 and} T 6 are applied to capacitor C ₁ .
The difference voltage between the threshold voltages V _th1 and V _th2 of T ₂ is charged.

After φ ₁ is cut, turn on T ₃ using Crochet φ ₂ .
Ground the _C1 node. At this time, since the difference voltage between the threshold voltages is held in _C1 , that potential is output to the node as is. When used in a voltage detection circuit as described later, the potential of the node at this time can be used as it is as a reference voltage. However, in order to be able to use it in a more general form, the transmission gate T ₆ is input by clock φ ₃ during the time when clock φ ₂ is entered.
Turn on T ₇ , take that potential into capacitor C ₂ ,
If the output is received by a so-called voltage follower that completely feeds back the output to the negative phase input (-) of the operational amplifier 5, the difference between the threshold voltages of T ₁ and T ₂ will be the output with sufficiently low internal impedance. Obtained as a reference voltage.

FIG. 8 shows a reference voltage generating device that similarly utilizes capacitance _C2 . Turn on _T8 by clock _φ1 . At this time, _T9 is in an off state due to clock _φ2 . The potential of the node is lower than the potential of the node by the threshold voltage V _th1 of T ₁ , the potential of the node is lower than the potential of the node by the threshold voltage V _th2 of T ₂ , and the difference voltage between the two is across the capacitor C. is charged. Then φ ₁ turns off T 8, and φ ₂ turns off T ₈ .
When _T9 is turned on, a voltage difference between the threshold voltages is obtained at the node.

FIG. 9 shows a known operational amplifier used in the circuit of FIG. T ₁ and T ₂ are a differential pair forming a differential amplifier circuit, and T ₅ and T ₆ are active loads thereof. _T7 constitutes a constant current circuit together with the bias circuit formed by _T3 and _T4 . _T8 ,
_T7 is a level/variation/output buffer circuit that uses _T7 as a constant current source load. The figure shows an example of a C-MOS circuit configuration, but single channel
Needless to say, it can also be configured using MOS.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a MOSFET having gate electrodes with different Fermi levels, which is necessary for the configuration of the present invention.
2a, b, 3a, b, c, and d are cross-sectional views showing the MOSFET manufacturing method according to the present invention, and FIGS. 4, 5, 6, and 7a and 7, respectively. 8
Figure 9 is a reference voltage generation circuit diagram using MOSFETs having gate electrodes with different Fermi levels, Figure 7b is a signal waveform time chart showing the operation timing of the circuit in Figure 7a, are shown respectively. 1... N-type silicon substrate, 2... Oxide film, 3...
...Gate oxide film, 4...P-type layer, 5...N-type polysilicon, 6...P-type polysilicon, 7...Vapor-phase growth oxide film.

Claims (1)

[Claims] 1 (a) A first portion and a second portion of the surface of a semiconductor substrate.
a polysilicon film is formed via a gate insulating film to cover the second part, and the polysilicon film covering the first part is doped with a first conductivity type impurity, except for the polysilicon film covering the second part. (b) removing the polysilicon film to form a first gate electrode and a second gate electrode in the first portion and the second portion, respectively; (c) removing the polysilicon film in the first portion and the second portion; and an impurity of a second conductivity type opposite to the first conductivity type to the first and second portions not covered with the second gate electrode and the first and second gate electrodes. by doping so that the doping amount is lower than the impurity concentration of the first conductivity type in the first gate electrode. forming a pair of insulated gate field effect transistors of the same channel type having gate electrodes of different conductivity types, comprising: forming source and drain regions and defining the second gate electrode as a second conductivity type; A method for manufacturing an insulated gate field effect semiconductor device characterized by: