CA1154880A - Reference voltage generator device - Google Patents

Abstract

REFERENCE VOLTAGE GENERATOR DEVICE
Abstract of the Disclosure The method is for manufacturing a semiconductor device with at least a pair of insulated gate field-effect trans-istors having semiconductor gate electrodes of different conductivity types. An impurity of one conductivity type is introduced into a portion of a semiconductor layer where a first gate electrode of one conductivity type is to be formed, and then an impurity of the opposite conductivity type is introduced into all of the semiconductor layer with a density lower than that of the impurity of the first conductivity type so that a second gate electrode of the opposite conductivity type is formed at another portion of the semiconductor layer. The method has the advantage of enabling manufacture of an improved semiconductor device without increasing the number of fabrication steps.

Description

l~S~1~3~) , This application is a division of Applica~ion Serial No. 321,~55 filed February 20, 19879 and relates to a method of manufacturing a semiconductor device.
In generating reference voltages in various semi-conductor electronic circuits, it is necessary to utilize a physical quantity having the dimension oE the voltage.
As such physical quantities, there have until now been solely utilized the forward voltage drop VF or reverse breakdown voltage (Zener voltage) Vz of a PN~ nction diode, the thrèshold voltage Vth of an insulated gate field-effect transistor (often represented by an IGFET or MOSFET), etc.
These physical quantities do not indicate voltage values which are absolutely fixed, since their voltage values are subject to fluctuations due to various fac-tors. In order to make use of these physical quantities for reference voltage generator devices of various elec-tronic circuits, accordingly, attention must be paid to the factors which cause the fluctuations of the voltage values and the allowable limits of the fluctuations.
First of all, the voltages VF and Vth usually have a temperature-dependency of approximately

2 - 3 mV/C. The fluctuation of the reference voltage attendant upon the temperature change reaches such a magnitude that their application has to be given up in some uses.
By way of example, when a battery checker for pro-viding an alarm when the voltage of a battery has fallen below a predetermined reEerence value is intended to be realized in an electronic timepiece which employs a silver oxide battery having a nominal voltage of l.~ V, whether the battery voltage is high or low needs to be judged with .

~ #~ the boundary (detection level) or the cletection re~erence value at about 1.4 V.
When a reference voltage generator device is to be constructed by exploiting the threshold voltage Vth oE a MOSFET or the forward drop voltage VF of a diode which is about 0.6 V, the detection level aimed at 1.4 V has a temperature-dependency of:
0 6 (V) x {2 ~ 3 (mV/C)} = 4.67 ~ 7.0 (mV/C).
Accordingly, even when the practical operating tem-perature range is estimated to be as narrow as 0C to 50C, the detection level fluctuates as much as 1.23 V
to 1.57 V, and a satisfactory battery checker cannot be obtained.
Furthermore, the physical quantities suffer from dispersions or deviations in the manufacture. For example, the threshold voltage Vth of a MOSFET has a : dispersion of about +0.2V, which is greater than the temperature fluctuation. Accordingly, when the above-stated battery checker is put into the form of an IC
` 20 (integrated circuit) by exploiting the voltage Vth, not only is there the difficulty of providing the external components and external connection pins (external connec- ~ :
tion terminals) necessary for adjusting the reference voltage, b~it also additional labor is required to carry ` out the adjustment after the fabrication of the IC.
The lower voltage limit of the Zener voltage Vz is :
about 3 V, and it is impossible to generate a reference voltage to be used in a low voltage range of 1 to 3 V or so. When using the Zener voltage or the forward drop voltage of a diode as a reference voltage, a current of the order of several mA to several tens of mA needs to be ~S~8~

caused to flow, which is inappropriate from the point of view of lowering the power dissipation of the reference voltage generator device.
It is apparent rom the above explanation, that the conventional reference voltage generator devices exploiting the voltages Vth, VF and Vz have not always been suited to all the uses when the temperature character-isticsl the dispersions or deviations in manufacture, the power dissipation, the voltage level etc~ are taken into account. For uses requiring very severe characteristics, it has often been the case that the practical use or the mass production must be relinquished.
The inventors of this invention have thus appreciated that improvements in the conventional reference voltage generator devices are subject to physical limitations and ~-carried out research in order to develop a reference voltage generator device based on a new idea or conrept.
To this end the invention consists of a method of manufacturing a semiconductor device with at least a pair of insulated gate field-effect transistors having semi-conductor yate electrodes of different conductivity type, comprising the steps of: preparing a semiconductor substrate having a semiconductor region of a first conductivity type extending to a major surface of said semiconductor substrate; forming an insulating film over said major surface at a first portion of said semiconductor region and at a second portion of said semiconductor region, and forming a semiconductor layer over said insulating film overlying said first and second portions of the semiconductor region; forming a mask over a first portion of said semiconductor layer overlain at said first portion of the semiconductor region except for a second L~

portion of said semiconductor layer overlain at said second portion of the semiconductor region; introducing an impurity of the first conductivity type into said first portion of the semiconductor layer except into said second portion thereof using said mask, to form a region of the first conductivity type having an impurity density at that portion; removing said mask over said first portion o~ the semiconductor layer; removing said semiconductor layer to form first and second semiconductor ~ate electrodes at said first and second portions of the semiconductor region respectively; and selectively introducing an impurity of a second conductivity type opposite to the first conductivit~
:. type into said first and second portions of the semi-conductor region with an impurity density lower than said impurity density of the first conductivity type at said first portion of the semiconductor layer using said first and second gate semiconductor electrodes as masks to form source and drain semiconductor regions of the second conductivity type on opposite sides of each of said first and second gate electrodes and to provide the second conductivity at said second semiconductor gate electrode while said ~irst semiconductor gate electrode is held at the first conductivity type.
Various preferred embodiments of this invention to be described later and of inventions disclosed herein and claimed in the parent application referred to above and other divisional applications iled simultaneously herewith have the following advantages:
3Q (1) A reference voltage generator device having small temperature variations can be providedO
-: - 5a -~5~&RB~

(2) There can be provided a reference voltage generator device in which the fluctuations of the voltage value to be obtained are small with respect to the fluct~ations in manufacturing conditions, for example, the manufacturing disp~rsions (deviations) among various lots are quite small.

- 5b -115~8~

(3) There ean be provided a reference voltage generator deviee in the form of an integrated eireuit whieh ean diminish the manufacturing dispersions to sueh an extent that no adjustment after manuEaeture is neeessary.

(4) There ean be provided an eleetronic circuit device in the form of an integrated circuit including a reference voltage generator device which can be manufactured with a large tolerance rela-tive to a specifieation aimed at.

(5) There ean be provided an electronie circuit device in the form of an integrated circuit including a reference voltage generator device which has a high manufacturing yield, i.e. a high efficiency percentage.

(6) A reference voltage generator device which is suited to an IGFET integrated circuit can be provided.

(7) A reference voltage generator device and a voltage comparator which are of low power dissipation can be provided.

(8) There can be provided a reference voltage generator device which can produce a low voltage (of or below 1.1 V) of very yood precision.

(9) There can be provided a reference voltage generator device which is suited to a power source of a comparatively low voltage (approximately l to 3 V), for example, a silver oxide battery of 1.5 V or a mercury battery of 1.3 V.
(lO) It is possible to provide a referenee voltage generator device which is suited to a semiconductor integrated cireuit.

(ll) It is possible to provide a voltage eomparator '~8~0 a stabilized power supply device, a constant-current eircuit and a battery checker which have high precision.
(12) It is possible to provide a semiconductor integrated cireuit device for an electronic timepiece which contains a battery checker of high precision therein and which has a small number of external terminals.
(13) It is possible to provide an IGFET integrated circuit in which the threshold voltage of an IGFET with a back bias applied thereto can be maintained at a substan-tially constant voltage independent of dispersions inmanufacture and changes in temperature, whereby the yield ; of manufacture can be enhanced.
(14) It is possible to provide a reference voltage generator device which is eompatible with a complementary type insulated gate field-effect transistor integrated - eircuit (CMOS IC) or with an N-channel MOSIC or P-channel MOSIC, and a method of manufacturing the same.
(15) It is possible to provide a constant-voltage output circuit whieh is suitable for making the power dissipation low. That is, there ean be provided a constant-voltage output circuit which produces a stabilized voltage with a low absolute supply voltage, sueh as the battery voltage, and whieh has a low power dissipation.
~16) It is possible to provide a referenee voltage generator deviee which is compatible with the so-called silicon gate insulated-gate field-effect transistor integrated circuit employing silicon for the gate electrodes, and a method of manufacturing the same.
(17) There can be provided a method of manufacturing a reference voltage generator device without inereasing the number of fabricating-steps in the fabrication of a silicon gate P-channel IGFET integrated circuit.
(18) There can be provided a reference voltage generator circuit which e~ploits the dif~erence of the Fermi levels of aluminum and intrinsic silicon, which does not employ P-type silicon containing a P-type impurity, such as boron, liable to be introduced into a channel portion throùgh a gate insulating film and which undergoes small dispersions in manufacture.
(19) It is possible to provide a method of manufac-turing a reference voltage generator device which can prevent an acceptor impurity forming a P-type silicon gate such as B, A~ and Ga from being introduced into a channel portion through a gate oxide film to change the threshold voltage of an IGFET whose gate electrode is made of the P-type silicon.
(20) It is possible to provide a semiconductor memory . which has the function of preventing any erroneous writing in a data retention mode. That is, when a supply voltage has become below a set detection voltage, at least one of control signals required for a writing operation can be inhibited.
(21) It is possible to provide a Schmitt trigger circuit which is constructed of MISFETs (insulated gate field-effect transistors) and whose hysteresis curves have a width which varies little due to the fluctuations of a supply voltage, the manufacture dispersions of the MISFETs, the changes of the temperature, etc.
This invention has been made by going back to the starting point of the physics of semiconductors and taking special notice of the energy gap Eg~ the Fermi level sao Ef, etc.
It is well known that semiconductors have ~nergy gaps Eg and various levels such as donor, acceptor and Fermi levels. However, until now there have been no proposals to produce a reference voltage generator device utilizing the physics of semiconductors, especially the energy gap Eg and the Fermi level Ef, despite remarkable develop-ments achieved in extensive fields since the discovery of semiconductors.
Based upon actual results, the inventors thought of utilizing the energy gap Eg~ the Fermi level Ef, etc.
; for reference voltage sources and have succeeded in this realization. It is not difficult in theory to use the energy gap Eg~ the Fermi level Ef, etc. for reference voltage sources, and the results will be readily under-stood. However, the success achieved by the inventors is believed to be unprecedented, particularly from the point of view that the inventors have gone back to the starting point of the material properties of semiconductors, bearing in mind that the history of the semiconductor industry is no longer short. This development is therefore believed to be creative and epochal, and is expected to contribute greatly to further advancements of electronic circuits and the semiconductor industry in the future.
According to the invention there is provided a reference voltage generator device comprising means for detecting a voltage substantially equal to or smaller than an energy gap of a semiconductor or a voltage based on an energy level of a semiconductor, a voltage based on the detected voltage being used as a reference voltage.
According to a preferred embodiment of this invention, g _ 88~

two IGFETs which have silicon gate electrodes of conduc-tivity types opposite to each other are fabricated within a silicon monolithic semiconductor integrated circuit chip. Since these FETs are manufactured under substan-tially the same conditions except for the conductivity types of the gate electrodes, the difference of the threshold voltages Vth of both the FETs becomes approximately equal to the difference of the Fermi levels of P-type silicon and N-type silicon. The gate electrodes are doped with respective impurities in the vicinities of the saturation densities, and the difEerence becomes approximately equal to the energy gap Eg of silicon (about l.l V), which is utilized as a reference voltage source.
Since the reference voltage generator device based on such a construction has low temperature-dependency and small manufacture deviations, it can be used as a reference voltage generator device in various electronic circuits.
The invention, and in particular the preferred embodiments thereof, are discussed in detail in the following with reference to the accompanying drawings, in which:-Figure l is a diagram showing -the band gaps Eg of GaAs, Si and Ge and their temperature-dependencies;
Figures 2(a) to 2td) are diagrams showing the band structures and Fermi levels Ef of semiconductors, in which Figures 2(a) and 2(b) illustrate an example of an N-type semiconductor and Figures 2(c) and 2(d) illus-trate an example of a P-type semiconductor;

Figure 3, which appears on the same sheet as Fig. l, ~S4880 is a diagram showing the temperature characteristics of the Fermi levels of N-type and P-type Si with the impurity densities being a parameter;
Figures 4(a), 4(b) and 4(c) are diagrams showing the distributions of energy levels possessed by Ge, Si and GaAs semiconductors and vario~s donor and acceptor impurities, respectively;
Figures 5(a) and 5(b) are diagrams showing the energy ; state and the states of charges of a P~-type semiconductor ` --insulator - N-type semiconductor structure respectively, while Figures 5(c) and 5(d) are diagrams showing the energy state and the states of charges of an N~-type semiconductor -~e rT.

~" 115~ 30 .

lnsulator - N-typ~ semlconductor structure ~espe¢tlvely;
Flgures 6(a) and 6(b~ are a characterls~lc diagram and a clr~ult dlagram o~ a MOS dlode clrcult for deriv1~g the di~ference of V~h of two F~T~ ~aving unequal hresno`ù
voltage~ Yth respec~lYely;
ure ? is a chara~2ristlc dlagram ~howing ~é
situation in ~hich a threshold voltage ls oha~ged by ion : lmplantation Figures 8 and 9 are dia~rams eac~ ~howin~ an ex~?le of a referenc~ voltage generator clrcult whicn expiolts the dlfference of threshold ~oltages 'Vth;
~igure lO(a) is a circuit dla~ram of a reference vol~age gene~2tor clrouit showing an Pmbodl~nt of ~hls i~ventlo~, ~hlle Figure lO(b) is an opera~ing wa~efor~ di~r 3~ 0~ the clrcuit ln ~l~ure lO(a);
Figure ll~a) s~ows a further exam~le o~ a reference Yoltage generator clrcult, while ~lgure lltb) shows ti~ing ; slgnal waveform3 thereof;
Figure 12 shows a reference voltaxe generator clrcuit :~
whlch 13 based on a~other embodiment;
~igure 13 ~hows an op~ratlonal am?llfler c~rcuit which has an offset vol~a~e ln accordance with thi3 invention, ~i3~re 14 shows a reference ~oltage ~enerator circuit ~hich u.llize~ the opera~ional ampllflar clrcult of r~ure 13;
Figures lj, 16 and 17 show reference voltage g~nerat.or c~rcuits wh~ch util~2e ope.atlonal ampli~ler clr~lts accor~-ng to other embodi~ent~
?i~ures lR and 19 ~how vQlt~ge detec~cr circ~l~ts ea~:r.
of wh~ch employ~ a refe~ence 301ta~e produced from the ,~ referenc~ volt23e generator circult according to ~his ln~:e~.'ion;

~ 12 -~ 880 -~igure 20 shows a ~ol~age detector c1rcult which utllize3 an operational ampllfier circuit haYing an offset voltage ln accordance with ~h'_ ln~entlon, ~I.sure 21 shows a voltage com~arator which ls for~ed by connacting ~-~OS~T~ of une~ual threshold voltages 'Jth in ~he differential type ln accordance with this inve~tlon;
~l~u~e 22 shows a di~feren~ial alQpllfier clrcult wh1ch employq ilOS~Ts of unequal threshold voltages Y~h ln accordar.ce with this inventlon;
~igure 23 ~hows the drain current - ~ersus - ~a~ ~olta~e characteristic~ of the diff~rential pair ~.OS transis'ors of the differentlal am~llfier circul~ show~ in ?16ure ~2;
~gure 24 shows an offse. type vo'tage co~arat~r clrcul~ whlch 1~ const~ucted of a voltage co~?arator clrcult and source ~ollower circults employlng two ~CS~Ts of threshold ~olta2es dlffere~t fro~ each other in accordance wlth thls ln~entlon;
~igure ~5.show~ an ofSset type ~oltage co~parator circult which is constructed of a voltage comparator circuit and Orounded-source clrcuits employin~ two '~IOS~ET~ of threshold voltage~ dl~ferent from each other in accordance wi~h thls inventlon, ~lgure 26 ~hows an example of a co~tant-current clrcult which i~ u~ed in the off~et ~ype voltage comparator clrcult of Figure 24 Flgure 2~ show~ a rererence Yoltage ~enera~or circul~
wh~c`n e~ploy~ the diferential ampllfler elrcult ~hown ln ~igure 22 ~l~u~e 28 show~ the deta'ls o~' tne o~fse~ typ~ ~oltage co~parator c1rcult shown in ~l~ure 24, and illustrates a case ilS~880 .

in which a reference voltage generator circuit is constructed by employing this volta~e comparator circuit.
~ig~rn Z9 shows a constant-currel~t circuit whicr, exploits the dlfference of the thr~shold ~olta~es o t-~o MOS~Ts in accordance with this invention, ~isure 30 3hows a constant curren~ ci-cuit ~o whic'n is applied a .eference voltage ~enerator cl-cuit t;~at ?roduces a reerence ~oltage on the basis of ~'ne ~ifferer,ce of t`~e threshold voltages of two t~iO3~T~ in accord~nce wlth thls inv~ntion, ~lgure 31 shows a cons~ant-current circuit in which a current mirror circult is added ~o the constant-cu.ren~
circult shown in Fi~ure 30;
~lgures 32 and 33 are clrcuit ~ r~s each ~howi~b a stabllized power supply circuit to whi~ ls ap~lied a reference volta7e generato. circuit that produces a reference voltage based on the difference of the threshold volta~es o~
~'O~Ts ln accordance wl~h this lnvention;
Fi~ure 34 shows a ~tablllzed po~wer ~upply circuit to which is applied an opera~onal ampllfier that has the di~ference of the threshold voltages o~ MOS~_Ts as lts off-set voltage in ~ccordance wi~h this lnventlon;
~lgure 35(a) ls a circult diagram for explainlng an example of a Yoltage regulator ~o whioh an off3et ~ype opera~ional amplifier circuit accordlng to thl~ in~entio~
is applied, while ~i~ure 355b) ls an electrical characterlstic dl~gram for explalning the operatlon of the volta~e re~ulator, F16ure 36(a~ ls a clrcult dl~gram for explainln~ a ~lta~e regulator accordln6 to a~oth~ em-o~diment of tnis ln~ention, w~,~le ~i~ure 36(b) ls an electrical chara~terlstlc diagra~

~5~88~

for explain~ng the operatlon o the voltage regulator;
~lgure 37 ls a c~rcult dlagram showlng an example ln the case in which this inven~ion is applied to a battery life-ime detector circuit;
~igure 38 i3 a diagram oPc- clrcuit for a clo~X-drive~
battery checker according ~o another em~odl.~ent, ?igure 39 ls a dlagraQ of a reference voltage ~enerator circult whose reference voltage ca~ be f~nely ad~usted ~ith a reslstor ou~slde an IC, ~igure 40~a) shows a Schmitt trlgger ~ircult t~ whlch :~
the pri~clple o~ thls l~entlon ls applled, while Fl~ure 40(b) shows the hy~tere~l~ characteris lc o~ the 3chmitt trlgger circuit;
Fl~ure 41 shows a Schmitt trigger circult according to another embodlment, Fi&ures 42 and 43 are diagrams.eac'n showln$ an oscllla~or clrcuit to whlch the Schmltt trigger clrcult according to ~hls lnvention ls Applled, ~lgure 44 ~hows a dlfferentlal ampli~ier whlch e~ploys MOSFETs;
~igure 45 shows a TTL - MOS slgnal level shlfter circult according to this invention; :
Flgure 46 show~ a logic thresho~d stablllzer circult accordlng to thl~ ln~ent~on, Fi~ure 47 ~hows a ~ubstrate bias generator circult accordl~g to thls ln~en~lon~
~lgure 4~ hows a status sett~ng circuit accordi~g to ~-thls ~nvention, r l~urf~ 49 ~how~ a ~'tatus setting circui~ hi~h has hltherto been proposed;

lL5481!3~

. Figure 50 shows a MOS memory whlch employs the ~ubstrete bi~ generator clrcuit shown ~n ~iæure 4~,~
~igure 51 shows a memory cell in the ~lOS memory o~' ~lgure 50;
~lgure 52 shows a semico~ductor random ac~e~s memory accordlng ~o thl~ lnven~lon;
Fi~ure ~3~a~ shows a voltage deteetor circuit whlch is used i~ the semlconduc~or random ac~ess ~emory accordlna ~o th~s invention, whlle ~igure 53(b) ~hows the opera~ing wave- - :
forms of the voltage detector circult;
~lgure 54 shows an elec.ronlc timeplece .o whlch the battery checker shown ln ~lgure 20 is appl~ed;
Figure 55 show.~ an electronlc timepiec~ t~ ~hich a slmilar battery checXer ls applied;
Flgure 5& shows an electro~lc tl~eplece to whlch the voltage re~ulator as shown ln ~lgure 36~a);
~lgure 57 shows an elec.ronic.tl~eplece to which a similar ~folt~ge regulator is applied;
Figure 58, which appears on the same sheet as Fi~. 61, is a structural sectional view of two MOSFETs which have threshold voltages di~ferent f~om each other in accordance .; with ~his invention;
! r i~ure 59 schematlcally showa sectional structures of p~ gate and N~ ~a~e ~lOSF~Ts usable for derl~lng the dlfference ~5 (E~ - Efp) of the ~er~l levels o~ M-type ard 2-type semi~
co~ductor~, ln whlch ~he left half sho~s a P-chsnnel F~T
while the rlgh~ half shows an N-channel ~rT
ure 60 also schemat~c~lly sho~s ~ectional s.ructu~es of p~ gate and ~ e MOSr ~Ta usable for derl~in~ ~he dif,erenc~ (E~n ~ Efp) o, the ~ermi levels of N-~ype and P-type semic~nductors; ~n which the left hal~ 3hows a 5~88~

P-channel Fr,T while the rlght hal~ show~ an N-channel ~_T;
Flgure 61 slmilarly shows a structu~e of two P channe~
MOSFET~ whic~ nave threshold volta~es different from eac:~
. other, ~lgures 62 and 63 are sectlonal v~ew~ ea~h showir.a the e~sentlal portion~ of MOS~T~ which are required for ~he construction of thls inventlon and whi~h have ~ate ele~trodes of different ~erml l~vels;
Fi~ure 64 ls a sectlonal view of the essentlal ?ortions of ~OS'r,Ts whlch constitute a reference vol~a~e ~enerator devlce a~-cording ~o this lnYent~on;
?igu.e~ 65(a) and 65(b) are plan view an~ a sectlonal vl~w o an ~ ~ate P-channel ~ ET respectively ~he section_l views being taXen along lines lndlcated by arrows ln the 15 . correspondlng plan vlews, ~lgures 65(a) and 66(b) are a plan vlew an~ a sectio~al ~iew of a P~ gate ?-channel ~;OS~T, respect~vely;
~igurea67(a) and 67(b) ~how a plan vlew and a sec.~onal v~ew of a P~ gate P-channel MOSF~T, respectlvely;
Flgure~ 68(a) and 68(b) qho~ a plan vie~ ar.d a sectlo~al view of an i &ate P^channel rGS~T, respectiYely Flgure3 ~9(a~ and 69~b) show a plan view a~d a sectlonal vl~w o~ an rt~ gate P-channel MOS?~T, respec~iYely; ~ -Figures 70(a) and 70(b) ~how a plan view and a sectional view of an N~ gate N-channel MOS~T, respec~L~ely;
Fi~ures n ~a) and n (b) show a plan vtew and a sectional view of an 1 gate N-c~annel MO~F-T 9 re~?ectively;
Flgures 72(a) and 72(b) ~how a plan ~lew and a section~l view of a P~ gate N-channel MOSFE~, res~ectlvely;
~igures ?3(a) to 73~ us~rate that N~ ~,at~ (par, ~) 115~8~0 and P+ gate tpart A) P-channel MOS~Ts are fabricated together wlth a P-channel ~ part C) and an l~-channel F~T (par~ D) wh~ch Con3ti~ute a conve~tional Gt~ple~entary ~,OS device;
Figures 74(aj to 74(d), ~'lgures 75(~) to 75(d), ~lgures 76(a) to 76(d) and ~lgures 77(a) to 77(d) show sectlonal v~ew i:n the princlpal steps in .he ~ase of ~anufac-turing two MOSFETs a~ording to thls inventlon .o~ether w'th a comple~entary ~IOS device, respectlvely;
Figure3 78(a~ to 78(e) show sectl~:nal vlews in the various steps of manufac~ure 1~ the ¢ase of .N-channel ~C~a~_Ts J
~i~ures 79(a) to 79(e), F~gure~ ~O(a) to 60td) 2n,d Flgures 81~a) to 81(d) are sectional views ~n varlous s.e?s for explai~lng a method of manu~cturing ~'OS~,T~ for use in . 15 a reference voltage generator clrcuit devlce accord~ng to this invention, respectively, a~d ~lgures 82(a) and 82~b~ and FlOures 83(a) to 83(d) show sectional Ylew~ i~ var~ou~ step~ for explainlng a~other :
method of manufacturin~ MOSF~Ts for use in a reference voltage generator ~ircult de~lce accordlng to this inve~ion, respectlvely.
The physics of semiconductors whi~h begins wi~h ~he crystalline structure o~ a semisonductor and which develops into the energy ~and o~ a semiconductor and phenomena brought about by donor and acceptor impuri~ies are well explained in the literature.
I~ is, of course, well known thet se~icon~ucto.s o~
dlfferer,t composib~on~ ha~e energy gaps ~g lnhe~ont t~.ereto and that the energy ga? ~g exp~essed in e~ has ~he dimension ~1~4~1V

of a voltage. As previousl~ stated, however, there has never been any suggestion of using the energy gap Eg as a reference voltage source based on the fact that the energy gap Eg exhibits a low temperatuee-dependency.
The present invention has been made by star-ting from - the fundamentals of the physics of semiconductors. There-fore, the detailed description of this invention will be commenced by briefly referring to the pertinent points of the physics of semiconductors. Since the material pro-perties of semiconductors are explained in extensive detail in many publications, reference will be made to one such publication, namely "Physics of Semiconductor Devices" by S. M. SZE, published by John Wiley & Sons in 1969, especially Chapter 2 "Physics and Properties oE
Semiconductors" on pp. 11 - 65.
Application of Energy Gap Eg Semiconductors have a variety of compositions. The semiconductors typically utilized industrially at present are non-compound semiconductors of germanium (Ge) or silicon (Si), and gallium-arsenic (GaAs) compound semi conductors. The relatlonship between the energy gaps Eg of these semiconductors and temperature are explained on page 2~ of the publication referred to above, and is reprinted in Figure 1.
As seen from Figure 1, the energy gaps Eg of Ge, Si and GaAs are 0.80 (eV), 1.12 (eV) and 1.43 (eV), respec-tively, at normal temperature (300 K). Their temperature-- dependencies are 0~39 (meV/K), 0~24 (meV/K) and 0.43 (meV/K), respectively. By deriving voltages of values equivalent to or close to the energy gaps E, accordingly, reference voltage generator devices can be obtained which B~

have tempe~ature-dependencies one order smaller than those of the forward voltage drop VF of a PN-junction diode and the threshold voltage Vth of an IGFET as stated previously. Furthermore, the voltage to be obtained is determined by the energy gap Eg inherent to the semi-conductor. With, for example, Si, it is about 1.12 (V~ at normal temperature substantially independently o other -~
factors. It`is possible to obtain a reference voltage which is not affected by dispersions in the manufacturing conditions etc.
An example will now be explained as to the principle upon which the voltage corresponding to the`energy gap Eg of the semiconductor can be derived.
Application of Difference of Fermi Levels _Work Functions) of N-type, i-type and P-type Semiconductors The conditions of energy levels when doping semi-conductors with donor and acceptor impurities are well known. Especially noteworthy to this invention is the phenomenon that the energy levels at which the Fermi energies of N-type and P-type semiconductors are located are separated towards a conduction band and towards a valence band with respect to the Fermi energy level Ei of an intrinsic semiconductor. The energy levels become more distant Erom the Fermi level Ei of the intrinsic semi-conductor as the densities of the acceptor and donor impurities increases, the Fermi level Efp of the P-type semiconductor comes close to the top Ev oE the valence band, while the Fermi level Efn of the N-type semi conductor comes close to the bottom Ec of the conduction band. Accordingly, when ~ 8~0 the di~ference (Efn - ~fp) ot` both the ~erml levels is taken, the energg~ level dlfference is sub~tantlally approximate to the energy gap ~g poqses3ed by the semiconductor and its te~perature-dependen~y ~s also approxlmate to that of the energy gap Eg. The ~ame applie~ to the dlffere~ces (~fn ~ ~l) and (~1 ~ Efp) between ~he Fermi levels of t,he ?-.~pe se~
conduct~r and the lntrln31c semlcon~uctor and ~e~een the ~erml levels of the N-type semiconductor and the intr~nsic ~e~lconductor. In this case, however, the absolute val~e approaches Eg/2. In ~he ollowing, the dif~erences relative to the intrinsic semiconductor will not be described in detail on the ground that they become one half of the difference ~et~een the P~ e and the ~I type. As ~ill be stated 1r, de~ail later, the hi8her he impuritll concentra-l~n, ~he lower tne .emperature-depèndency of tE~n - ~fp). In order to attaln a great ener~y level difrerence approxlmate to the ener2y gap Eg and to a~taln a low temperature-depe~denc~
thereof, accordlngly, it i3 fa~orable ~o establish an ~mpuri~y denslty aa close to the saturatlon denslty as possible~
rrhe Fermi levels ~fn and Efp concern not only the density of the donor or acceptor impurity but also donor or acceptor levels Ed or Ea~ which differ according to the impurity.
materials. As the leYel Ed or ~a has an energ~ level nearer to the conduction band or the ~al~nce band res~ecti~ely, ~he Fer~i levèl Efd or ~fa ~omes clo~er thereto. In other words, as the lmpurlty levels ^d and Ea of the do~or and acce?tor ha~e s:^all^wçr levels, the difference (Efn - E~p) of the -~
~er~ level~ co~es ~lo~er to the energy gap ~ o~ t~e se~-i conductor.
~0 As the lmpurity le~el Ed or E of the donor or acceptor a ;

.~
~ - 21 -~ - . .. . .
:

~'S~

is closer t the ~erml level E1 of the intrln~lc se~i-conductor, that ls, as it ha~ a deeper le~el, the difference ~f~ - ~fp) of the ~er~l level~ becomes more dlsta~t from the ~nergy gap Eg o~ the semlconductor. Thls, howe~2r, does not signlfy that the ~e~?erature-de2endency degrades, but signifles that the absolute ~alue o~ the difference (~fn ~ Efp) of the Fermi levels di~lnishes. Accordln ly, the diffQrence (^~n ~ ~fp) o~ the ~ermi levels or the difference of ~ork functlons is a physlcal quanti~y lnherent to the semiconductor ma~erial, the impur~ty materials, etc. ?ro~ an~ther ~iewpolnt it cAn become a ref~rence voltage source paraîlel or si~llar to the energy gap Eg of the ~emicor:ductorD That i5, the difference ~Efn ~ Efp) o~ the Fermi levels ~ se can be-come a reference voltage source which is lower in temperature-dependency and less llable to be affected by the ~an~ac~urin~
conditions than ~he forward Yoltage drop Y~ o~ a PN-Junctlon and the threshold voltage Vth of an IGFET. In consequence, the expedient of taking out the di~ference (Efn - Efp) of the ~ermi levels by the use o~ lmpurity materlals exh~blting donor and acceptor level3 Ed and Ea ha~lng shallow levels can beco~e one method for deri~ing a voltage of a value substantially approximate to the energy gap Eg of the seml-conduc~or. 0~ the o~her ~and, as regards ~he settlng of a voltage value to be obtained, when it is desi~ed to obtain a comparati~ely large reference voltage equivalent to the.
energy gap of the semiconductor, impurlties wh1ch exhlbit shallow levels may be used, and when it is desired to obtain a comparatively small reference voltage, impurities which exhibit deep levels may be used.
Specific Examples of the Selection of Impurity Materials ~ 88~

The relations between the ~erml level ~ and the donor level Ed, accep~or level ~a~ donor denslty Nd, accep~or denslty ~a and ~he temperature T wlll be described in detail ~ith reference to ~l~ure 2 a~ ~lgure 3. ~ri~ to this description, the data on page 30 of the afo~ementioned publication as reprinted in Figure 4 will be re~erred to in order to explain what levels various impurities present to ~he Ge, Si and GaAs semiconductors and to explain how the impuri~ies are utilized in this invention.
F1~ures 4(a), 4(b) and 4(c) are dla~r~s ~hlch show the ener~y distributions of varlous l~?ur'~les for Ge, Si and CaAs, respectlYely~ ~he numerals in the respective diagrams indlcate energy dlfferences ~Ec ~ ~d) from the ~ottom ~c f a conductlon ~and aq to levels located ~bove the center o~
a gap or the ~ermi level Or an lntr1nsic ~emiconductor r-drawn by a broken llne, and indlcate energ~J differ~nces (~a ~ ~v) from the top E~ of a Yalence band ~s to levels located below the gap center E~, the unl~ belng (eV) ln both the cases.
Accordlngly, an im~urity materlal indicated by a sm21}
numerical value in each dla~ram ls suc'n that lts level is close to the bottom Ec of the conduction band or the top ~v of the ~alence band~ and lt is appropriate as an im?urlty for obtaining a voltage close to the energy gap ~g. By way of example, ~or Sl whlch is used most fre~uently at present, le~el differences (~c ~ ~d) and (Ea ~ ~) respectively e~hib~ted by the donor impurities Li, Sb, P, As and Bi and the a~ceptor impuri~ies B, Al and Ga are the smallest, and both the le~el dlf~erences are b~low abol~t ~ o f ~.he 3~ energy ~ap Eg ~f Si. ~hen a ~empe~a~-~r.~ ~hâr.3e fro~ C CX ~s ~15~8~0 neglected, the dlfferenee ~Efd ~ Efa) of ~e ~ermi levels o N-type Sl and P-type Si em~loying these lmpuritl s becomes about 94 ~ - 97-% of the energy gap ~g of Sl, which value ~s ap~roxlmately equal ~o ~g. A donor lmpurit~ and an acceptor lmpurlty which exhlblt the smal:lest leYel differences ~c ~ Ed) and (Ea - ~) next to the above i~purl~ie~ are ~
(abou~ 16 ~5 of 2g) and In tabou~ 14 ~ oî ~g), respectively, The dl~ference (~d ~ Efa) of the ~erml ~evels of ~l-type Si and P-type Sl employlng the respective lmpuritie~ becomes about 0.85 ~g at 0 K, and the de~l~tlon from the ener~y gap ~g of 51 is as grea~ as about 15 ,~ is accordlngly understood th~t the deYiatlon ls much greater than those of the aforementioned impurities.
Thus, one donor impurity selected from the group con-si~ltln~ o~ Ll, Sb, P, As and ~1 and one acceptor impurlt;
selec~ed from the group con~ist~ng of B, .:l and Ca are sultable as ~he impurity materlals o~ ?-.ype and ~-t~pe ~i for ob~aining a Yoitage sub~tantlally equal to the energy gap ~g of Si. The other lmpurltie~ wlll ~e suited ~o .he end of obtaln~ng ~ol~ages considerably smaller than the energy gap Eg of Sl~
Phy~lrs of ~ermi Le~el ~ -Now, ~he di~ference (E~h - ~fp) of Fermi levels will be explained with re~erence ~o Fi~ures 2(a) to 2(d). These figures are diagrams illus~ra~ive of ~he energy levels of semlconductors. ~igure~ 2(a) and 2(~
~ho~ the energy leYel model of an t~-type semicon~uctor and the temperature charac~eris~lc thereof respec~ively~ while ~igures 2~c) and 2(,d) .show the ene~gy }erel ~o~el a~ a ~ty~e se~iconductor a~d the temperature characteristic thereof ~54 respectl~ely.
Carriers in a ~emlconductor consist of the s~m between electron~ nd created by ionl~atlon of ~onor i~puritles ~d and elec~ron-hole pa~rs e~c~ed from a ~alence ~and.
't~en the donor impurity density Nd is suf~iciently hlgh, the number of the excited electron-hole pairs ls negligible, and the number of conduction electrons, n beco~es:
n ~ nd .......................... (1) nd and n are respectively eYalua~ed from the probab~lity at wh~ch electrons are trapped by the donor level a~d the number of electrons whlch exls~ in a conduction ban~, and become:
nd ~ Nd {1 1 ~ exp ( d 15 .~ ~ Nd . .
1 ~ exp ( d) ~T
and ~F ~c 20n ~ N~-exp (~ -) .......... ~3) -~ere, the effective denslty of states in the conduction band, Nc becomes:

Nc n 2( ~ kT) where h: Planc~'~ constant, ~: e~fectl~e mass of ele~tron, k: Bolt~mann's conqt2n~, and T: lattice temperature.
~rom Equations (1~, (2) a~d ~3), Nc exp ( ~ c) ~ _ ~d kT

25 - ~

~ 4~
.

and ~ ~ exp ( ~ c) ~ exp ( ~ ) .~,(5) Nc kT kT

Here, slnce the Fer~i level ls suppose~ t~ lle a~ a posltlon proximate to ~he ~ottom o~ the conduction ba~d ~c~
the flrst term of Equation ~5) ls negli~ible, so that:

l/2 ~E~ ~ Ec) - 1/2 kT~ ...v..(6) This equatlon (6) signlfies the ~ollowl~g~ In the case where the impurity concentratlon denslty Nd is hlgh, not only at a low temperature, but al~o at normal temperature, NC/Nd approx~mates.l (03e) and ~ ~ ~ 0, SQ ~ha. the ~ermi level E~ lles at t~e lnter~edlate point between ~ne bottom - 15 r c ~ the co~ductlon band and tne donor le~el ~d and the temperature-depende~cy beco~es substantially equal to ~he temperature characteristlc of ~c However, when ~he tempera~ure has become sufficien~ly .;
high, ~he electron-hole pairs excited ~rom the vale~ce band predomina~e, the i~fluences of the impurities :
lessen and ~he Ferml le~el EFn ln the ~I-type s~mi~onductor comes close to the leYel E~ of the lntrin~ic se~lconduc~or. ~:
Th~ above rela~lon~hlp ~ 3 illustrated ln ~igure 2~b).
; Qulte the same applie~ to the case of a P-type semiconductor contalnlng only an acceptor lmpurity as ~hown in Flgure 2 When the temperature is low and when the accepto~ impurity den-sity is high, the Fermi level E~p in the P-type semiconductor lies at a substantially intermediate posi~ion between the top v ~ the valence band the ~cceptor level Ea. When the temperature is saised, the Fermi level EFp comes close to the ~ 6 -1154~8~

Fer~i level ~i of t~e lntr~n~ic ~emlconductor.
The te~perature-dependency of the ?erml level ~Fp ln the P-type sem1conductor ls lllustrated in Fi~ure 2(d).

Level E~ and I~pur~ty Density ~Spe~i~ic Example) The relation~ between the temperature depende~cle~ of the Ferml levels Ef~ and E~n and ~he ~mpurlty densities have been explained ln terms of physical properties. Now, by ~aking as a specific example the Si semiconductor, which is used mos~ frequenkly in practice at present, the diference o~ the ~ermi levels (En - Efp) and its ; temperature-dependency in practical use will be explained with reference ~o data on page 37 of the aforementioned publication. ~he data are reprinted in Flgure 3.
15 . In ~onventlon~l processes for manwfacturlng a ~i qe~
conductor integrated circuit, boron (B) and phosph~rus (~) are solely used as the impurity materials. Their high impurity den-sities are lo20 (atoms/cm3). However, even when the donor and acceptor impurity densities Nd and Na are lol8 (atoms/sm3), ;~
which is lower by two orders, the dif~erence ~Efn ~ E~p) of the ~erml le~el3 of the N-type semiconduc.or and the ?-type sem~conduotor 1~ 0.5 - (-0~5) ~ 1.0 ~eY) at 300 K as read fro~ Flgure 3, and lt ~3 a v~lue comparatively close to the energy gap Eg ~ l.l eY at the ~aQe temperature. The change~
of the di~feren~e YersUs te~peratures are Xrom about 1.~4 (eY) to 0.86 ~eY) in a range of ~r~ 200 K to 4C0 ~ ~-70 C
So 130 ~)1 and th~ changlng rate 13 0.9 (~ C) . T'n~s ls a small Yalue of approximately l/3 in co~p2ri~0n with 2 ~o 3 mV/C
i of the rates of ch~nses ~er~us temper~tures of ~he tnre~hold 3~ ~oltage Yth c~ an I~T and the for~ar~ drop vol~a~e 'J~ of a ;

,,~

1~488 diode as stated preYiously.
W~e~ the impurlty densitie~ are 102C) c~ 3 or hlgher~
the ~erml le~el difference becomes ~ubstant'ally equal to the slllcon energy gap (2g~Sl ~ l.l (V), and the changir.g rate ~ersus ~emperature~ becomes about 0~2 .~/C, wh~ch ls a sufficlently s~all value.
Accordln~ly, if ~he impurity concentr2tlons are about 1018cm 3 or hi~her, a tempera~ure-dependency which is, at lea~t, reduced to 1/2 - l/3 of ~hose of the prlor art can be attalned. ~'ore preferably, the l~purlty ~oncentratlons are 102Gcm 3 or ~ her ~a reduction of about l/lO), and most preferably, they are the saturatlon den~itles or dege~ere.e ,.
denslties.

Actual Exam~le Upon what principle can the volt~e correspondin~ to the dif~erence of the ~ermi levels (E~r - Efp), (Ef~ Ei) be ta~en out? An example 1s to u~ilize the dlf~erence of the tbreshold ~oltages Y~h of two MOS~E~s of channels of the same conductivlty type which hare ~e~iGonductor gate electrod~s tha~ are formed on gate insulati~ fllms for~ed under s~stantlally ~he same condi~lons on different surface areas of an ~dentical semiconduc~or body and t~a~ are ~ade of ~a~erials belng of an ldentical semlco~duc~or substance ~for example~ silicon) but having dlfferen~ conductivity types. A specific example o~ this will now be described.
Each of ~gures 59 and 60 depicts the conreptual sectlonal structures of the respecti~e F~T~ formed wlthin a com?le~en~ary ~IOS integrated circuit ~C~.QSIt:) . Here~nafter, for the -~aice o~ breYltr, the MOS tra~si~tor whose gate electrode ls made .

~ ` ' :
of a pt type sem~conductor shall be called the "?+ &ate MO~", the M05 tran-el~tor whose gate electrode ls made of an N+-type semiconduGtor shall be called the "~t ~ate MOS", and ~he MOS
transistor whose gate electrode ls made of an intrinsic or ~-t~pe seml~nduc~or ~hall be called the "i ~ate ~IOS". In Figure 60, the left half shows P~, i and N* gate ?~c~annel ~;OS trans~stor~, while the right half shows P~, 1, and N~
gate N-chann~l MOS transi~tors.
~he difference~ o~ threshold voltages amon3 the ~OSF~Ts (Ql) (Q3) a~d t~4) ~ (Q6) ln Flgure 60 is as in the following t~ble:
: _able ~Unit: ~olt) ., _ . .
~ i Ql Q~ 43 a4 a5 ~6 ., ~ __ . . . ~ __ . ., `~ 5 Ql ~ O~ j 1~1 ~_ _ _ ` _ _ ~ ~ r _~
Q2~ 0~55 ~ ~ 0~55 ~.__ _ ~ .
Q3 1~1 0~55 ~ _ _ _~~
_ ~ 0~55 1 ~1 Q _ _ _ ~)~55 ~\ 0~55 5 ~ ~_ . - _ .
6 _ _ _ 1~1 ~55 ;
s As will be described ~n det~ll later, ~gure~ 73~a) to 73(f) illustrate sectlonal ~ews of prlnclpal steps w~lch ; show that the P~ 9ate MOS and the N~ gate MOS can be fabricated withou~ altering or adding to any of the steps of a conventional process for manuacturing a comple-mentary MOS in'cegrated circul t (CMOS IC) .
~lgure~ 65~a) and 65(b) or ~igures 66~a) and 66(~) ,~

deplct a plan view and sectional s~ruetur21 vle~ of N~
gate or P~ gate P~channel ~OS tran~istors ~o be actually used ln clrcult struc~ures, respectivelyO
Referring to Flgures 65(a) ~d 65(b) or ?i-~ur~s 66(a) and 66(b), 1~ order to form a self-allgnment structure, a P-type impurity 1~ difused in both those end parts _5 and of the gate electrode G for~ed o~ an i-ty~e or lntrinsic :.
~emiconductor which are close to a ~ource tS) antl a dr~n (3), for both the P+ ga~e MOS and the N~ gate MOS because t~e ~OS ~ransi~tor ls of the P-cnannel in thl3 case. In e central part Cp of the gate electrode G, a P-type impuri1:y ls diffused for the P~ gate ~.OS, and an IN-ty~e l~purlty ls dlffused for the N+ ~ate MOS. A reglon l~in which no l~purit~ ls di~us~d~
is pro~ided between the central re~l~n and b~th 1:ne e~d pa~s ES and ~ ~103e ~o the source a~d the ~ralr~. It i~ thus con~idered that the point of difference between l:he ?~ g2te MOS and the N~ gate ~l03 is only whether .he regi~)n of the cen~ra} reg~on part Cp o the gate ls of the P~t~e .~emiconductor or the N-type semiconductor.
In Flgure~ 65~a~ and 65(b) or Flgure~ 66(a) and 66~b), numeral 101 designa~es an N slllcon substrate, numeral 108 a P~ source reglon, numeral 113 a P~ drain reglon, ~umeral 105 a gate oxlde f~lm, numeral 104 a thlck ~ield oxide film, and numeral 111 another oxide ~ilm. As can be understood from Figure 65~a) or ~igure 66(a), a ~lurality o~ P+ ~ource regions 108 are electrically connected in common with one another by an interconnectlo~ layer 114, a plurality o~ P drain re~ior~ 113 are electr~cally connec-e~ ln CO~G~ wl~h e~ch other by an l~terconnection layer 112, and a plurelity o~
3~ gate electrodes G.are elec~rlcally connected ln com~o~ wi~h j~r ,'~

~ ~ 88V

one another by an interconnectlon layer 115.
?urther, in order to reduce as much as possible varlat~on of ~he effective channel lengt~s o~ the MOS
trans~stors attrlbuted to the ~act that ~he ~ ype impuri.y di~used reglons at both the end parts ~S an. EQ o~ the gate electrodes ~ formed for the self-allg.,~ent may shif t onto elther the left or right side (source side or dr~in side) during manufacture on account of the error of mask alignment, the columnq ~f the source regions and the Ar~in re~ions are alterr.ately arranged, and the columns are arr~n~ed so ! hat the left half and the right half may be put lnto line sy~metry with r~spect to th~ channel dlrec~ as a wnol-, Accordln~ly, even wh~n the sh~ ftir.g sf the -.as~i all6~en.
wlth resp~ct to the c~anr.el direcllon ~lef~ward or ri~h.t~;~.r~
shifti~g) ~hanges the effectiYe channel len~ths of tne ~.~l`s ln the respec~lve columns, the average efecti~e c;nar~el len~ths of the P+ gate MOS and the N~ gate ~OS ln the respec-tive column~ connected in parallel ha~e the chan~es ca~.~elle~
as a whole and become ubstantlally co~stant. `~
Figures 73ta) to 73~f) illustrate how the P' Oate ~OS and ~he N~ gate MO~ are construc~ed by the ~se o~ the conventional ~anufacturing process for a silicon gat~ C~GS IC.
In ~lgure 73~a), numeral lOl designates an N-type ~llicon semiconduc~or having a specifi~ res~tance o, l n c~
2~ to 8~cm, on which a thermal oxidation film 102 is grown to O O
about 4,000 A to 16,000 A. A window for selective difusion is provided in the ilm by a photoetching technique. Boron, to serve as a P-type impurity, is ion-implanted in a quantity of approximately loll to lol3 ~m~2 at an e 50 KeV to 200 KeV, whereupon it is thermally di~fused for ~lX~8~0 about 8 to 20 hour~, ~hereby to form a P well region 103 whlch serves as a substrate o an N-channel MOS transistor.
In Flgure 73(b), the thermal oxidation fllm 102 ls fully removed, a new thermal oxldat~on fll~ 104 is formed at about 1 ~m to 2 ~m, and a region of this fll~ ~Qrresponding to the source, drain and gat~ of the .`~,OS translstor ls remoYed by e.ching, Thereafter, a ~ate oxlde film 1O7 ~h~cn ~ 5 about 3OO A - 1,5O0 g ~hick i-~ formed. On the resultant ; substrate, polycrystalline S1 106 ~elng o the i-type or in~rlnsic semiconductor lqi grown to about 2,000 A ~o 6,000A.
By etching, it i-q remov~d with the gate ~3rt C of the ;~OS
; transistor left behind.
In ~lgure 73(c), a-mask oxlde ~llm 107 ls ~'or~ed by : vapor 6rowth, and l~s reglons under wh1~h a P-~ype im?urity is to be dif~used are removed by the photoetchlng technlquen Theraafter, boro~7bein~ the ~^type lmpurity,ls dlffu~ed at a high denslty of abot 102 to 1021 Gm 3 to foFm a sour~e re21On 108 and a draln region 113 of the ?-channel ~OS transistor and slmultaneously to form a gate elec~rode of a P-ty?e semiconductor.
In ~l~ure 73~d)9 as ln the foregoing, a mask oxide film lO9 is formed by vapor ~row~h, and i~s reqions u~der whlch an ~-type lmpurity ls ~o be dlffused are removed by the photoetc~lng techniqueO Thereafter, phosphorus,b~ln~
~5 the N-type impurity3i~ d~f~used at a hlgh denslty of about 102 to 1021 cm 3, to ~orm a ~ource region llO and a dr~ln region 116 of the N-ch~nnel ~OS transistor and s1multaneo~slY
to form a gate electrode of an N-type seQloonduc~or.
In Fl~ure 73(e), the oxide film lO9 1~ r~moved. An o oxlde film 111 w~lch ls approxlmately 4,000 A to 8,0CO A

- 32 ~

~ 8~

thlck is formed by the vapor growth, ~nd lts re lon corresponding to an eIectrode leading-out portion 1~
re~oved by the photoetchln3 technique. Therea.ter, a metal (.~luminum) 1~ evapora-ed, and an electrode ln~ercor.nectlon portion 112 is ~or~ed by the photoetcnin~ techni~ue.
In Figur~ 73(f), the resultant su'ostrate is covered ~ith an oxlde fllm ~eln~ 1 ~m to 2 ~m thiek by vapor ~rowth.
Now, the threshold voltage of the ~.OS translstor employing the semlconductor for the gate electrode wlll be describe~ wlth reference to Figures 5(a) to 5(d). ?lrst, ln the case of the P~ gate ~lO~, the following is indicated from an energy band dlagra~ o~ ~gure 5(a):

~~ Va + ~ ~FP~ ~ 2g ~ q ~ ~ q VO ~ q ~s~
~, + ~ ~B ........................... ,.. -(7) ~Si where YG: Potentlal difference be~ween a semiconductor substrate and a gate electrode (P~ semiconductor), ~ : Electron afflnlty, E : Energy gap, ~.
g ~srf: Sur~ace potential o~ an ~I-type semiconductor s~bst.ate, d~p: F~rmi potentlal of a ?-type semiconductor w~th reference to th~ ~ermi potencial of 2~ lntrinsic sel~icon~u~.tor, ~B: ?ermi potential of the ~' ~ype se~ico~ductor substrate 3wlth reference to ~he Fermi potential of the lntrinslc semlco~ductor , . . .

l:lS~8~3 q: Unit charge of electron, YO: Potentlal-dlf~erence applled to an insulator, Ec: Bot~o~ o~ a conduction band, Ev: Top of a valence band, Ei: Fer~i level of the lntrinsl~ semlconductor. ~:
In Equation t7), the work ~unctlon of the ga~e electrode 1~
denoted as ~MP ~ in potential, and .he work funct~on of the semlconduc~or ls simllarly denoted as ~S~- Then, MP 2q '~P ............................. .(8) s ~. X ~ ............................... .( There~ore, ; 15 vO ~ + BMP ~ ~S1 ~ ~Srf ~ 0) From the relatlon of charge~ in Figure 5(b), ~ -COx~VO ~ QSS + Qi ~ QB ~ ......... ~... (11) .- where COx: capacltAnce o~ the in~ulator per uni area, : QSS: Flxed charges in the lnsulator, QB: ~ixed charges due to ionlzatlon of impurltles ln t~e semiconductor substrate, Ql Carriers ~ormed as a ch~nel.
From (lO~ ~nd (ll), ~COX (~Y~ + ~ ~ ~S~ ~ ~Srf) . :~
QSS ~ Q~ ~ G ............ ,,.. ~12) The gate ~ol~age V~ a~ the time whe~ the channel Qi l~
formed is the ~hreshold vol~age, Therefore, le~tlng Y~hp~
denote the threshold ~oltage of th~ P~ gate MOS, ~hp C l~o ~ si P5r~ - c ~ ~ . t 13 ) ~S~8~0 ` - .

... .
At thls t~me, ~Sr~ ~ 2 d~.
Llke~l.qe, in the N+ gate ~QS transl3tor, only the work functlon ~ o~ the gate electrode dl~fers as f~ w~:

~MN ~ ~ 2q + ~N ..................... (14) Accordingly, the threshold voltage VthN~ of the N t gate MOS becomeq:

VthN ~MN ~Si ~Srf C .(15) !~ 10 OX OX " ```
where ~r~ ~ 2 ~
Thus, the dlf~erence V~hp+ - Vt~y~ of the threshold ;. voltages of the P~ gate ~OS and the N~ gate MOS beoome3:
hN MP ~MN ~FP ~ ~ 16) whlch i~ equal to the dlfference o~ the ~ermi potent~als of the semlconductors ~ak~ng up the gate elec~rodes.
Thl~ can be readlly under~tood from the ~act that, when ~igures 5(a) and 5Ic) are compared, the gate ~oltage at the tlme when the same charge.proflle ls establl~hed ls equal to ~he dlfference o~ the work functio~s of the gate electrodes and the d~f~erence of the Ferm~ levels.
~hile the above descrlpt~on has been made by tak~ng the P -c~annel ~OS t~ansi3tor as an e~ample1 qulte the same applies to the ca~e of the N -channel MOS tran~lstor.
From ~he above, i~ can be understood ~hat a voltaqe ~ substantlally equal to the energy gap Eg can be derlvPd a~
t~e difference of the threshold voltages of the P~ gate MOS
and the N~ gate ~IOS.. As another me~hcd, the ~rolt~e of ~he en~rgy gap Eg can be derlved with the dlf~rence of the 3~ thre~hold Yoltage of a MOS who3e gate electrode ls ~ade of .

. - 35 -, ~154880 ar, intrinsic semiconductor ~hereinbelow, written a~ the ni gate MOS") and the ~hre~hold voltage of the P~ gate MOS
!' or ~he N~ gate MOS.
Let~ing Y~hl denote the threshold voltage of the 1 gate MOS, ~lnce the Ferml level of the lntrlnsic se~icor.ductor - ls O (zero) ~as the ~erml level of t~e ~ntrinslc semlcond~ctor : ls made the reference), the di~ference of the thre~hold voltage3 of the i gate MOS ~nd the P+ ga.e MOS is:
thi - YthP ¦ ~ lo - ~FP ¦ ~ 1/2 3g ,.,....... (17) The difference of ~he threshold ~oltages of the 1 ~at~ iYOS
and the N~ gatc MOS becomes:
IYthi YthN ~ F~ - O ¦ 1/2 ~g ................. ( 18 ) It can be readily understood tha~ the difference becomes a voltage of just a half of the energy ~ap Eg, The ~oltage which 13 obtalned owinz to the dl~ference of the thre~hold.Yoltagea of the 1 gate MOS and the P~ gate or N+ gate MOS is ~ery u~eful in that lt la approxi~ately 0.55 V and sul~able for a low reference voltage s~urce, and that> as wlll be stated later, a reference vol~age source Or hlgh pre~ision i~ easlly obtalned, not only by the ~anufac-turlng proceqs of the CMOS integra~ed c~rcult, b~t al~o b~
the manuSacturlng proces~ of single-channel MOS lntegra~ed clrcu~t becau~e ~he dop~ng of ~ate electrodes wlth an lmpurity can be carried ou~ by one ~tep.
~lgures 67~a) and 67~) to ~lgure~ 72(a) and 72(b) deplct plan patterns and sectional ~tructure~ along llnes A - A o~ the plan pat~ern3~ of P+ gate, 1 gate a~d N~ gate P-channel and N channel ~OS ~ransls~or~ to ~ ac~ually us~d ln c~-cult str~ctures~
In the various figures, as in Figures 65(a) .

~S4880 ' ':
and 65(b) or Figures 66(a) and 66(b), the P- or N-~ype region~ of a source and a drain are formed by tne diffusion of an impurlty by employi~g polycry~talllne Sl for a ~a~k. In order to allow a margin for th~ mssk al~g~e~t between the mask for selectively ~lffusing a ~-t~fpe impu~it~
or an N-type i~purlty and t~e source and drain re~ions, the same impurlty as that of the ~ource and dra~n regions i~ diffused ln both end parts ~S and ED of a ga~e ~lectrGde G ad~oinlng the ~ource S and drain D in both the P~ gate MOS and the N~ ~ate MOS. I~, for example, the ?-channel ;~!OS, boron whlch is ~h~ P-type impurlty ls diffu.~ed. In a central part of the gate electrode, a P-type lmpurlty ls ~lffused for the ?~ gate ~IOS, and an N-type lmpurlty ~s dif~used for ~he N+ gate MOS.
Flguras 67(a) and 67(b), Figure~ 68(a) and 68(b) and ~igures 69~a) a~d 69(b) represe~t plan vlews and ~ectional views of P-cha~nel MOS transistor~ Or the P~ gate, i gate and N+ gate, respecti~ely, whlle ~lgures 70(a) and 70(b), ~l~ure~ 71~a) and 71tb) and ~lgure~ 72(a) and 72(b) represent ~-channel MOS transls~ors of the N~ gate, i gate and P~ ga~e, respectlve}y.
In ~igures 67(a) and 67(b) to Fi~ures 72(a) and 72~b), ln order to reduce to the utmost ~he Yaria~lon of .he effectlve channel Iength~ of the MOS transl~tor~, attributed ~o the fact tnat those region~ a~ both the end part3 Es and o~ the gate electrode~ e, whlch are formed ~or the ~elf-allgnment~and ln which the ~ame i~pur~ty as that of the ~ource and drain regions ls dlffu:se~,~nift to eithar the lef~
or right side (source side or drain side) during manufac-ture on account of errors of the mask alignment, the columns 1~5~0 of the ~ource re~lon~ and the drain reglons are al~ernately arranged, and the columns are arrqnged so that the lef~ half and the rlght half may be put ~nto a llne sym~etry wlth respect to the channel dlrection ~s a wholeO Accordingly, even when the sh~ft~ng of ~he mas~ allgn~ent with respect ~o the channel dlrection (lef~war~ or rlghtward shiftlng) changes the effe¢~i~e channel len~ths of the ~ETs 1~ th~
respec~lve columns, the aYerage effecti~e ¢hannel len3ths of the P~ gate MOS, i gate MOS and the N+ gate MOS ln the respectlYe column~ connected in parallel haYe ~he changes cancelled as a whole and b~come ~ubstantlally constant.
Flgures 74(a) to 74(d) lllustrate how the ?~ gate MOS
and the N~ gate ~OS are constructed ~n the conventlonal ~illcon gate ~MOS manufacturlng process.
~ In ~lgure 74(a), numeral 191 deslgnate~ an N-type sllicon ~emlconductor havln~ a speciflc re~istance Or iQ CQ
.... . .
to 8Qcm, on which a thermal oxidation film 102 is ~rown to about 4,000 A - 16,000 A. A window for selective diffusion is provided in an area of the ~ilm by the photoetching technique. Boron, to serve as a P-type impurity, is ion implanted in a quan~lty of approxiMately lOll - lOl~ cm~2 at an energy o~ 50 KeV - 200 ReV, whereupon it is thermally diffused for about 8 - 20 hours, thereby forming a P well ~egion 103 whlch ser~e~ as a ~ub~trate of an N channel MOS
transi~tor.
In Figure 74 (b), the thermal oxidation film 102 is en-tirely removed, a new thermal oxidation f ilm 104 is ~ormed to abou~ 1 ~m - 2 ~m, and a reglon of thls fi'~ c~rre r~ndir.g to ~he source, dral~ and gate of tne MO~ ~ransistor is removed by etchlng. T~ereafterl a gate o~lde fllm lV5 which 1~54~8~

l~ abou~ 300 A ~ 00 A thlck 15 formed. On the resultant ; ~ubstrate, polycry-qtalllne Sl 106 being o~ the l-type or intrinsic emiconductor lq grown about 2,0CO A - 5,000 g.
By etchlng, ~t ~s remo~ed wlth the ~ate ~art C of the MOS
translstor left behind.
; In Fl~ure 74(c), a mask oxide fllm 107 ls f~rmed by vapor growth, and i~s regions under which a P-type lmpurity ls ~o ~e dlffu3ed are re20ved by the photoetchln~
technl~ue. Thereafter, boron to become ~he ?-type lmpurity at a high denslty Or about 102 - 1021 CDI 3 15 dlffused, to for~ a sourc2 region 108 and a draln reglon 113 of the ?-channel MOS translstor and s~multaneousl~ to form a gate electrode of a P-~ype semlconductor.
In Flgure 74(d), as ln the ~o-e~olns;, a ~ask oxlde ~ilm 109 ls formed by the ~apor growth, and lt~ reglons under whlch an N-type impur~ty lq to be dl~fused are remo~ed by the photoetching technlque. Thereafter, phosphorus to become the N type lmpurity at a hl~h concentratlon of about 102 - 1021 cm 3 i~ diSfused, to form a source reglon 110 and a draln reglon 116 of the N-channel MOS translstor and slmultaneou~ly to form a gate electrode of an N-type semico~duc~or.
Subsequently, the ox~de film 109 is re~oved. An oxlde fllm whi~h ~s approximately 4,000 A - 8,00Q A thlck ls for~ed ~y the ~apor growth, a~d lts part correspondl~g to an electrode }eadlng-out portlon 13 removed by the photoetch~ng technlque.
Thereafter, a metal(aluminum~ lq e~porated, and sn electrode lnterconnect~on portlo~ 1~ formed by the ~hotoetchin~ tech~lque.
Sub~equently, the resul~ant substra~ ls co~ered with ; 30 an oxlde ~ being 1 ~m - 2 ~m thlck by vapor growth.

- 39 ~

l~S~880 Here, ln Flgure 74(d), Q3 and Q4 lndicate MOS translstor~
whlch cons~ltute a conYentlonal C~IOS ln~er~er, and al and Q2 indlcate P+ ga~e and N~ gate MO~ translstors ~or ~enerat~
lng a reference ~oltage.
~igures 75(a) to 75(d) ~how sectlons ln the ~anufactur-ing process of P~ gate M03 and i gate ~OS tran~istors of the P-channel type. In thiq example t the steps up to ~igure 75(c) are the same aq those up to Flgure 74(c). In ~i~ure 75(d), however, the N-type lmpur~ty is diffused wlthout removlng an oxide film lO9b o~erlyl~g the ~ate of the MOSFET Q
Figures f6(a) to 76(d) sh~w sectlon~s in the manufac.uring process of pt gate MOS and N+ gate MOS t~anslsbor~ of the N-channel type.
~lgure~ 77(a) to 77(d) ~how sections ln t~e QanuYacturinz ; process of N~ gate MOS and 1 gate MOS transistor~ of the N-cha~nel type.
Now, a proce~s i~ an N-channel MOS ~emiconductor lntegrated cirouit wlll be explained with reference to sectlons illu~tra~ed ~ Figures 78(a) to 76(e).
(1~ A P-type se~lconduc~or substrate lOl having 2 speclfic re31 tance of 8 - 20~ cm 1~ prepared, and a ther~al ox~datlon fll~ 102 whlch i~ hick lq fo~med on the ~urface of the substrate .
(2) In order to expo~e the semlconductor substrate surface correspondlng tQ portion~ ln whlch ;f~FETs are ~o be formed, selected part~ of the thermal oxldatlon film are etched.
(3~ ~hereafter, a gate oxide ~llm (SiO2) 103 whioh is 750 to ~,000 A thlck is fo~med on the expoqed ~emlconduc~or ~- - 40 -~1154~38 substrate -~ur~ace (Figure 78(a) ) .
(4) ThaS part sf the gate oxide fllm 103 whlc:h ls to come ~to dlrec~ co~tact with a polycry~talllne t~illcon layer is selectively etched, to form a dire ~ cor;ltact hole lO~a. (Fl~ure 7~
(5) SlllcGn ls deposlted by the CVD (Chemical Vapor Deposition) process onto the whole maJor surface o~ the semiconductor s~bstrate 101 ha~lng the oxlde film 102, the gate oxlde fllm 103 and ~he c~tact hole 103a, ~o form .~he polycrystalllne silicon layer whlch is 3,000 to 5,000 ~.
(6) Selecte~ p~rts of the polycrystalllne slllcon layer 104 beins of the i~type or lntrln~ic semlconductor are etched.
(~lgure 78 tc)).
(7) A CVD-mask SiO2 fllm is deposi~ed to a thlckne~ of 2~000 t9 3,000 A on the whole maJor surface of the se~1-conductor sub~trate 101 by the CV~ ~rocess.
(8) The CYD~matl~ S102 fllm 105 is selectively left only at high resistance parts ~uch a~ memory cell load reslstors, and on the polycrys~alline sllicon layer of lntrln~ic level gate portions 104a. (Figure 78(d)).
(9) Pho~phorus is diffu~ed lnto the ~emlconductor 5ub- ;
strate 101, ~o form source reglons and ~rain reglons 106 at an lmpurity denslty o~ 10~ atoms/cm3. At thi'3 tlme, the impurlty ls also introduced into ~he polycry~talline sillcon layer, ~o form gate electrode~ 104b, a dlrect ~ontac~ 1~4c and a polycrystalline ~ilicon intPrconnectlon porticn 104d, (Figure 78(d))o

(10) A P3G (Pbo3pho-Sllicate-Glas~ 107 is ~'or~ed at a thlckne~s o~ 7,000 to 9,000 g on the entlre ma~or ~urface of the t~emi~onductor ~ub~trate 101 ~J

~ 8~

tll) Al (alumlnum) is thereafter evaporated on the whole area of the maJor sur~a~e of the sem~condu~tor ~ub~trate 101, to for0 an Al ~ 108 whlch iq 1 mm thlc~.
(12) The Al film ls ~electl~ely e.ched to form inter-connectlon reglon3 108. (Figure 78(e)).
The prlnc~ple of derlving the di~'ference of ~er~1 levels descrlbed above and actual e~am~les will be brlefly explalned agaln. ~lements ~hown ln ?lgure 58 are enhan~emen~
type p-channel MIS~ETs ~al) and (Q2) whlch are ~ormed on an n-type seml~o~ductor substrate 1. The ~ate electrodes of the respectlve MISFrT~ are made of conductor layers wnich are con~tru~ted ln such a way tha . polycrystalline ~ilicon layer~ are dQped with semiconductor 10purlties o~ dlfferen.
conductlvity types. More specl~ic211y, the MISFE~ C2) are ~abricated a~ ~ollows. As shown ln ~igure 5~, p+-type semlconductor region3 4,5 to form ~he sources and drains of MI3FET~ are selectlvely formed on an n-type ~e~iconductor ~ub~trate ~. Gate insulating ~ilms 2 are forme~ on the area~ of the surface of the semlconductor 3ubstratP between the oppo~lng source and draln re~ion-~ 4,5, and poly-crystalllne sllicon layers 6 snd 6' are ~ormed on the gate lnsulatlng films 2. The polycrystalline sili~on layer to coDstltute the gate 6' of one MISFET (Ql) is doped wlth a seml~onductor lmpurlty of the ~a~e conductLvity type as that o~ the substr~te ~n-type). The polycry~talllne sillcon layer to con~titute the gate 6 of the other MIS~T (Q2) is doped wlth a semlconductor impurit~f of the conductivity type op~os~te to th2t of the substr~te (p~ype).
The threshold vltage~ (~thGl' Vth~2) MISF~T~ ~Ql~ Q~ in the above constructlon are evalua~ed 1~ 0 from the followins equatlons (19) and (20):

V q3 QD
~thGl ~ ~M~ + C ~ C ~.(19) Yth~2 3 ~r,p + S~ ~ cD o ~ ~. (20 ox ox Here, ~Mn and ~Mp denote the wor~ functlons between the ~ates of the respective MIS~Ts tul. C2) and tne sub~trate, COx the gate capacl~ance per u~it are~l Qss the surface charge, and aD the charge ~f ~ substra~e ~epletlon layer.
'~'hen the difference of the thre4hold ~ol.a&es of bo.h the MIS~ET3 ~Ql' Q2) 1~ eYaluated, lt beco~e~ the di~ference (~lp - ~M~) betwee~ the work functlons which are t.qe first terms o~ the rl~h~-hand sides of rquatlons (19) and (Z0), ar,d ~-it can be derived as a volta~e which corresponds to the energy gap of sill~on. Slnce th~s ~oltage becomes a ~oltage s.lpulated ~:
by the energy gap o~ silicon? de~iat~ons ln ~he manu~acture are not l~volYed. In addltlon, the temperature-deperidency 1 extremely smal~. The reason why the threshold voltages of MIS~Ts exhlbit ~reat devlations ls that ~he ~econd te~ms (~ss/Qox) and the thlrd terms (Q~/CoX~ on the rl~ht-hand sldes of Equatlons (19) and (20) fluctuate dependlng upon ~:
~he condltlon~ o~ ~anufac~ure. In this em~odimen~, the ;~
the MIS~Ts ~ Q2) are manufactured under ~he ~a~e co~di-tlon3, whereby the seco~d term~ and third term~ on the ri~ht- hand side~ of E~uat~ons .19 and 20 are msde ~u~-stantially equal. By e~aluatlng the difference between ~.~e right-hand sides, t~e second and th~d terms are can~ell~d ~0 Thus, ~he magnltude equl~alent t:o the energy gap is used as ~15488V

an output volta&e.
Slnc~ the MISFET (Q2) ha~ ~he source, drain and ~a~e electrode ~ormed ~y the use of the semlcondu~tor ~mpurity of an ldentlcal conduct~vlty type, the conventio~al manufactur-lng ~echnology of a ~illcon gate MISFT ln which the seml-conductor lmpur$ty diffuslons o~ lt~ ~ource and draln and lts gate electrode are si~ultaneously carried out can be employed. On the o~her hand, the gate electrode o~ the MIS~ET (Ql~ cannot be formed ~imul~ane~u~ly with the source and drain thereo~ and accordlngly ~eeds to be formod by a separate Qtep. In thl~ regard, a method ls consldered wherein the MIS~ETs (Ql' Q2~ a~ above descrlbed are formed while empioying the co~ventlonal ~anufacturlng technology c~ :
the s~licon gate MIS~T in wh~ch a gate insulatln~ film and a ~leld lnsulatlng film are used as a ma3k. Alternatively, . .
the measure illustrated in Figure 61 may be considered. More specifically, those parts 6a, 6a' o~ gate electrodes 6, 6' of MISFETs (Ql' Q~) whlch are proximate to souree~ and dralns ~re made gate electrode portlons ln whlch a p-type semi-conductor impurlty o~ the same conductl~lty type as that of the sources and dralns lg dl~fused. The ~entral parts o~ tne gate ele~trode3 which are not doped ~lth any ~e~lcor.ductor lmpurlty, that is, which are made of the intrinslc semi-conductor ~i-type) are elec~ively ~ormed wi.h a gate eiec~rode ~5 portion 6b in which a p-type lmpurity is diffused and a gate electrode portion 6b' in which an n-type semiconductor impurity is dif~used, respectively. The parts doped with no ~eml~onduc~or lrpur~ty have been dis?o~ed ln ccn-slderatlon of t~e mlsre~lstratlon of the ma~k al'8n~ent when formlng the gate electrode portions 6b, 6b' - 44 ~

-1~5~8 -of the d~fferent semiconductor lmpur~ie3 in the selected reulons. In thl3 method, ~he gate electrode portlon~
6a, 6b of the MIS~ET (Q2) are formed by the same ste~? as that f~r the diffusion of th~ sour¢e and draln.
Each of the ~ISFETs ln the above con~tru~ion has a gate electrode whlch ~s ~ade up of the plurality of ga~e electrode port~ons. The plura}ity of gate electrode portions are connected in common and the diference of threshold :
voltages of both the MISFET-q (Ql' Q2) are taken, whereby threshold Yoltage components based on ~he electrode portlons of the same ~tructurès (gate electrode portions 6a and 6a', and l-type electrode portions~ ln both the ~iIS;~Ts (C~ 2) are canceled In addi~lon, regarding the ~I5~Ts owln~ to the gate electrode port~ons ~b, 6b'~, the 3econd and third . terms o~ the rlght-hand sldes of ~uatlons (19) and (20) are not cancelled. As the difference ~oltage, there ls obtalned the voltage whLch corresponds to the sillcon el~ergy ~ap bein3 the difference of the work ~unctlon between the ¢entral : parts 6b, 6b' of ~he ga~e electrodes and the s~lbstrate as de~crlbed prevlously, and whlch ls approxlmate:Ly l.l V.
Figure 62 ~hows a complementaty lnsulated ~ate field-effect translstor integrated clrcuit ~CMOS~C~ accordln~ ~o ; another embodlment of this in~entlon. P-channel MOS transl3~0rq A~ B and C are ~ormed on an N-type slllcon body l, ~hile i~-channel MOS tran~lstor~ D, E and ~ are formed o~ a well layer ~ in whlch a P-type lmpurlty is diffused A~ a low concentration. A reference voltage generator devlce is constructed by exploltln3 the ~lfference o~ the ~hreshold ~oltage~ of the MOS trans'stor~ A and B, .he ~tOS ~ransl~tor~
~C A and C or ~he ~OS ~ransistor~ ~ and C, or the difference of 115~88~

the threqhold voltages of the MOS ~ranslqtors D and E, the MO~ translstors D and ~ or the MOS tra~sls~ors E and ~.
Here, numeral 3 desl~nates a thlck field oxide fllm ~SiG2), and numeral 4 a gate oxlde fllm (SiO2). Nu~eral 5 deslgnates a P-tyPe semlconducto~ region for the source or draln of the P-channel MOSFET, and numeral 6 an N-type s~miconductor reglon for the ~ource or drain of the N-channel MOS~ET.
~umeral 7 ~ndlcate~ P-type polycrystalline sil~co~, n~meral 8 N-type ~olycrystalllne sillcon, and numeral 9 th2 lntrinsic .~emicondu~tor or l-type polycrystalline sillcc~. ~he reference voltage generator devlce derlYes the ~erml level dlf~erence amon~ the materlal~ 7, 8 and 9 ln the ~orm of the Yolta~e.
~igure 63 show-~ an embodlment which is a further improve-~ent on tne embodlment of ~lgure 62. P-type lm~urlty layers lO shown in Figure 6~ are dlsposed under the gate oxide films 4 ln a manner to ov~rlap wlth the central parts 8 and 9 of the gate electrodes of the respective ttansistors B and C ln Flgure 62, and the transistor A 1~ also pro~ided wl~h a P-type lmpurlty layer lO so as to have an effecti~e channel length equal to t~ose of the transistors B and C.
Further, N type impurity layers ll shown in Flgure 63 are disposed under the gate oxide ~ilms 4 in such a manner as to : overlap with the central parts 7 and 9 of the gate electrodes of the re~pec~lve ~ransi~tors E and F ln ~igure 62, and the transistor D ls also provlded wlth an N-type ~purl~y layer

11 so as tO have a~ effectl~e channel length equal to thoae -: of the trans~stors E and ~. ~he effectl~e Ghannel ~en~ths of the translstors A, B and C or ~he transistor~ 3, E and r can be made auba~antlally e~ual by dlsp~sing the P-type ~0 impurity layers 10 or the N-type lmpurity layers ll.

Accordln~ly, the characteristlcs between the draln cur.ents and gate voltages o the translstors A, B and C or the tranQlstors D, E and F become curves whlch are parallel to one another and whlch shlf~ ln t~e dlrectlon Or the gate ~olt~ge axl8 by the dlfferences of the ~er~i lev~ls of the polycrystalllne slllcon materials at the central parts of the gate electrodes of these translstors. Therefore, the d~fferences of the threqhold ~oltages o~ tha tr2nsls~0rs can be derived wlth high prec~s~on in reference voltage generat~r clrcu'ts to be descrlbed later.
Th~ tem~e.ature-d~pendencles of the differences of :he thres~old voltage of the thre~ sorts of IG~ETs are v~ry small Oecause the temperature-dependencles of the dlf~erer.ces Or the ?erml levels of the gate electrode semlconductors are low.
Fl~ures 79(a) to 79(e) lllustrate a method o~ man~fac-turlng the ~OSIC shown ln ~lgure 63.
(a) A.low concentratlon P-type well reglon 102 ls formed ln an N-type slllcon body 10~ by the conventlonal selectl~e dl~fusion process. Subsequently, a fleld oxlde ~ 103 i8 formed. After for~lng a gate oxlde ~llm 104 ln reces~e~ o~ the fllm 103, a P-type lmpurlty layers 105 and an ~-type ~mpurlty layers 106 are Sor~ed by the con-ventlonal selectl~e lon lmplantation processes.
(b) Polycrystalllne 3111con gate elec~rodes 107 are formed by the conventlonal chemlcal vapor deposltlon and photoetchlng. At thls stage, the electrodes 107 are of the lntrlnslc ~emiconductor.
(c) A mask oxide fllm 10~ ls ~or~ed on sel2c.~d areas by the chemlcal ~ap~r depos~tlon. Uslns lt as a masX, source ~5~ ~ 0 and draln.layer~ 109 of ?-channel ~SOSFET~ and ~-type polycrystalline layers 110 are ~ormed by the ~electlve diffuslon of a P-type lmpurlty.
(d) A ma~k oxlde film 108' 1~ formed on selecte~ areas by the chem~cal ~apor deposition agaln. Using 1~ as a ~ask, source and draln layers 111 of N-channel r`!GSFcTs ar.d ~ pe polycrystalllne layers 112 are formed by the selec~ive diff~sion o~ an N-~ype lmpurlty.
(e) A phosphosllicate gla~s ~113 113 ls deposited, contact holes are formed ~herelr., ~nd aluminu~ electro~es 114 are for~ed Then, the deYice ls completed.
~gure 64 shows a~other embodlment of the ~tructure of I~FETs whlch ~onstitute the reference v~ltage genera;or de~lce of thls lnventlon and which have gate electr~es o~
dlfferent Ferm~ l~vels. Here, IG~ET~ A, B and C have a gate ~:
ele¢trode whlch 13 made of ?-type silicon 7, a gate electrode whose both end~ are made of P-type slllcc)~ 7 and who~e ; central par~ 1~ made of lntrinslc sil~co~ 4 and a gate electrod2 whose both ends are made Or ?-type silicon 7 and who.~e central part ls made of aluminum 12, respe~tlvely.
These gate electrodes are overlying on the sate oxlde f~lms (S102) 3 whlch are for~ed on dlfferent sur~ace areas of an identlcal N-type slllcon body 1 under subs~antlally ~he sa~.e condition~. Further, the IGFETs have source and drain layers 8. A~ to the threshold voltage~/ when the threshold volta.~e YT~ of the IGF~T A ls made -0.8 Y, that of the IG~ET ~ beco~e~
approxlma~ely -1.40 Y, and tha~ of ~he IGFET C becoQes approxlmately -}.95 V. They produce differences which are ~ubsta~ially equal to the dlfferen~es of the ~r~i levels of the Si and Al materlal~ at the central par~s of ~he gate electrodes.
Th~a embodi~ent ha~ been made w~ th note ~aken of the fact that the ~emperature-dependency of the difference of ap~roximately 1.15 eV between the ~er~i levels of the hi~h concentratlon P-type sllicon and the aluminu~ or the dlfference of approx~mately 0.60 eV between ~he ?Prmi levels of the intr~nslc sllicon and ~he aluminum is lo~.
~l~ures 80ta) to 80(d) lllustrate an e~bodiment o~ ~
method of ~anu~acturing a P-channel ICFET integrated cl~cuit whi ch ~ncludes all the IC~ETs Ag B and C shown in ?i~ure 54.
(a) ~ thlck fleld oxide film (SiC2) 2 havlr.~ recesses is formed on the surface of an N-~ype sil~con ~ody 1, a ~a.e oxlde f~l~ 3 ls formed in the recesses, and a ?olycryst2111~.e qillcon layer 4 ls deposlted by the chemi~al vapor depos~t~or.
~he polycry~talllne sllicon layer 4 ls of the intr1nsic semlcon~uctorO Further, a ma~k oxl~e fil~ S is formed on a part of the layer 4 by the chemlcal vapor deposition.
~b) The polycrystalllne ~lloon layer is selectlvel~
remoYed by the conventional photoetchln~ process, and a P-~ype impurity such a~ boron ls thermally diffused, ~o form source and drain layers 8 and ?~type polycrystalline sillcon layers 7. At thls time, the part of the polycrystalllne -.
sillcon layer 4 coYered with the oxide fil~ 6 ls held int.lnslc.
(c) An lnsula~ing f~lm 9 such as phosphosillcate ~5 glas~ film owing to the chemlcal vapor deposl~lon is de-.poslted, and contact hole~ are formed therein. At thls t$~e, a contact hole 1~ 1~ slso formed in the central part of a gate ele~trode in an area to become an IGFET ~.
~d) Alumlnum electrodes 11 and 12 are for~ed, and a 3C heat treatment ls copducted at 380 ~o 540 ~C ~or 30 mlnutes ~ 8~

to ~ hours. Then, ~he polycrystalllne slllcon at the contact hole 10 dif~uses towards the upper surface o~ the ; aluminum layer owing to its Alloyin~ reac~ion with the ~`
~lumln~m, and a structure ln whlch the alu~inum and the gate oxide fllm l~e.ln direct contac~ is es.ablls~ d.
The method of manufacturl~g the ?-channel IG~T in~e~rated circuit as lllustrated ln Figures 8C(a) t~ ~C(d) lq also applicable to ~he manufacture of a complementary IriI3 lnteQrated circuit ~ubstantlally as lt is.
The alloylns reaction may be replace~ with an e~?edien.
ln which the central part of the gate electrode ~s r~moved by photoetchin~, whereupon alumlnu~ 1 brought into diAec~.
contact w~th ~he gate lnsulatln3 fllm.
Th~ reference voltage gener~t~r dev~ce ~a~ed on such a constructlon exhiblts a 3mall temperature-d~pendency and small manufacturlng deviations, so that 1t can be utilized for varlous electronlc circu~tq.
Flgure Sl~d) show~ the ~tructure o~ IG~ETs A, B, C and D whlch have threqhold voltage dl~erences based ~n the ~er~
level dlfferences of gate electrodes ln accordance with another e~bodl~ent of this ~n~entlon. The ICFET A ls a P-channel ~OSFET ha~lng a gat~ electrode made of P-type slllcon 11, whlle the I&r~ET B ls a P-cha~nel MOSF~T h~vlng a gate electrode w~ose both end parts are made of P type slllcon 11 and whose central Fart is made of N type s~licon 8. The IGFET C ls an N-channel MOSFET hav~ng a gate electrode made o~ N-type sillcon 8, wh~le the ICFET D is an N-channel : MCSFET having a ga~e electrode whose both en~ parts ~re made of Ntype s~licon 8 and whose central part ls made of P-type silicon 11. ~ reference ~oltage generator device ~s con.s~ucted ~ 880 by employlng a voltage based on the difference of the thre~hold voltaga~ of the MOSFETs A;and B or the ~OSF~Ts C an~l D.
Flgures 81ta) to 81~d~ lllu3trate a method of fabrlcat-in2 a ~OS lntegrated circult whlch includes the IG?ETs A, B, C and D. :
~a) A P-type well reglon 2 ls for~ed ~n an N-type silicon body 1, and a thlck field oxide fllm 3 havln~ recesses ls formed. ~hereafter, a gate oxlde fllm 4 is for~ed ln the rece.qse~ of the oxlde ~ilm 3, and a film 5 of polycrystalline slllcon bein~ the ~nt~ln~lc semlconductor lq deposlted and worked by the photoetch1ng proce~s.
(b) A ma~k oxide fllm 5 is formed on ~elect2~ areas by chemical vapor deposition. using i~ as a mask, an N-type lmpurity such as phosphorus ls diffused lnto 3el~cted reglon~, whereby N type regionq 7,~o beoome the sources and dralns o~ N-channel MOSFET~ and N-type polycrystalline layers 8~are ~ormed.
(o) A mask oxlde fllm 9 i3 f~r~ed on selec~ed areas by chemical vapor deposition, Using it as a mash;, a P-type 1mpurity such a~ boron 1~ ion-lmplanted, whereby P ty~e regions lO,to become the qourc~s ~nd dralns of P-channel MOSF~T~ and P-type poly~rystalline silicon layers 11, are formed. He~e, when using boronl the oxide film 9 ls m~de about ~,000 2 ~hlc~, ~nd an lmplanta~i~n energy o~ ~0 to 50 KeY and an ~mplanta~on quant~ty o~ ~. x 1015 to 1 x 1016/cm2 are approprlate. The actlvat~o~ o~ the implanted ons 1~ ~ultably don~ by a heat t~eatmer.t at goot~c ~or 10 minutes to at l,OOdC for 30 m~nutes~
The diffusion of the N-type impur~t~ in the step (b) -.~.-r ~ - 51 -~154~8V

may be performed a~ter the step ( c) . In ~hls case, the N-type lmpurlty ~lfXus~on lndicated in the ~tep (b) had better be executed by ~he lon lmplanta.~on of phosphorus or the like. When using phosphorus here, the oxide fll~ 6 ls ~ade about 3,000 2 t:~lck, and an ~mplantatlon energy of 60 to 100 KeV and an lmplantatlon quantity of ~ x 1015 to 1 x 1016 /cm2 are approprlate. Sui~able for the acti~ation of the i~planted ~ons i~ a heat treatmen~
at gooc for 10 minute~ to at 1,000C or 30 ~lnutes. By carrying ou~ the doplng wlth the P-ty~e impurlty ln thi~
manner, the heat treat~ent after the doping w~th the ~-type impurlty can be relieved, ~o that the channel portlon~ can ; be pr~ented from ~eln~ doped wlth the ?-type l~purlty.
(d) J~fter depoqltlng a phoqphoslllcate 31as.~ fll~ 12 by chemical vapor deposition, contact holes are Eormed, and aluQlnum ~lectrodes 13 are S4r~ed. Then, the devlce ls flnlshed.
Referring aga~n to Flg~ure 58, another e~bodlment oS
thls lnventlon will now be described. In the figure, a P-channel MOSFET (Ql) has a g~te electrode made of ~-type poiycry-~talllne sllicon 6', ~nd 8 P-channel ~OSFET ~Q2) ha~ a gate electro~e made of P-type polycry~alllne sillcon 6.
Since the~e ~ETs are manu~actured under substznt~ally ~he ~ame co~dition~ except the condu¢ti~lty type of the gate eleetrod~, the dlrference of the threshold Yolta3e3 Yt~ of both the FETs ~ecomes substantially e~ual to the difference of the ?erml le~els of the P-type silicon and the t~-type sillcon. The gate electrodes are d~pe~ wlth A e~pectl~e impurlt~es near the .~aturation denslties, and the ~0 dlfference become~ substa~tlally equal to the energy gap ~g - 52 ~

, , ~ 488~
-, Or slllcon (approxlmQtely 1.1 V). The Vth-difference can be take~ out at hlgh precision by maklng the channel dl~enslonq of both the FETs equal, a~d it is ut~li2ed as a reference ; voltage source~
Slnce a re~erence ~oltage ~enerator device based on sjuch a construction exhiblts a ~all temperature-dere~dency and ~mall manufacturing deviatlons, lt can be used ~or varlous electronlc clrcuit~.
In Fl~ure 58, numeral 1 deslgnates an ~-type slllcon body, : :
numeral 3 ~ thlck fleld oxlde fllm, numeral 2 a ~ate oxlde fllm, numeral 4 a P-type source region, a~d numeral 5 a 2~
type draln reglon. Here, the N-type polycrystalllne sillcon gate 6' has a qtructure which 13 doped wlth botn an ~-Sype lmpurity and a P-type l~urity, the denslty o~ the N-type i~purity being 1,5 tlmes or ~ore hlgher than the de~s~ty of ~he P-~ype lmpurlty. Alternatively, lt has a structure which ls doped wlth an N-type lmpurity, almo~t no ?-type l~purity belng eontalned, and neverthel~s, whlch ls self-alig~ed with the ~ource and drain, ~ : ;
The rea~on why the den~lty of the ~-type i~purlty needs to be 1.5 tlme or more h~gher than the denslty of the P-type impurlty i~ a~ follows. In the ordinary hlgh-denslty lmpurlty doplng technlques, the control of a dens~ty ls s~bJe~t to deviations of ~set value ~ 2Q ~) or ~o. ~ccordin$1y, the : ~5 ratlo between the devlatlon~ of the N-t~pe lmpurlty densl.y and the ?-type impurity denslty ~ecome~ ~1.5 ~ 0.3)~ 1 0.2).
Slnce the mini~um value o~ ~hl~ ratlo become~ 5 the ~erDi level of the polycry3talllne ~llico~ Aoped wlth bo~h the N-type an~ P~type lmpuritle~ varle~ greatly.
~0 I~ order to allow some extent of manufacturin~ dlsperslon, ~5~880 accordingly, the ratlo ~f the i~purlty densl~le~ needs to be l.5 or greater wlthout fall.
Flgures ~2(a) and 82~b) lllustrate a method of manufac-turin~ ICFE~s ~or .~et~ln~ the ratlo of th2 impurlty densltles at l.5 or greater.
(a) An N-type silicon body l at a ~:omparatlvely low 1~pur~ty.den~1ty (fcr examplef below 5 x lOl6 cm 3) is oxidized to form a th~ck oxlde f1lm 2 for lsolatlng element~.
After form~ng a gate oxlde fllm 3 in reces~e3 of the fll~ 2, an intrln~ic ~emlcondu~tor polycrystalline slllcon ilm ~t 6 and 6' i3 deposited by chemical vapor deposition.
~; ~urther, a ~ask oxlde f1lm 7 19 for~ed on a ~elec~d area ~y the chemical vapor depo31tlon. Uslng the oxlde fllm 7 as a ma.~k, the polycrystalline silicon fllm 6' is doped wl~h an N-type 1mpurity ~uch as pho~phorus or arsenlc ~electively and at a high denslty tfor example, above 5 x lOl~ ~m 3).
Thus, the N-~ype polycryqtalline sllicon fl-lm 6' ls obtained, tb) h~ter removihg the ~aqk oxlde ~llm 7, the working of a polycrystalline silico~ gate electrode is done by photoetchlng, and source and draln lmpurlty layers 4 and 5 are formed at a low denslty ~for examp}e, below 3.3 x 1018 cm 3) by thermal dif~usion o a P-type impurity such as boron.
Here, th~ den~i~y of the N-~ype lmpurity with whlch the polycrystalllne ~llm 6' i~ doped ln the s~age ( a) ls made 2S 1.5 tlmes or more hlghar than the density of the P-type lmpurl~y wl~h whlch ~he polycry~talllne ~ con ~llm 6' lq doped at the ~lme of the P-~ype l~?urlty d1ffu~10n ln the s~a~ (b), whereby the polycry~talllne sillcon gate 6' ls held at the N-type.
Flgures 83(a) to 83td) 1llustrate a~other method of . .

~54~80 ~anufacture according to ~his lnventlon. ~lgure 83(a) ~hows the same manufacturinb step ~ in ?lgure 82(a).
(b) Aft~r remo~ing the mask oxlde film 7, the proces~lng of a polycrystalllne 3illcon gate electrode ls done by photoetch~ng. Tnereafter, usln~ the ~olycrystalllne sillcon gates 6 and 6' a~ a mask, the gatQ oxide fllm whl~h overlles parts corresponding to sources a~d drains to be form~d ls r~-moved, whereupon ~he resultant slllc~n body ls sub~ected ~o oxidation in steam at 750C to 900C for 60 seconds to 600 second~. In the oxidation, the oxide film-~rowth rate of the sillcon surface depend~ upon the dnns~ty o n impuri ~y contained in the silicon. The oxide film-growth rate becomes very high when the imp~rity density is at least 5 x 1ol8cm~3, preferably 102 cm~3 or hi~her.
Therefore, comparatively thin oxide films 8 and 10 of 20 to 40 A are respectlvely formed on the surface of the parts corresponding to the source and draln and having the compara~lvei~ low lmpurlty den~lty and on the ~urface of the intrins~c polycry~talllne ~llicon 6. on the other hand, a comparatlvely thlcX oxide f~l~ 9 of 70 to 200 ~ is for~.Ded on the ~urface of the N-type polycrystalllne sillcon ~ate 5' havlng the comparatlvely high lmpurlty density.
(c) Boron can pa~s through a~ oxide film of a thickness of at mos~ 40 A by thermal difusion, and canno~ pa~s ~hrough an oxlde fllm o~ a thlc~ne~s of at least 70 g.
Therefore, boron i~ ~ubse~uently thermally dlffused a~
950 ~o l,OC0 C for about 20 minu~es~ Tbus, the boron peneJcrates through the comparatively thin oxide f ilms 8 and 10 to f orm ~h~ P-typ~e impur~ty layer;, 4 and 5 and .he ?~ ~-ype ~0 polycry~talllne ~llicon layer 6. At ~his tlme, the ~;-.ype .~5~8~

polycrystalll~e slllcon layer 6' i~ protected by the ccm-ratively thlck oxide fllm 9, and lt ls no~ doped wlth the boron. A3 an a}ternati~e expedlent, before the ther~al dl~fuslon of boron~ the o~lde fllms are etehe~ wlth an etchant consisting o~ H~: ~2 = 1: 99 for 60 seconds, to : remove the oxlde ~llms 8 and 10 and to leaYe the oxide fll~
9 with a thickness o~ 40 - 50 A. Therea~ter, the thermal dlffus~on of boron ls carrled out. Thus, a slmllar ~tructure ls obtained.
(d~ Thereafter, a pho-~phosillcate glas3 film 11 is formed, contact holes are formed, a~d alumlnum electrodes

12 are for~ed. Then, the fabrlcatlon of .he devlce ls completed.
Although the present method of manufactu.~ has been explalned as to the caqe o~ the sill~on gate P-ch~n~el ~03~Ts, qulte the .~ame applles to the case of P-channel l~'OSF~T~ ln a sillcon gate C~IOSIC.
; Now, circuita accordlng to embodiments of thls l~ven.lon for derlvlng the dlf~erencQ of the threshold voita~es V~h of the MOS translstors wlll be explalned, Although ~he clrcuits descrlbed below can become ex-pedients for ~aking ou~ ~he dlf~erence~ of the Fer~l levels (Efn E~p), (Efn ~ E~) and (El - E~p~ they are ~urther appllcable a3 reference vol~age generator devlce3 wh~ch~ in general, utillze as ~ reference Yol~age a ~ol~age based on the difference o~ the threshold ~oltages V~h o~ FETs hav~n3 unequal threshold voltage values.
Flgure 6tb) shows a clrcuit whlch genera~es voltage~
correspond!ng to thre~hold vol~ages o~ MOS tran~lstors.
Transl~tor~ Tl and ~2 cons~ruct the so-oalled MOS.diode3 .

~5~8~

ln ~hlch drains and gates ~re connected in common, ~;
Io deslgnateQ a conqtant-current source, and Tl and T2 lndlcate MOS~T~ whlch have unequal thre~hold voltages '~thl and Yth2 as indicated in ?lgure 6(a) and substantially equ~l mutual conductanceQ ~. Lettlng the ~raln volta3~s of 'he re~pec~ive tranQistors be Yl and V2, 1/2 ~ (~1 ~ Vthl)2 1/2 ~ ~V2 - Yth2)2 ... ....... (21) Therefore, ; Vl ~ Vt~} ~ ~2 Io/~

V2 ~ Vth2 ~ ~ ........... (22) By takln6 the d~fference of the drain volt2ges, the di~ference of the threshold voltageq can be derived.
~ the constant-current source~, suf~lclently high reslatance~ may be uqed. If thelr charac~eristlca are unifor~, dif~usion resistanc~,polycrystalli~e Si resistances, resistances formed by ion implantation, or high resistances ~ormed of MOS transis~ors can be used.
~hen, ln thls circu~t, the N+ gate P-channel MOS 2nd the P~ gate P-channel MOS prevlou~ly expla'ned wlth ref2rence to Flgure~ 58 and 59 respecti~ely are u3ed a~ ~he trzr.31stors Tl and T2, that dl~ference (Efn ~ Efp) of the ~erml levels of the N-type ~emlconduc~or and the P-type ~eml~onductor which is a value substant~ally equal to the dlfferenGe of the thre~hold voltage~ can be de~lved.
Beslde3 by ~aklng ~he compcsl~lcns of the gate electro~e~
dlferen~, it is posslble to e~dow ~he unequal thresho~d voltage~ by, for example, implanting ions into the channelY, ~ 57 -llS~1~80 alterl~g the thickne~es of a doped ~ate oxide or ~ate insulatin~ fllms I etc. When quch a mea3ure ls applied to the circui~ of Flgure 6(b), the d~fference of threshold voltages corre~pondlng to ~he i~planted ~uantltle~ of the lons or the dlfference of threshold voltaces correspondir,~
to the quantlties of an lmpurlty wlth whlch the ga~e lr~sulat-ln~ films are doped or corre~pondi~ to the thScknesses of the gate lnsulat~ng ~llms can be simllarLy 8erlved as .he reference voltage, For example, the lon ~mplantatlon 1~ ch hl~her in the preclslon of the lmp~rlty concentratlon than .he conventional difPuslon because the quantl~y of lmplantation can be ~onitored in the form of curren~. ~13ure 7 illustrates thls sltua~ion.
_ven if, lettlng Tl denote the charactarlstl~s of ~OS tr~nsl~.ors before the lmplantatlon of lons, they have been lndivldually dispersed during manufacture and the threshold value~ are indlviduall~ ~hift~d by QVt~ on account of the lon lmplanta-tlonl the magnl~ude ~Vth belns the difference of both the thre~hold Yoltage~ i5 determlned by the quan~lty of th,e ion implantation and is there~ore dispersed to an extremely small extent. It can accordin~ly be similarly used as a reference voltage with little dispersions of manufacture. More speci~ically, letting Vthl indicate the th~eshold voltage o~
the MOS transistor Tl which is not subjected to the ion implantation, likewise to Equation (15):
Vthl ~ d~S ~ 2 ~ SS _ ~B ,.,~,,0.~. ~23) ~ettlng ~QB ~ndlc~te the ~ncre.~ent Or flxed ~.a~es 1~ rhe sub~trate due ~o ~he lon implan~a~lon, the threshold ~olta 3~ Vth2 of the MO transl~tor T2 subJe~ed ~o the ion lmplantatlon ~` - 58 -~R ~

115~88 becomes:
th2 ~ ~MS 2 ~ _ SS _ ~ ....... (24 Accordingly, B
Vthl ~th2 COX ....... ~25) The temperature varlat~on of this dlfference vol~age between the thre~hold volt~ges ls extremely small because QB ls almost lnvarlable agalnc~ temperature changes.
Addl~lonal great ad~antage3 are that the re~erence voltage can be freely set by the quantity of ion lmplantat~on and ~hat the device can be e~slly pro~u~ed even by a single- :~
channel ~IOS manufacturin3 proces~.
~l~ures 8 and 9.show example~ of clrcult~ wherein an N+-~ate ~T Tl and a P~-gate F~T T2 havi~ une~al ~hreshold voltages as in the case of ~igures 6(a) and 6(b) are u~d, and the ~ET Tl ls co~nected in the ~05 diode for~ and i~
connecte~ ln serleq with the FET T2, to derive the difference of the threshol~ volta~es, I~ is ~uppo~ed that the FET Tl has a ~hreshold ~olta~e V~hl, whlle ~he FET T2 ha~ a ~hreshold vol~age Vth2.
Under the conditions in which a resistance Rl is sufficiently great as compared with ~he impedance of T
and that a resi~tance ~2 is sufficiently great as compared with the impedance o~ T2 Vl - V2 - Vthl ............... ~........ ~26~

1 i th2 ......................... (~7) Therefore, V2 ~ Vthl ~ V~h2 ............ ~r~...... (28) ~lgure ll(a~ shows a devl~e wherei~ volta~e~ correspond i~g to the thre~hold volt~ges of a~ gate ~'CS Tl a~d a P+-ga~e MOS ~2 are applied to Doth ter~lnal~ of a ca~acitor _ Sg _ ~15~8~0 Cl connected to the ~.0~ translstors, and a voltage held ln the capacitor ls taken out as a dlf~erer.ce voltage.
~lgure ll~b) deplcts ~he operating timlngs. ~OS ~ET~ T5 and T6 are turned "on" by a clo~k pulse ~I~ to charge the difference volta~e of the thre hold voltages Vthl and Vth2 of the MOS F~T ~1 and T2 in a capacltance Cl.
After turnlng ~he MOS F~T~ T5 and T6 "off" by the pulse ~1~ a MOS FET T3 ls turned "on" by a clock ~2 so as to ~round a node ~ of Cl. Since, a~ thls timel the difference ~oltage of the thre~hold vol~a~e~ lq re~ai~ed ln Cl, t~.e di~ference potentlal appears at a node ~ of the caFacltance Cl as lt ls. In the case of a use for volta~e detector circuit to be stated ater, the potential of the node ~ at thls ~'Qe can be employed as a reference voltzg_ as i. ls. In order to permit the use ln a more general form, however, ~ransmlssion ~ates T~ and T~ are turned "on" by a clock ~3 wlthin a perlod of time in whlch the high level sl~nal of the clock ~2 ls enterln~, the potentlal la held ln a capacltance C2 con~ec.ed to the non-lnverting input (~) of an 02er2~10nal a3plifler 5, and the potentlal ls recleved by the 30-called voltage follower in whlch 100 ~ of an output ~s nega~lvely fed back to the lnver~lng input (-) o~ the operational amplifler 5. Then, as the output of the ~ol~age follower, the diff2rence of the threshold ~oltage3 of Tl and T2 is obta~ned a3 a reference voltage when the internal ;mpedance is sufficiently low .
~i~ure lO(a) ~s a clrcuit dlagram showing an embodlme~
of a dynamic type differen~e voltage output circui. whicn explolts the difference of the threshold volta5e~ of an N -gate N-channel MOS Ql and a P~-gate N channel ~.CS ~2 48~0 .
In this circult, the gate~ and dralns of the ~lIS~Ts (Ql' Q2) are lnterconnected~ and they are connected to a bla~
power supply VDD ~hrou~h lo~d resistors (~1' R2~ A ~apacitor (C) 1~ i~ter~osed between the gate and drain termlna~s, and the d~fference component betweeh the threshold volt2ces of the MISFETs (Ql' Q2) ls stored ln the capacltor so as ~o provide an output. More specifically, a P-channel MISFET
(~3) whlch i~ dri~en by a clock pulse (~ i3 incorpora-ed between the gate and source of the MISFET (~1) of the s~aller thre~hold voltage~ The respectlve load re~iYta~ee~ of the MIS~Ts (Ql' Q2)' and the "on" res~ance of the ;~IIS~ET (~) ls made sufficlently smaller than the "on" resistances Or the ~.ISF~Ts (Ql~ ~2) Owing to suc~ a clrcult a~ran3emer.4, as shown ln an operatlng wavefor~ ~lagram of ~lgure lC~3), when the cloc'~ pulse ~ has reached a low level to turn the MIS~E~ (Q3) "on", the difference -(V2 - Vl) between the draln voltage~ (threshold voltages Vl, Y2) of both the ~I~F~Ts ~ 2) 1~ provlded from the drain of the ~I3F~T (~2) or the terminal of the capacltor (C) remote from the MISF_T ~3).
The difference voltage output slmllar to those of the fore- .
golng clrcul~s are obtalned by sampllng it at the time (~).
Figure 12 ~hows a reference ~oltage ~enerator devlce whlch utlllzes an N~-~a~e ~IOS Tl a~ well as a P~ -sate ~'OS
T2 and a capacltance C2 slmllarly. ~ MOS FrT T8 ls turned non" by a clock ~1' At ~hls tlme, a MOS FET Tg i~ ln the "o~f" state owin~ to a clock ~A The potential of a node become~ lower than that of a node ~ by the threshold vo}tage Vth~ of the MOS F~T Tl, an~ the po.entlal of a node ~ beco~es lower than that o~ the node 0 by the .hreshold voltaze ~th2 o~ the MO~ FET T2 Accordln~ly, the difference voltage o, ~5~8V

'::
both the threshold voltages Vthl and Vth2 ls the capacltance C2. Subsequently, the 1~50S ~T T8 is turned "off" by ~l and the MOS F~ Tg ls ~urned "on" by ~2. Then, ;-the dlfference ~oltage of the threshold vo].,ages ls ?rovlded 5 at the node ~ .
Figu.e 13 shows an opera~lonal ampllfier accordins to the princ~ple of thls lnvention. Tl and T2 deslgnate a differ entlal pair constltutlng a differantlal a~plifier clrcult, ~`
~ and Tl2 and Tl3 desi$nate actlYe loads of the ~iffer~ntial lO . ampllfler. A transistor Tll forms a constant-current circuit together wlth translstors T~4 a~d Tl6. Transistors Tl5 and Tl6 cons~lt~te a level ~hift output bu~fer ~ircuit whose constant-current source load is ~he transls.or ~16.
Although the example o~ a clrcult arrangement based on C-.-OS
is shown in the flgure, the circult can of course be con.~ructe~
of qlngle-channel MOS.
: In thls operatlonal ampllfler, the differential pair translstors Tl and T2 constitu~ing ~he differential ampllfler clrcuit are especlally endowed wl~h unequal threshold vol~a~es 20 Ythl and Yth2 on the basls of the Ferml level d~fference of the sate electrodes stated before, the difference of the threqhold voltages can be utillzed or derlved as a reference voltage. Thls ls an applicatlon o~ ~he operatlonal amplifier whlch has hlthert~ not been existent. ;
~l~ure 14 ~chematically deplct an ordlnary operational ampllfier by pic~ing up only the dlfferen~lal porti~n tr,ereo~.
It 1~ here assumed that MO~ transl~tors Tl and T2 have un-equal thre3hold volta3es Vthl and V~h2 respectively and t'n~
the other character~stlcs such as mut-~al conduc~a~ces are equal. Signs (-) and (~) appearln& on the inpu~ slde 1~5~880 signlfy the inverting and non-inverting inputq, respectively. ;~
Letting Vl denote an lnpu~ voltage of the translstor Tl and V2 an input volta~e of the transistor T2, ; Vl Ythl Y2 ~th2 that ls, Yl - V2 - Vthl ~ Vth2 ..................... (29 ;
The output level changes w1t~ thls inpu~ vol.a3e cond~tion as the boundary.
The operatl~nal amplifier ls endowed with an input offset correspondlng to the differe~ce vvlt2ge of the thrPs-hold voltages. Therefore, when elther o, the inYer~in~
input (-) and the non-lnvertlng lnput (+) is ground~d or connected to a reference potentlal of a power sup~ly, lt ca~
be opera~ed a~ a Yoltage comparator whose reference vol~a~e is the offset voltage. On the other hand, when the output is connected to the lnvertlng input terminal (-) to construct a voltage ~ollower clrcult and the no~-lnvertlng input ter~lnal (+) ls ~rounded as _howh ln ~lgure 14, the di~fere~ce of the threshold voltageq ls obtaln~d at the output Out. I~ this case, ln order to effect the operation of ~he operational ampllfler, the tran~lstor T2 needs ~o b~ of the depletion mode ~OS ~-~T. For example, in case of usln3 the ?~-gate MOS for Tl and the N~-gate MOS for T2, they may be made ~he de~letion type by subJectlng ~he cnannel portlons of both the MOSFETs to the lon implanta~ion under the sa~e con~i~lonsO :~
~lgure 15 shows a devlGe whlch can arbitrarily set a reference ~roltage by the ~use of the operatlonal a~pllfiP. ~n Figure 14. An output i~ ~ed bac~ ~o the l~er~i~g lnpu~
through volta~e divlder mean~ ~5 and R6. ~hus, lettl~g r -~ - 63 -. .

~S~8~

.

denot~ the voltage divl~lon ratio R6/~5+R6, the ~utput vol~age V become~:
.. V Vthl Vth2 .................. ,.... (30) r The volta~e dlvlder mea~s R5 and ~6 should deslrably be llnear re~istances, but any reslqta~ces may be adopted in~ofar as thelr cha~acterlstics are sufficlently unlform to a permisslble ~xtent.
~ereas the circults of ~gures 14 and 15 ~.remlse the use of the depletion type MOS, clrcul~s ln ~lgures 1~ and 17 are ~ade o~erable wlth enhancement type PIOS. Cf cours , the depletion ~ype MOS may well be adopted.
Li~ewise to the example of ?l~ure 14, the e3~ample of ~igure 15 dlrectly feed~ an output back to an inverting ir.?ut (~) Lettln YDD denote a supply voltage, the output VO ~;;
.; becomes: : ;
Yo ~DD ~Ythl Vth2) (31) With the circuits Or Figures 14 and 15, at least one of ~he differen~al pair tran~ ors needs to be put into the de-ZO ple~ion mode, which necessitates an increase in the number of manufacturing steps in some cases. However, they can de.ive the dlfference voltage of the thre~old ~oltages ~ with reference to the ground potential.
ConYer~ely, ~ith the c~rcults of Figures 16 and 18, tne :-reference of the difference Yoltage to be obtained ls not the grou~d:~otential. ~owe~er, the condition of the operatln~ ;
mode of the ?ET ls not lmposedO
'~hich clrcult form ls to be adopted may be declded ~y ~:
the merlt or demerit to which more.lmportance is attached.
Llkewlse to the example of Flgure 15, the example of ~5~88~

Flgure 17 f~eds an output back to an lnvertlng input (-) throu~h voltage divlder means R7 a~d R8. The output becoDes;

VO VDD Yth2 ,,,0,.O,, (32) ~lgure 18 shows a voltage detector ~lrcult whereln a reference Yoltage VR ~rom a refere~.ce vol~aGe generator devlce RVG according to th1s l~vention whlch explolts the dlfference of the threshold ~ol~ages V~h 1~ applied to one lnput of a co m ent'onal ~oltage comparator YC an~ a volta YD to be detec~ed ls applled to the other input, whereby the helght of ~he ~oltage to-be-detected V~ relatiYe to the reference vol~ag~ VR can be discriminated.
~n example ln ~lgure 19 ls a voltage detector clrcult wherein a reference voltage V~ fro~ a rererence volta_ generator devlce ~YC which utlllze~ the dlfference of thres- :
hcl~ volta3es Vth correspondlng to the ?er~ level dlff2r~r.ce of gate electrodes ln accordance with thi~ ln~entlon is applied to one lnput of a voltage comparator VC and wherein a voltage obtalned by dividlns a ~oltage to-be-detected V~ :
with voltage dl~lder means Rg and Rlo i5 applle~ to the other input. Letting r denote the voltase divislon ratlo, Vref denote the reference voltage a~d V5en5e the detec~ level:

Vsense ~ re~ (33) - 25 The detection le~el V~n~e can be arbltrarily ~et through t:~e voltage dl~l-qion ratio r.
An example in ~igur~ 20 is a ~oltage detector clr~uit whicn use the operatlo~al a~plif~er wlth the offset ~orres-ponding to the difference o~ the thre3hold volt~ses Yt~ as descrlbed wlth reference to ~igure 13 and exploits the offset voltage as a reference voltage as explaine~ pre~iously.
Rll and R12 indlcate voltage divider means as ln the exa~ple of Figure 19.
I~ the volt~ge to-be-detected YD i-~ a battery supply voltage ln the exa~ple of ~lgure 18, 19 o~ 2~, the volta~e detector clrcult can be utillzed as a battery checker in 2 ~y3tem whlch uses a battery as a power su~ly. A concrete example in which the voltage detector clr¢uit of ~lgure 2C
is applled to the battery chec~er of an electr~nic tl~eplece 0 13 ~hown ln Flgure 54, and wlll be described ln de~ail later.
_ . . ...

2~ ~ /

Figure 21 shows æno~her embodiment of an operational .
amplifier circuit whlch is construGted by conneoting in the dlfferen~ial form N-channel MOS ~E~s Ql a~d Q2 Aavln2 unequal th~eshold Yoltages Vtn on the basis of the differ-ence o~ the Fermi levels of gate ele¢trodes in accordance with this invention. MOS FETs Q3 and Q~ operate as load ~ETs of the dlfferentlal pa~r MOS ~ETs Ql and Q2' and a MOS FET Q5 operates as a constant current scurce of the differentlal pair ~tOS F~Ts Ql and Q2.
Figure 22 shows a differentlal amplifier circuit which has as its of~set voltage the dlfference of the : threshold voltages Yth of MOS transistors Ql and Q2 accordlng to this lnvention.
Figure 23 show~ the dra~n current ~ versus - gate voltage charac~eristics of the MOS translst~rs Ql and Q2 ln Flgure ~2.
In this case, the mu~ual conductances of the MOS
translstors Ql and Q2 constitutlng the dlfferential palr are deslgned so as ~o become e~ual. As the current ~, 20 of a constant-current source CS of the differential circuit changes to Io~ Iol and Io'l, their points of intersections with the Va~ - ~ S characterlstic of the translstor Ql ~ary to points 1, 1' and 1" and their points o~ lntersections wlth ~he VGS ~
: 25 characteristlcs o~ the translstor Q2 vary to points 2, 2' and 2n. At flrst, voltage~ V~l and VG2 are applled to ~he ga.tes o~ the respecti~e transistors Ql ar.d ~2 in order to bring the dl~erentlal circuit i~to ~e balanced state, Hereln, e~en when the current of ~he cons~ant-current source CS has changed ~rom Io to Iol or Iol' in ~15~L880 dependently of the temperature, the dif;Eerence o the vol-tage~ VG~ d VG2 whlch balance the differe~tial circuit are held substantlally con~tant. In actuali~y, the difference voltage reflects the difference (Vthl ~ Vth2) of ~he threshold voltages of the tra~sis~ors Ql and Q2 a~ it ls. Accordlngly, the temperature characteristic of the differenee (Vthl ~ Vth2) f the thres~old voltages of the translstors Ql and Q2 appears as it ls~ as the difference (VGl - VG2) of the voitages to be applied to the gates of the transistors Ql and Q2 in order to put these transistors lnto the balanced state.
When the P~-gate and N~-gate N-channel ~iOS ~ransistors pre~iously descrlbed.are respecti~ely use~ as the transis-tors Ql and 42~ a voltage of approximately l.l V
corresponding to the band gap ls obtalned. In the case of a sili~on semiconductor, this di~erence voltaye ha~ a temperature gradient of -0,24 mV/C.
The temperature dependency of the difference volta~e of the gate vol~ages can be nulll~ied by making ~he values of the conductance~ of '~he transist~r-~ Ql acd Q2 unequal.
It ls suppo~ed by .way o~ example that the temperature dependency of the constant-current sour~e CS of ~he differentisl circult ha3 a positive gradient, whlle the di~erence tV~hl - V~12~ o~ ~he ~hreshold voltages of the tran~istor~ Ql and 2" exhlbits a ~emperature dependenc~ o~ ~ negatlYe gradlen~. As lndlcated at Q1 and Q~" in Figure 239 the conduc~ance of a2" is ma~e ~maller than the conductance ~ Ql' whereby the gate voltage of the ~ranslstor Q2 under the balanced state i~5~88~

varies as indicated at ~, ~' and 3" in d~pendence on the temperature, and ~he temperature de~endency of the differen~e vf the gate vsltages of the tra~sistors Ql and Q2" as based on the dlfferen~e of the condu~tances of the translstors Ql and Q2" has a posltive gradient.
By properly combining the magnitudes o~ the ¢onduc~ances, ~he total temperature dependency can be made zero or can be improved substantially.
When the temperature dependency of the cons~a~t-current source of ~he differential circuit ha~
a negatlve gradlent, the conduc~nce of the tra~sistor Q2' ls made greater than the con~uctance of the tr~nsistor Ql conversely to the ~bove, whereby the temperature dependency can be lmproved to zero.
Under the balanced s~a~e, the ~ollowing relations hold among ~he current Io ~ the~constant-current source, and the threshold ~oltages Ythl and Vth2, mutual conduc-tances ~1 and ~2 and gate voltage~ VGl and Va2 of the respectl~e ~rans~tors Ql and Q2:
o ~~~~ (VGl ~ Vth~ (VG2 ~ V~h2)2 ................ ~34) YGl ~ V~hl ~ ~ 2 Io/~l ( VG2 5' V~h2 ~ ~ ,.,(36) VGl VG2 ~ (Vthl ~ V~2) + ~ ( ~ ~

-.(37) In E~ua~ion (37), when ~1 > ~2~ I < o, and ~hen ~ 2' ~ - ~ > 0. There~ore, the temperature gradient of the second term of E~uation ~7~ can bec~me ;, ~ .
9 _ ~ 88 bothi po~itive and negatlve.
~ lgures 24 and 25 show application circuits of voltage comparators ea¢h being another em~odiment ~ich can reduce the temperature dependency on the basis o~
thie concept described abo~e, In Flgure 24, ~IOS F~Ts Ql and ~2 whose threshold voltages Vth, are unequal owlng to the dlfference of the Fermi levels of gate electrodes ~n accordance ~ith th~s in~en,tlon are operated as source follo~ters, ~,e balanced state corresponds to thie time when the differe~tial input ~oltage of a ~olta~e ¢o~paraitor circuit ar opera-tional ampli~ler circuit C~l Decomes O (zero) volt.
Under ~he b~lanced state, the follo~wing rela~lans hold amonig the threshold ~oltages Y~l and Vth2, mut~lal : 15 conductances ~1 and ~2~ gate voit~ges VGl and V~2~ source voltages Yl and V2 and draln currents Il and ~ of the respective MOS ~ETs Ql and Q~:

Il 3 ~ ~31 (VG~ Vl)2 20I2 ~~ ~2 ~VG2 Yth2 ~ V2) .. ~(38) Vl ' Y2 ... (~9) Accordingly~

VGl - Vthl ~ Vl + J2 Il/~

25V~2 = Vth2 ~ V2 ~ 2 ~ 2 ,~
VGl ~G2 ~ (V~hl ~ Yth2) + ( ~1/~1 ~2 I2/~23 ~ 4~) Thus, assumin~ that I~ I, th tempera~re 3 dependency of (VGl ~ V&~) can be made zero by a?pro~riat~

;~

., ', .

1~54880 qettlng ~1 and ~2 in con~ormity wlth the temperature dependency of I a~d ~he temperature depende~cy of (V~hl -Vth2) qulte simllarly to t~e case of the differential clrcult, Further, i~ thls example of the circuit, as.sumi~g that ~ B2 ~ 13, Equation ( 42) becomes:

VGl -- VG2 a Vt;hl ~ V-th2 + ~ (~rl ~2 ~ ( 43) Thererore, even when the currents Il and I2 are set at unequal values, the tempera~ure dependen~y of ~e ce ~YGl - VG2~ can be sfmilarly ~ade 0 (zero) A~ an example of a constant-curre~t cir~uit, one as shown in Figure 26 ls considere~. Here9 when the conduc~an~es Or FETs Q2 and Q3 are m~de l : n, a current flowing ~hrough the ~ET Q~ can be made n.I relatlve to a curr~nt I ~lowing through ~ETs Ql and a2~
Accor~lngly9 Il and I2 in Equation ~43~ c~n be readily realized by changing the ratio n in the abo~e constant-current clrcuit.
Figure 27 show~ an embodiment of a speci f i¢ form oî a ref~rence voltage generat~r cir~uit based oll the differentlal circult o~ Figure 22.
Ql' Q2' Q3 and Qg enclosed wi~ dot~ed lines in ~igure 27 constl~ute a cor~st~t-~rre~t circuit similar to t~at ln Figure 26, whlle tra~s~stors Q~9 a5, Q6~ Q7 and Q3 co~stitute a dff~e~ 3tial circui-. similar to that lzl ~igure 22. ~ere, the transistor Q~; is a P*-gate ~ channel MOS transistor, and the tr~nsistor Q7 is an W~-~ate Nwchannel MOS transistor.
The arrow !cymbols of ~he gates represents the N~-gate and ~ 5~8~V

the P+-gate discrlminatingly.
me MOS transistors Q6 and ~ have the~r ~hreshold voltages shi~ted by e~ual Yalues by means of the ion `~ lmplantatlon or the ll~e, and the MOS tra~s:lstor ~ is made a depletion MOS transistor. .
, An output based on translst~rs Q8 and t~g is negati~ely ; fed back to the gate of the transistor Q5. For an output :` ~oltage, the offse~ ~oltage of the translstors Q6 and Q~ can be used as a re~erence ~oltage. Le~';i~g VO de~ote the output ~oltage and letting ~n E~uatlon ~:37) VC~l ~ Vo~ VG2 ~ , Vt;hl 5~ V~hn+,, Vth2 ~- Yth ~, 6 and ~2 ' ~7, then:

VO ~ Vthn~ ~ ~thp~ 44) 15In thls case, (Vthl - Vt~2) is the difference between the threshold ~oltages of the P~-gate ~T-ch ~ lel MOS
transls~or and ~he N~-gate N-channel MOS transistor !and become substan~ially e~ual to the band gap vol~age of l.l V~ The output voltage ~0 has ~he form in whl~h 20the correctio~ ~oltage o~ the second te~m ls added ~o ~he band gap ~oltage~ -Letting ~he mutual co~ductance of the tran$istor Ql be ~l~ and suppo~ing the drain ~ a~e of the ~ransls-tor Q2 to be substantlally e~al to ~he ~hreshold Yol~age Y~hn ~hereo~, o ~ (YDD Yth~)~VDD ~ V~hp~

~ tYDD ~ ~hp~ ~. ... (45) In a~d~t~on,.
~1 3 ~OP (~/L)l . - 72 -:1~5~880 ~ 6 = ~ON(~/L)6 ~ ~7 ,BoN(W/L)~
where ~ Bop and ~BON denote the mutual condu~tances per Wlit area o~ the N-MOS and P-~SOS transistors, respectively, 5 Accordlngly, the output Yoltage becomes:

V ~ V~ -- V~hp+ + ~ ~/~ !
r ~ - r : ~
~/(W/L),7 ~ /6 ._ _ . . .
\I~TL) 6 (W/L)?
X ~(YDD - V~) (VDD ~ Vthp) - ~(VDj~ Vt~.p) . . ,(46) Differentiating Equation (46) as to the temperature T, ` ~ ~ ~(Vt}m~ - Ythp~

(~/L)~ ~ .
L ~
)6 (~t!L~7 x ~ ~(VDD Yt~n)(VDD~ p) --~(VDD~ ~ )2 ...(47) (W/L)6 and ~W/L)7 ca~l be set so ~at; ~0 O may be held.
Figure 28 shows an embodiment o~ a reference ~roltage generator clrcuit which is based on the princlp}e const- ;
ruction of Figure 24~ A c~rcult wl~hi~ dotted li~es in Figure 28 forms the comparator circuit ~Pl ln Figure 24. :~
s~ors Rl, Q~, Q~ and Q6 c~nstitu~e a ~o~stan~
current circuit. Currents to ~low ~hr~ugh transistors Q3 and Q~ ~an also be made unequal by making the .
ratlos o~ the conductances o~ the transistors Q4 and .
- 73 - j ~15~

, .

Q6 differen~ relative ~o ~he conductance of the transistor Q2.
Here, the transistors a3 and Q5 are an N -gate N-channel ~IOS transistor and a P~ ga~e ~i-channèl MOS
translstor respectl~ely.
As in t~e ~oregoing~ the ou~put ~oltage VO is nega-tively fed ba~k to the gate of the transistor Q~ so as to form the voltage follower, and the ground po~ential ls applied to the transistor Q5.
The temperature depe~ndency o~ ~he output vol~age can be made O (2ero) by making the conduc~ances o~ the transistors Q3 and Q5 or the conductances of ~he trans~stors Q4 and Q~ u~equal in accordance with Equat~on (42) or (43), or by ~omblning Ooth ~hese measures.
By way of example, ~t is supposed that the conduc-tances of the transistors Q3 and ~5 are e~ual and ~
that the current to flow through the transistor ~1 is Iot and that the rati~ o~ the conductanoes of the transist~rs Q2 and Q4 Is I : n, while the ratio of the conduc~ances of the translstors Q2 and Q6 ls 1 : n'~ Then, the outpu~ ;
voltage VO becomes:

Vo ~ V.~;h,n+ ~ Y,t;~,lp~. +~ t~ -~) (48) By ad~ustlng the Yalues o~ n' and n~ the tempera~re ~5 dependency o~ the ou~put vol~age VO can ~e 2ade subs~tlally zero. A further circuit arrangement which general~es a refer ence voltage and which can reduce to zero or at le~ast improve the temperatuxe dependency o~ the re~erence voltage, is shown in Figure 25, i~ addition to the foregoing circuit arrangements.
: 30 This circuit is operated with the sources of transistors.
. .. . . .. .. ... ..... .. .

llS488 . Ql and ~2 gr~unde~.
.~ An example in ~igure 2~ ls a clrcuit of a constan~
current which ls determined by ~he dlfference of the threshold voltages o~ MOS FETs Tl and T2 i~ ac_ordance with this invention.
The MOS ~ETs Tl and T2 ha~e equal mutual conductances ~, and their threshold ~oltages ha~e values Vthl and Vth2 dif~erent ~rom e~ch other owlng to the di~ference of the ~erml le~els o~ gate electrodes in accordance wlth this invention. If a resistance R20 is sufficie~ly high as compared with the impedance of Tl, the drain voltage (- gate v.oltage) Vl of Tl becomes subst~tiall~
equal to Ythl.
~hen T2 is i~ the saturation region, a curren~
}5 I2 flowing through T2 is:

IOUT ~ ~~~ (Y~hl - Vth2)2 .-(49) An example in Elgure 30 is a consta~t-curren~ circui~
;~ employing ~ reference voltage generator devlce RVG which 20 generates a re~erence ~ol~ge V~ Vth L ~ Vth2) dec~ ded .; by ~he di~ference voltage of the l~reshold ~roltages i of I~OS FET~ correspor~ing to the çllfferen~e of the Fermi lev els of the gate electrodes thereof in a~cord~nce wi~ ~i.s i~rentio~,and an ord~nary cperational amplifier 25 VC. Irl ~e const~nt curre~t clrcuit, a vol~age d.r~p ` IoU~;R2~. ~ased on a current I ~lowing t~rough a ~1;0S ~ET
T22 is compared wi~ a reference voltage VRE~ " and the gate lroltage o~ Tl ~s controlled so that bsth may become eg,ua:l at all times.
3o , ~r~ - 75 -l~S~18~) IOutR21 - YF~

I VÆ ~ ...t~) Here, the re~erence voltage may ~e obta~ned by en~owing the operatio~al ampll~ler ~C with a~l o~set and groundi~g ~ e non-lnverti~g input (+~ of the opera-tional ~mpll~ler VC as in the foregolng example of ~igures

13 and 14.
An example ln ~igure 31 is a constant-currD~t circult whereln the so-called current mirror clrcuit ln ~Jhich ~ilO~ ~ransistors T~l ~nd T33 ha~e the sa~e cha...acteristics, An example i~ Figure 37 is an ap~licatiotl ~hereln a reference voltage VRE~ ~hlch is dec~ded by 1~e di~ference voltage of the threshold volta~es of ~IOS F~Ts correspondinO
to the dif~eren~e o~ the ~ermi levels o~ ~he ~ate electrodes of the MOS ~ETs ln accordance wlth t~ls invent~o~ ls explolted for R stabill2ed power sup~ly clrcu~t, A
re~erence ~oltage generator de~i~e RV& is constructed 20 by any of the above~stated seYeral me~hods according to the prin~iple o~ this l~ention. A dlvide~ ~ol~age of a stabili~ed outpu~ ow~ng to ~ol~age divlder ~eans R13 and . R14 and a reference voltage are compared~ and ~he gate ~oltage o~ a controll~g MOS FXT T20 15 co~trolled so as ~o bring them intQ agreement7 th~reby to st~bili~ the ou~put ~o}~age ~ ut- Any operatian~l ampli~ier may ~e used as lo~.g as i~s characterlstics are allowable.
I~ th~example o~ Figure 33, the ~iOS tran~lstor used for ~20 in the example of Fl~ure 32 ls replaced with a ~0 blpolar ~ranslstor TRl~

.. .. . ... . . ..

~5~8~0 An example in Flgure 34 uses ~he operational ampllfier YC as s~own ln ~he example of Figures 13 and 14, ~thlch ~as the o~fset voltage ~ased on th2 dlfference vsltage of the threshol~ ~oltages Vth of MO~ FETs and whose non-inrerting lnput (~) is grounded. T21 ~ay be a MOS tran-~istor, a bipolar transis~or or a ~unctlon field-effect transistor.
~ 1gure 35(a~ sho.~ts a voltage regulator accordlng to this i~en~lo~ h ls a fur~her im~ovement o~ '~he 1~ stablll~ed power supply circùits lllustrated in Flguu~es 32, 33 and 34, and Flgure 35~b) is a characterlstlc ~iagram thereof.
The clrcuit arrange~ent ln Flgure 35(a) has the constructlQn of a compar~ng volta~e regulator. It dl-fer~
from a con~entlonal ~oltage comparator in that ~he input character1st~cs of an operational ampllfier YC belng a . voltage comparator are asymmetric at the input terminals of an non-in~ertlng lnpu~ ~) and an inYertlng input ( ).
That is~ this ~oltage comparator does no~ bal~nce ~hen the ~oltage le~els o~ the non-ln~ertlng input ~) and the ln~ertlng lnput (-) are equal to each ~ther, and it balances whe~ a predetermlned hlgh lnput ~oltage ~in the absolute ~alue~ i~ applied on the in~er ~ g l~put (-).
In other words, ~ this voltage ~omparator, ~he i~put le~els of tha non-in~erting input ~+) and the ln~ertlng input (~) ha~e an of~set wi~h respect to ~he balanoe : poln~.
0~ ~he other hand, accord~ng to a conYentional ~ voltage regulator, in case where an lnput ~ol~age Vin ; ~0 i~ high, an output Yol~age VOu~ depends upo~ a reference .
- 77 ~

i~S~8~0 voltage Yref generated from ~he reference voltage gene-rat~r RYC and the difference of VOUt - Vin ls made large, whereas in ¢ase where the input v~lt~ge Vin is low9 VOUt depends solely upon Vi and ~he dif~erence of ¦~in ~ VOUtI ls made s~all. Accordlng to thls ln~entlon, the changlng poln~ P between both the cases is set at a polnt o~ V1n - Vl wit~ respect to the inpu~ vol~age Vln (Vl Indicates th~ lowest operating.vol~age o~ a regulator load L).
Accord~ng to the voltage regulat~r o thl5 in~en~
tlon thus ~o~structed, wAen the ~npu~ ~oltage ~ is higher than the lowest operatlng Yoltage Vl, ~he load L
is operated by t~e output voltage V0ut which ls hlgher ~han the lowest operating voltage Vl bu~ lower ~ha~ the lnput voltage Vin~ and hence, the power dlsslpatlon is reduced while ensuring proper operation. When the inpu~
~ol~age Vin is low, the load L is operated by ~he output ~oltage which ~s ~ub~tan~ially equal to the ~nput Yoltage Vin or somewhat smaller than lt, and hence, ~ voltage ~ear the lowest operating ~oltage Vl of ~he load L for the input v~ltage Vin is suppliedO Slnce ~he outpu~ ~oltage VOUt is redu¢ed to a ~oltage sui~ed to ~he load L for ~he high lnput v~ltage ~ n~ ~his voltage regula~or can endow ~he load L with a lou power d~ssipatlon a~d a wide ; 25 range of input volta~es Vi~.
Such an effect o~ thls lnvention will be des~ribe~
in de ~ 1 with reference to ~he graph of F~lre 35~b) in compariso~ with the prior-ar~ v~ltage compari~g regu-lator ha~lng no of~set.
In the figure, the abscissa represents the lnput voltage Vln,while the ordinate represen~s the output VOUt and ~he re~erence voltage Vref. 3traight line ~ ~cates VOUt equal to Vl~, in -other words, a virtual cuFve ir~ the ~ase where the load 5 L is operated directly by the inpu~ voltage V1n wit~out employing t~e voltage generator.
Curve c indlcates a reference voltage Vre~L generated from any of the re~erence voltage generator devices in various forms. Depending on the type thereof, the reference voltaqe 10 generator circui t device ~VG utilizes various parameters of semiconductor devices such as the t~reshold ~roltage V~;h of a MOS~E:T, the mu.,ual conduc~ance om, t~e forward voltage V~ or backward Zener vol~ge ~ o~ a PN-Junction~
and the curren~ gain hfe of a bipolar transistor, There-1~ fore; the reference voltage Vrefl depellds upon the supplyvoltage Vin according ~o the voltage depen~ency o ~he parameter C Vre~l 3 f (Vin)]
When the refarence vol~age Vrefl is used as ~he reference voltage of the ~ol~age oomparator circult VC and where the comparator circuit VC ls not endowed with ~he off~et as prev~ously stated, the output ~rol~age VOu~ becomes equal to t~e reference volta~e Vre~L
and agreea w~th ~e curYe ca Since the reference voltage YrefL doe~ r~ot become higher tha~ the input voltage Vin~ ~he output Yoltage V0u~ become3 lower ~han the input vol~age V~n in any range. As a result, the input voltage V~ a~ the ~me ~en the ou~pu~ voltage YO11~ be~omes equal to the lowest operating vol~age Yl of t~e load (po~nt R) becomes V2 (~2~ Yl). Accordlngly, the usable 30 range of i~put voltages Vin as vlewed from the load L

~5~8~

,; .

suffers a loss of a voltage co~ponent correspondi~g to IV2 - V1l-In order to make this loss small, ~n ~e ~ol~age regulator of Figure 355a) according to thls iavention the operation21 amplifier VC making up the ~ol~ge c~mp~ra~r balances when the inverting input (-) has become hlgher ~han the non-inverting lnput (~) by ~he off,3et v~lta~e ~VO ~, In consideration o~ the of~set ~ol~age~YOf~ o~ the operational amplifier ~C~ a referen~e voltage Yre~2 (curve d) which is smaller than the vlrtual .e~erence Yoltage Yrefl and which has a s~m11ar characteristlc is employed as an actual refere~ce voltage Vref~ The valuos of Yref2 ~d ~Voff ~re set so that a substantial co~pari-ltage tVref2 ~ ~Yoff) at an input volta~e V3 ln the normal operation may become e~.ual to the virtual re~erence voltage Vre~l, namely, ~hat it may agree wi~h a deslred operating polnt 3, Wi~h su~h a construction, the voltage comparator VC
formed into the voltage follower balances under the con~i-.~ tion of Vout ' Vref2 ~ ~Voff- S~c~ ~lput voltages Vln satlsfyl~g the balance condition are only V1n ~ Yref2 +
o~
When the input voltage Vin is smaller than (Vref2 + Q~off), the oUtput voltage VOUt also becomes smaller than it~ so that the vol~age Go.~para~or VC func-tions to raise the output voltage VOut. This ~eedbac~ controlf howQver, is limited wh~n ~le ou~put ~ol~age Vo~t has become equ 1 to the lnp~ ~oltage Vin.
Accor~lngly, with ~he lnflexlo~ point (P) at V1n - Vre~2 ~ ~Vo~f, the output voltage You~ ~s reduced ~154~

(limited) to Vref2 + ~Vof~ tcurre bl) when the lnput ~oltage Yin is hlgher than the i~flexlon poi~t P, a~d it is made substantlally equal to ~he input volt~ge V
; (curve a2) when V~ lower ~ha~ the i~flexion point.
If the ln M ex~on point P is the same as or hlgher than ~he lowest operating vol~age Vl (po~t Q) ~ith respec~ to ~he input ~oltage Y~n (on the abscissa), the foregoing loss can be avoided.
This 15 because the curve bl has a point of ~ntersec-tlon ~ith ~he stra~ght line al owing to ~Voff~
when the operational ampli~ier does not have the offset vo~tage ~lJOff and where there ls no polnt of ~nterse¢tion . w~th the straight line al as i~ the curve d, s~ch a~.
effect ls not achleved.
Although a MOS FET TC ln ~lgure 35(a) f~nctlons as a source follow~r, it ~s a depletion mode N-chan~el FET, s ~rOut 3 Vln posslble when Yin ~ Y f ~Vof~ d ~at lts threshold ~roltage Vth has no loss.
Accordingly, this is e~ective wh~n the input voltage VLn is smali~
l~is, however, does not deny the use o~ a source follower FET oî t~e enhan~ement mode. The en~ cemerlt mode FET ~ s very ef~ectiYe when the input voltage is great and th~ Y~ lo~s is not a serious probleD~ and when the adoption o a depletion mode FET manufactu~ing process ls di:f~icul~. In t~s case, cu~:~re a2 (Vou~: 3 Y~) ~,rhich d~ter~ines lower output ~ol~ges V0~ ~ ('oelo~
~e ~::hangirlg polnt P) merely sh~f~s downwards by V.~,h (VOut ~ V~n ~ V ~)" and it ls s~mllarly posslble to brlng ~0 forth the e~ect as preYiously stated on the output :

.

voltage VOUt, In the ~iguret the N-chan~el F~T can be replaced -;
wlth a P-channel FET, In this case, ~he ?-cnannel ~ET
functlons ~tA ~he source grounded, and the loss of r~h above described ls not involved.
~e~her the source groundin~ or the source ~ollower :
~s adopted as the controlllng FET does not pro~uce an ; esse~tial dlfference. Howe~er, in case of the source - grounding, no special consideration for the loss of . 10 the threshold v~ltage Vth, as is required for the depletion ! mode FET, is necessary. In case of the source followerl, when the operatio~ of the voltage comparlson r.eeds to be cycllcally sample~ (for examp~e, when the comparator 15 subJected to the clock dri~e in order to rend~er the power dis-sipatlon low), thl~ ~ET is convenient a~s lt functlon~ as a voltage fo UowerO Th~s is becau~e ~he ou~put voltage ls dete ~ ned by ~he gate voltage~ if ~he ~u-tual conductance gm f the FE~ is sufficiently hlgh~
It is also possible to use ~ ~ipolar transistor as the controll~ng transistor.
It is not neces ar~ly denied that the offset o~Off becomes a ~u~ctlon o~ the input voltage Vln. In set~ing the ln~lex~on point P, howeYer, lt ls desirable ~ha~ :~
~Vof~ i~ constan~ with respect to Vin.
I~ a refer~ce ~oltage which has a fl~cbuating ~aotor slm~lar to th~t of the loa~ L is used as the re-erence ~oltage Vref2, output voltages VOu~ correspond-lng to ~he characteristlc of ~he load L can be oD'~a~ned, whic~ ls ~lso con~enlent. I~, in that case, ~re~2 is set at the lowest vol~age at whl~h the load L can operate ~`;' .
. - ~2 -~15~88~

in advance, ~Vof can be exploLted as means o~ a cer-~ain margin.
Irhile a construction for bestowi~g +~he ofse~ ~V~
and an appl~ca~io~ clrcuit exp~oi~ ~he di~ere~ce ~f the threshold voltages o~ two MOS FETs accordlng t~ ~he princlple of ~his in~e~on to be de~cribed later, anot~er method for endowing ~he output voltage VOUt wlth the inflexion point will be e~plained here wlth reference to the circoit diagram of Fi~ure 36(a) and the g~aph of Figure 36(b).
In the followlng descriptlo~ and the gra~h of Figure 36(b), all ~he voltage values shall be absolute ~ values, ; In ~ re 3~a), Ql07 desi ~ ates a controlll~g tra~slstor which is made o~ an N-channel depletion mode ~ET N_cha~ne} ~ETs Qlol ~nd Ql02' Q104 and Ql06 oonstruct current mlrror clrcuits. A draln current approxlmately e~ual to the drain current ~f Ql03 flows through a diode-~onne~t~d P-~hannel FET Qlo~
and a diode-¢onne~ted N-channel FET Rl05- The saurce-drain voltage drops VD~.of the diod~-connecte~ P-channel ~ET Ql04 and.N-channel ~ET Ql05 become approxlma~ely equal to respective threshold volt~ges Vthp and Vthn owlng : to the high Impedance loads ~102 and Q
: 25 vltages ~thp and (Vout ~ Vthh3 are respectively applied to the non-ln~ertlng input t~) and the i~verting inpu~
(-) of an op~rational amp11~4er V~ const~uc~in~ a vo ~a~e compara'~r (cur~es d and b ih Fi~ure 36(b)~.
supposing a case where the operational amplifier vc ha~ no offset, lt balances when ~ol~h ~he ~puts of ~he ~ 83 -:115~880 non-in~erti~g lnput (~ and ~e i~lvertlng impu~ (-) are equal. Acoordlngly, th~ eq,~ ihrlum eon~it;ion is ~VO
V~ ) 3 Yt;hp~ ~;hat is~ YoU~ ~ Y~p ~ V~. The output voltage Vou1; ls limited to tV.t;hE, ~ Vt~l3) when ~ 2 Vthp 5 V~ d it becomes substa~ally equa~: ~o V~ when Vln ~, Vt;hp I V~L- Accor~ingly, ~ase whi~ra ~.e load L
15 constru~ted of a oomplemenEary MOS i~te~p~ated ~ircuit (C~IOSIC), ~e o~erating lower-llmlt ~rolt~e o~ ~he CMOS
cl.cuit usua~ly ~eoomes (Vthp + V~) arld ~he ou~ut 10 voltage Y~Ut ~an Gompensate ~r ~t.
Alt~ough the t~reshold ~roltage to be deri~red by ~e diode-coDnected ~OS Ql04 an~ Ql05 i inheren~ t~reshold Yoltage, i~ i5 n~t e~al the~reto and follows up ~e drai~ curre~3t of the circuit. Qf ¢ourse, 15 lt ~s ~av~r~ble to maie t~e outpu~ ~oltage V,D~t of the equilib~um polnt somewhat greater t~ the l~herent - (V ;hp ~ ~) . To that en~, ~e m~ltual c~nductance o~ t~e FET Ql03 mar be ma.de small in adva~ce so as t~ ~ed~lce ~he curren~ to flow t~roug~ each MOS di~de Cl}04 o~ I
20 Ql05-The approximate t~reshold ~l~age to be deri~red by ~e MO~; ~ode prem~seq t~e ~1GW 0~ the ~rai:n current.
Therefore / the clrc~ mus~ be c~n,3tructed s~ at the curre~ts mzly flow ~rough bo~ ~e di~des eYen whe~a the 25 input voltage Vi~L becomes lowO
q~he refererlce v~l~age ge~et~a~o~ deY~oe ac~:ordi~g .o this inYenti~n ca~ g@~erate t~a~ dl~re~e ~ age o~
the ~r~old voltages o~ 2'r.0S as the refereFl~e Yoltage, and can t~ere~ore be Go~str~lc~e~:.of MIS~ETs, Ac~or-lfngly, 30 it ~an be extensi~ely ul;ili~ed as various ~o;lstant-voltage '!~' -- 8~ -- , ~54880 ' sources ia~ morlolit~i~ iritegrated clrcuits for a~
electr~nlc desl~ top c~i~ulator9 ar~ electronic tlmepiece etc. made up o~ MIS~ETs. As ill~strated ~y way Or exam~
ple in ~igura 37, a lifetline detector clrc~t f~r a 5 battery can be obtsl~ed in such a way t~hat the out:put o~
the reference Yoitage generator de~rice (N~-ga~e N-channel MOS Ql' P~-gate N-channel MOS Q2~ resi~t~r P~l) as shown in the foregolr~g embodlment is applied to orle ~nput of a ~roltage co~arator ~lrcuit (7) as a re~erence ~roltage 10 and that a ~rol~age obtal~ed by d~vidlng a ba~erY ~roltage (VDD) by mea~s of di~rider reslst~rs (Rlo~ Rll) is applied to ~e ot~er i~lpUto In this case, s~ce thR battery v~ltage does no~
lower sudd~nly, it iQ de~lrable to d~iYe t2~e co~st~
15 voltage generator ciroult, ~e ~ro}tage dl~rlder clrcult and the ~oltage comparator ~ircuit wi~ clook pulse~, thereby to ach~e~re the reductio~ o~ ~urrent cons~tio~
- Likewi~e, when the constant-volta~e output is no~ re~uired at a:Ll times, t~ie consta~ olt~ge generator 20 c~r~uit may be clock~ri~er~ as ~ ed abo~e.
~ he ~lrcuit for ob~g t~e di~ferer~e ~ ~e threshold ~ltage~ o the ~IS~:Ts (Ql~ Q;~) ls ~ot restri~ted t~ ~e co~stru~ t;iOIl l~f t~e a~re em~d~ment, but ~t carl be modi~led in various ways and a~ spe~i~ic cir- ~:
25 cult arra~gement may be used~
Flgure 38 shows another embodiment in w~ioh this lnventio~ ~ applied ~o a ba~te~ ecker~, Ql9 ~2~ d Q9 co~3tltu~e a ~onstant-cu~rent 3~ Q5~ Q4' Q6 a~d Q7 const~tute a ~fferentlal 30 circuit~ QL~ and Qlo serve ~or the clock drl~re to t~e i~5~80 end of the reduction of power diss~pation.
Rl and R2 ~onstl~ute a battery voltage d~ider circu~t for set~ing thQ detection le~el of a batter~
~oltage. Gl and G2 ~unc~ion to latch an outpu~ owlng to Q8 and Qg.
Q4 and Q6 are an N+-gate P-ehannel ~I~S a~d a 2~-ga~e N-channel MOS, respectl~ely. By ~he ion impla~tation o~
equal quantitles, Q6 ls adapted to ~perate in the deple-tlon mode~
:: 10 The embod~men~ shown in ~lgure ~8 is the ba*tery checker for a tlmepiece. Nhen the dete~tion ~ level ls set ~etween 1.3 V and 1,5 V, a ~r~e~t fl~wlng ; through Q7 has a po~itive gradlent for the ~emperature, and ~he di ~ erenGe (- band gap Yol~age ~ 1.1 V) Gf ~h~ I
threshold v~ltage3 o~ Q4 and Q6 has a negatl~e gradle~t for the temperature. T.herefore9 the dimensional ratlo of t~e MOS~Ts is set so that .~he ¢o~ductan~e o~ Q~; may become smalier ~an ~e ~ond~c~ce of ~4.
Fi~e 39 shows a high-precislon reference voltage 20 generator ~lrcult of the ~roltàge î~llower ty~e utlliæing an operati~nal a~lifler, N-chan~el ~IOS F~:Ts of the P~gate a~d Nt'-gate are used` for ~4 and Q5, res~ti~ely.
~urt;her, ~e Gond~l¢~ es o~ the FE~s are ~a~e dlffer~Ilt to produce.an o;efset voltag~. By adJusting a ~esis~or 25 Rl outsida an IC, a co~tan~.:curre~t to flow thT~ough a oonstant-c ~ en~ sourc~ Q6 is ad~uste~ ~here~y to ad~us~ . :
the o~set ~oltage. Thu~, the ~ adJustm~t o~ a re~erence Yoltage ~s made pos3i~1e~
On the o~her hand, as ~ S~hmltt trfgger Gircuit compo~ed o~ MISF~T~ a ol~ouit as shown i~ ~igur~ 40(a) -~ . ~.

~-5~

which has redu~ed the number of constituent elements has been proposed by one of the inventors.
The ~ircui~ shown in Fi~ure 40~a) is such that two inverters are c~nnecte~ in cascade and that a MISFET
tT3) forming a positive feedback circuit is disposed between the input and output of the inverter on the output side. With this circuit, the width of a hysteresis curve (the difference of two logic threshold values ~TLl and VTL2) deviates on account of deviations in a supply voltage tVDD), the threshol~ voltages tVth) of i MISFE~S, etc. Therefore, when the circuit is applied to an oscillator whose output oscillates within the voltage width, the frequency deviates disadvantageously.
;~ This invention employs MISFETs formed by a method wherein the threshold volta~e ~f one ~T2) of MISFETs constituting the first~stage inverter in Figure 40(a) is made higher than that of the other MISFET having the same conductivity type channel by a voltage component based on the difference of Fermi levels. In this way, it is intended that the width of the hysteresis curve of the Schmitt trig~er circ~it tthe difference of two lo~ic threshold voltages) assumes a fixed ~oltage (a voltage substantially equal to the Fermi le~el dlferen~e3 fluctuating little against the supply voltage, the manu-acturing deviations of the MI5FETs, tem~erat~re ~hanges, etc.
In the following, this lnvention will be described , 115918~3V

in connection with a l~referred er~odiment. Referring t~ Figure .
40(a), the Schmit~ trigger clrouit is ~onstrtlcted o an in~-erter 1 to which an inpu'c signal ~ s applied, an inverter 2 which recelves an ou:tpu~ of the in~rerter 5 1 as i~s lnput and which forms a~ ~3u~:put siynal (VO) and a MISFE~ T3) whlch ls inter~o~ed betw~e~ a~ input terminal and a ground termlnal of ~e lnYerter 2 and wh ich i3 controlled ~y the output sig~al~, ('r~);
me MISFET (~3')' aæts as positi~re ~eed~ba¢lc ~eens 10 of ~e output; side lnverter 2. ~he ~perat~o~ of positively ~eeding the inpu~ sig~al o~ the lnver~er 2 t~ the output slgnal thereof ic inseparable ~rom l;he ope~a~ion of the inYerter 1 formin~ the inpu~ signal. The ci~cui t operation ~s more easily u~iderstood whe~ explal2~ed ~n 15 ~elat~n with the input side imrer:~er l, as in the followlng.
When ~e lnput; sig;nal ~V~) is at a high le~rel (ground level~, the ~utput of the ~33?ut side ln~er~er 1 ~ecomes a low leYel (-VDD) bec~use the Nchannel MISFET.(Tl) 20 is "on" and t}le P~hannel MISFET ~T23 is "o~fnO l~e N-channel MISFET ~T~) of the ~ul;}~ut sid~ i~verter 2 reoelvlng thls ou~pu~ of the ~nput s~de 1~3Yer~ter 1 tu~s "off" a~d ~he P channel ~l.IS~ET~ (T5) turas "on", so ~hat t;he output o~ the output slde in~e~ter 2 becomeg 25 the high le~rel~ tgroun~ leYe}),. For thi~ reas~r~, the P~channel MISFET ~T3). ~all~ lnto t~e tto~f" s~a~,e~
~ en, u.~der ~is condi~l~n9 the i;lpu~ ~ignal (V
inte~ids to change to th~ low level3 ~he ou~ut ~f ~e 'nverter 1 forms an output ~ignal whi~h is dep~ndent 30 upon t~e lel,rel o~ e l~pu~ ~ignAl ~V~ ) a~d wh:aeh ~ s deter-.. :

p~.

~5~88~

is , ~ .

mlned by the impedance ratlo of the ~I3F~Ts (Tl, T2), ; because the MISFET T3 is "off"~ The inpu~ level of ~he output 31de ~nverter 2 is changed from the l~w level to ~ the hlgh le~el.
; 5 Accordingl~, when the o.utpu~ of ~he outpu~ side ln~er-ter 2 is chan~ed from the hi~h level to the low level and this output signal (VO) has exceeded ~he thresh~ld Ysltage of the ~ISFET (T3), the MISFET ~T3) starts the "on" operatlon. Owlng to the ~on" operat~o~ of the MISFET (T3), the output level of the lnput side in~erter l is decided by the impedance ra~io between the MISFET
(Tl) and the parallel MlS~ETs (T2, T3), and i~ is shifted onto a higher le~el side. In other words, upon the "on" operation of the MI3~ET (T3) .which .~s controlled by the output o~ the output slde ~ert2r 2, the posi-tiYe feedback in whlch the input level of the output side inverter 2 is chan~ed ~n~o the high level side les applled to ~he input o~ ~he outpu~ ~ide ~nYertlar 2.
Then, the output ~gnal (VO) changes a~r~ptly. A~ord-~o in~ly, the logic threshold ~alue (V~L23 in Fi~re 40(b) ls determlned by ~h~ threshold Yoltages Vthl ~?~ V~h~ and mutual conductan¢es ~1 and ~2 of the MISFET~ (~rl, T2) in F1~ure 40(a). Th~t is, rDD ~ V~l ~ ~ Y~h2 ~TK2 ~ 51) :L+ ~
i ' ,~ ~1 ' .
On ~h~ o~her hand~ when the input signal ~Vi~ is ~0 at the low lerel, the ~-channel M~SFET tT1) ~f ~he in~ut :~L15~880 side inverter (1) is "o~f" and the P-¢har~e} MI3~;T (T2) is "on", t~e N-channel MISF~:~ (T4) of the outpu~ slde inverter 2 ~s "on" in the P-channel MISFE~ ~T5) is "off", and t~e P-~hannel MISFET tT3~ ls "on" owlng to the low 5 level o~ the output sighal (~0), so that the out;put s~gnal of the input side inYerter l ls determ~ned by the impedatlce ratio between the MISFET (Tl~ and the parallel MlsFETs (T2, T3)-Accor~ gly9 in t~e co~rse 1~3 whi~h t~e in~ut signal lO (Vi) ¢hange~ ~roc~ the low level to the high level, urllessthe.input signal (Yi) be¢o~e~ a leval hlgher ~ha~ the loglc tl~reshold Yoltage (V~L2) in t~e precedlng operation, the outpu~ s~gnal o~ the lnput slde in~erter 1 does not change to the low level. However~ on¢e ~hl~ output 15. (the input si~nal ror the output slde in~erter 2) has begun to change toward~ ~he low lelrel a~ to cha~ge the output o~ th~ out~u~ side inYer~er 2 onto the high le~rel slde, the lmpedance of ~e MISFET (T3) shanges to increase~ Therefore, ~e p~iti~re ~eedbacX ln wl~lch 20 the change of the ~utput ~f t~he lnput side ir~rerter 1, namelyg ~he ln~ut sigllal of` ~e ~utpu~ glcie in~er'cer 2 is promcs~ed ~s applied, and ~che output signal ~v$~ :
changes ab2vup~ly. Here, when ~e P-chaNlel ~ ET ~T2) has its gate electrode ~ormed of a semiconduc~r of 25 ~e opposi~e ~on~ti~ity type (N-t~e) to the c~ducti~lty type ~P-type~ of t~e ~ate of the con~rentlonal P~chan~el - MISFET (T3) or fo~ e~ oî arl i~trl~slc ~i ~ype) seml~o~3-ductor~ 1~ haa a t~r~shoI~ Yoitage whl~h is higher ,~,han the threshold ~olta~e VTH o~ ~he ~rdlnar~ MXSFET (T33 by a ~oltage correspond~ng to ~he dif~ere~ce o~ FerLi leYel~

~S4~8~

: ' .
e.g, to the dlf~erenee of the intri~sl~ le~el and the Fermi le~el, respect:L~ely~
Accordi~gly, the log~ ~hresh~}d r~l~age (V
- ln Fi~ure 40(b) ls approx~mately expressed as foilow3:

VDD Ythl ~ th~
TLl ~ .(52) 1 ~ 1 ,~ i ~

~2 ~ ~3 ls held by maklng ~he 3izes o~ the ~ISFET ~Tl) and ~he MISF~T (T2) e~ual. Theref~re, the dlLfe~ence (VTL2 - YTLl) of the two Iogie threshold ~alues becoQes:

,_ 1 ~2 VTL2 VT$l ~ ( th2 Vth3) o..(53) A~¢ordlngly, the difference (VTL2 - VTLl) ~S the logic threshold ~ues in Flgur~ 4Q(b) assu3es & fixed ~oltage w~leh i5 propor~lonal ~o ~he di~ere~ce (Vth~ ~
Vth3) of the thre~h~ld ~oltage~ of ~he MISFET 2 and the MI$F~T 3, that is, the difference o~ the Fermi levels of t~e gate electrodes Or these MISF~Ts 2 and 3.
An example ~or deri~ing the Yoltage ~orrespondl~g to the dl~feren~ o~ the ~erm~ levels i5 to utilize the d~ference o~ ~he threshold Yoltages ~h ~ tw~o MOSFE~s having ~emlconduc~or gate electrodes wh~ch ha~e differe~t condu~tivlt~- types a~d whi~h are ~ormed on gate g I

~o insulating fllms formed on an identl¢al seml¢onduc~or substrate by an iden~i¢al process, ~ereunder, a spe~ific . example will be explainedO
~lgure 59 pre~lously refarre~ to represents the 5 con~eptual sectiona} structure ~f the respective ~ETs, and the structure can be fabrlcated by the ~IOS manufacturl~g proces~ i~lustrated in Flgures 73ta) - 73~ ereunder, îcr the sake o~ brevity~ the MOS tra~slstor whose gate electrode ls made of a P~type semicond~ or shall be c~lled ~he "?~ ga~e ~OS", and the MOS transist,~r whose gate electrode ls made o~ an N+-type seml¢o~u¢tor shall be called the "N+ gate MOS".

~he difference (~thP~ ~ VthN~) of the threshold YoltageS 9f the P~ gate MOS and the N+ gate t~OS ~e¢omes the dtfference o ~he ~erml potentials of seml¢~nductors maklng the gate electrode~ a~ seen fro~ E~uatlo~ ~16~.
Whlle the abov~ descrlption has been made by ~aXing the P~-channel ~OS tran~i3kor as a~ examplr, ~ulte ~he same applle~ ~o the ~ase of the N~-chaNnel t~i~S transl~tor.
Besides, qu~te ~he same a~plies to the i-type gate MOS
whose gate elec~rode ~ mad~ o~ an lntri~s~ seml~onductor, ~ lgure 41 shows a Schmltt tr~gger c~rcult according to another embodlme~t o~ thl8 in~e~tlon. The pv1~t of dlffere~ce from t~e embodlme~ of Figure 40(A) 1~ that an input ln~erter 11 includes a P+-gate P-channel depletion type MOS tra~slstor Tll ~or a load, a P~-gate P~channel enhancement type ~SOS transist~r T12 ~or ~rl~e and an N~-gate P-~hannel enhancement ~ype ~OS tra~ istor T13 ~or feedbacX, and that an output i~erter ~2 1~G1UdeS
a P -gate P-channel depletio~ type MOS trans~stor T14 for a load and a P~-gate P-cha2~el er~ancemerl~ type MOS trarlsis-tor T15 for drlve. It is lden~l~al that t~e dl.fference of loglc ~reshold tralue~ becomes a co23sta~t vol~ge propor-tlonal to the difference of the ~erml levels of the gate elec~rode~ o~ the MIS~ET 12 and MISF~T 13.
Now, an oscillator will be des¢rlbe~ as &n example of appllcation of the Schmi~t ~rigger clrcuit ~f in~rention.
~ gure 42 is a clrcuit diagFam of an ~scillator ~o which the Schmlt~ tri~ger clrcuit of thls in~entlon is applled. A part enclosed wi~h dotte~ lines i~ Flgure 4 is the 3chmitt trigger clrcui~. ~n out~p~t o~ the S~ t trlgger clr¢uit tSTC.) becomes an input of an i~verter 3 , an output Q~ whlch becomes an i~put o~ ~he Schmitt trlgger ~ir~uit (STC).
Upo2l closure of a supply Yoltagef the level of a point (d) proceeds towards the le~rel (-V~D) gradui~lly.
When lt h8s exceeded the threshold ~roltage ~VT~,2) of ~e Schmitt trtgger ~lrcuit (STC~ 9 t~e pote~tial ~f a point 20 (f) changes ~o ~e ground ~r~ltage, ar~d the p~tential of a point (g) changes to the suppl~ t~oltages (-YDD). men, as ~e point tg) is ~he lr~put o~ ~e intrerter (3), a MISFET (T4) turrls '10n" 9 arld tl~e potentlal of t~e point (d) prsceeds towards t~e ground lrol~age immedl.ately~
25 When the le~el o~ the po~nt (d) ha~ beoome below the logic t~reshold troltage ~Y~ ) of ~he Sohmitt trigger ci~rcult (STC~ e potentlal of the point (i~) char~ges 40 ~e ground voltage~ and the ~roltage of the pofnt ~g) cha~ges to the supply voltage (-~DD). Ihere~crej, the MlS~:T (T4) 30 oî the succeeding inYerter (3) t~r~3s l'~ffll, and the : i~5~88~

le~el of the polnt (d) is charged accordlng to a time constant CR which is de~ermi~ed by a resisto~ (R) and a capacitor (C) c~nne¢ted to the ~olnt (d). When the potential of the polnt ~d) gradually approaches the supply ~ltage (-YDD) a~d has ex~eeded ~he threshold voltage (VTL2) of ~he Schmltt trlgger clrcuit (STC), the pote~tial of the point (f) changes to the ~r~und potential, and the potentlal of the point (g) changes to the supp~y Yoltage (-~D~). T~erea~ter, ~he in~e~sioF.s are similah-ly repeated to cause osclllatioa~ Sin~e the po~ential of the point (d) reclprocates between the ~o loglc ~hreshold Yoltages (~TLl~ VTL2) o~ the Schm~t ~rigger clrcult (STC), the oscillatio~ ~requeacy of the oscillator ls determined by the speed at whlch ~harges are stored into or dlscharged from the capacitor tc) by ~he resi~tor (R) or ~he MIS~ET
,- (T4). Assuming now that the resistance (R) is ~ ~lclently greater ~ha~ the i~pedan~ o~ the MISFET (~4), the oscil-lation frequency o~ ~he oscillator cir~uit is ~e~ermined by only ~ and C5 and the os~illatl~n of a ~req~ency whlch - 20 is s~able agai~st fluc~uations in the supply v~ltage, temperature changes, manufactur1~g de~iatio~s, et~, When the reststor (~) is moun~ed outslde the in~e-grated circuit, only one ~in suffl¢e~ ~or the in~rated circuit o~ the osclllator clr~ul~, a~d the stable oscll-lation ~s reallzable under suc~ a condltlo~.
The resistor tR) may be ~ny of a di~usion reslstor, a resistor ow~ng to a MISFET, ~tc~ Howe~er, when a resistor of su~iclently small deviatio~ ls formed i~ an integrated circuit, the oscillator clr¢uit ca~ b~ enti~el~
contalned thereln.

.

~ igure 43 ls a ~lrcuit dlagram showlng an example of an ~sclllator cir~ul~ u~i}lzl~g ~he Sc~mltt trigger circul~ (5TC) as shown in ~igure 41 1~ which ~he wldth o~ hysteresls ls cons~ant acGor~lng to this in~e~tion.
A thlrd inverter 3 is conne~ted to the input o~ the Schmltt trigger clrcult tSTC), a ~urth inverter 4 ls connected to the output of ~he ~¢hmltt t~igger ci~cuit (STC),. and a resist~r ~R) and a couplin,g capacltor (C) for determinlng the osclliatlon ~re~ueney ~re con~ected to the l~put o~ t~e third lnverter 3.
Con~rol of m reshold Yolta~e ~ ~-The threshold ~oltage~ (~th) ~ MOliFETs being discr~te elements in a MOS integrated Glr~ult lorm an important parameter whlch determ~nes ~he characte~lstlcs 15 of the LSI. Th~ ~reshold ~oltage. V't;h l~dergoes a great de~riatlon due to Ehe marlu~ac~ring p~ces~ d a great change depe~ing upo~ the tem~e~ature, and tlle control of V.~;~ ls a d~fflcult~r ~n the ma~ufa~ture of the MOS LSI.
I~ th13 ~;nYention, as shown by way oî example in 20 Figure 50, a bla~ volta~e VBB is applied ~ a silicon substrate of a MOS memory IC ~o reduce ~srasiti~ capaci-tan~e~. In order to obta~n ~e blas ~roltage VBB, a substrate bia~ generator c~rcuit S~GC i~ employed. The substrate bia~ generator ~lrc~i* SBGC has an arrangement 25 whlch is lllustrated 1~ ~igure 4~.
In this lIIvention ~ ffle ~mpara~or employlng t~e difference ~ the work fun~ti~ns ~ the gate ele~trodes of MIS FET~ as pre~iously s~ated ls used ln th~ s~bstrate bias ge~erator circult SBGC so as to co~trol V~h lnto a constant ~ol~age, ,~, , . .
_ 95 _ - , . . . ,, ~ ;

~5~88~

Vth c~ange~ in dependence on the substrate blas VB~, an~ ls expres~e~ by the foll~wing equation:
Vt~ a VthO ~ X (2 0F ~ ¦ VBB I ~i~
where V~ho de~otes Vth whe~ the substrate ~t~s ~oItage VBB - O V, K denotes the substrate effe~ c~nstant, and 0 denotes the ~erml level. Therefore~ Vth ls con~rollable by varylng the substrate blas VBB, ~ substra~e bias Yoltage generati~g circult SBGC sh~wn i~ Figure 47 has a V~h sense por~ion 471, a comparatsr 472, an 05 lation cir~ult 47~ and a waveform sha~ing p~rti~n 47~
The oscillation clr¢uit portlon 473 may be replaced with ~ ~-~nother osclllati~n clrcu~t~ T~e wa~el~rm shaplng portion 474 is com~osed of two MOS ~iodes Ql and Q2 and a capa-citor C~, and it functl~ns to drawlng out charges o~ VB~ :
to the ear~h polnt by a pumpi~g a~tion, Owing to the pumplng action9 VBB ls draw~ towards a negati~e voltage.
ge VBBM of I~BI is deter~ined by a point at which the drawing-out ~oltage owlng ~o the pumplng act io~ and ~he sub a~e le~kage current are stabilized.
~o As long as the oscillatlon c~rcui~ ls opera~ng, VBB is held at the stable polnt VBBM. A~ter s~op of the oscil-la~io~ howeYer, ~h~ charges of the substrate leaks due ~o the substrate lea~age ~urrent a~d ~BB approa~h~s the ground level. When VBB has become close to the ground level, Vth lowersO.
The c~mpara~or portlon 4?2 in Figure 47 exploits the differ~nc~ of ~he F~rml lerels ~ ~he ~ate electrodes5 and an example ~n t~e N-channel proc~s~ is shot~
~igure 21, The comparator portion 472 employs an i~rlnsic sllicon gate MOS as ~ in Figure 21~ and an N

~15~8~

gate MOS as Q2. These are depletion type MOS. Therefore, this comparator efrects ~he i~ersion when a ~oltage of = 0.55 V has been pu~ i~to an lr,verting lnput (-~.
The Vth se~se p~rtlon 471 in Figure 47 is c~mpo~led o~ a reslstan~e and ~ dlode-c~nnected MOSFET Q3. ~ere, the reslstance may ~e either a polyory~talllne s~ n d~fused layer resistance or a MOS reslstan~e, and the resistance value 1Q se~ so tha~ an outpu~ may be~Qme 0,5~ ~ when V~h oX Q3 ha.~ become 0,55 V. Now9 when the su~strate bias voltage VBB ls close to the grou~d level an~ Vth of ~3 is below 0.55 V, the (-) ln~ut voi~age o~ the compara~or portion becomes below 0.55 V, ~he Ouqput of the comparator becomes "1" and the oscilla~lon clr^ult ~onti~ues to operate. )~hen the subs~rate blas vol~age ~BB approaches VBBM and Vth rises and exceeds 0.5~ V, ~he comparator output becomes ~rOrlJ the os~illation ceases and t~e s~bstrate blas ~oltage VB~ becomes close to the ground le~el due to the leakage. That is, since a feedbacX l~op is formed, V~h ls contr~lled to the s~able point by this substra~e bia~ generator ciroult SBGC. m e voltage O.55 Y obtalned in the comparator portlo~ 472 is l/2 of the energy gap, wh~ch changes little against temperature chan&es~ manufac-turing dlspersio~s an~ sup~ly ~ol~age fluctuati~s, Therefore, i~ be~omes posslble to control V~h at a ~ery hlg~ preclsion, and a MOSLS} wh~h is wide in ~he tempera~ -ture margin, the manu~a~tur~ng proces3 margln ~nd the power supply margin is ob~a~ed. ~s w~ll be s~ated later, also in point o~ the process~ the intrin~ic s~llcon gate MOS Ql ~ ~h~ comparator portlon 472 ~an be obtained.
by qulte an ldentic~l process to that ~or ob~ainlng a ~5~880 high resistance load ~ in a memory cell shown i~:Figure 51, so ~hat the control of V~h ca~ be readily realized wi~h the prior-art process, Level Shift ~ir¢ul~
S I~ cas@ w~ere a 5 V power supply i~ empl~ye~ as a power sou~¢e in a M~SLSI ~nd wher~ S~gI3al3 fro~ a TTL
loglc ¢lr¢ult are employe~ as lnpùts, the outpu~s of the TTL logi¢ cir¢ult become 2.0 V as a ~igh level an~ ~.8 V
as a low le~el. In ¢onverti~g the TTL sig~als i~o the ~OS
levels, lt has heretofore been carrled out to take ~Lhe ratios of inver~ers in an input port~on an~ tQ ¢G~Y~rt them l~to the MOS leYels. However, the~ e has bee~ the pr~blem that the inpu~ le~el margin becomes s~All o~ aecoun~ of the dlspersio~ of Vth and temperature ¢hanges.
Figure 45 show~ a TTL - ~ MOS slg~al lbvel converter clrcult whloh employs the refere~ce voltage Yref generated from the reXere~ce ~oltage generator cir~ult utllizl~g the dl~erence oi the Fermi le~els of ~he gate e}ectrodes as pre~lously deqcrlbed~ The signal le~el co~lYerter clrcult in Figure 45 is pref~rably applie~ to ~he address buf~er clrcults XAB and ~AB o~ ~he M9S memo~y ~howa in Figure 50. A~ the re~.e~e~ce vvltage ~ref~ ~he reference vol~age of 1,4 V i~ generated by the ~o~ego~ng reference voltaee generator cir~uit of ~igure 15. A dlf~ere~tial ampllfier employing MOSFETs in F~gure 44 is e~ployed as an amplifler (~P) ln Flgure 45, ~nd an input bufler in whlch the loglc ~ eshold vol~age of ~ ~p~t i~ 1,4 Y
equal to '~he reference Y~ltage Vre~ 1~ prepared. Wl~h the present method, the TTL-~ MOS signal le~el co~Yerter clrcult is obtained.

: - 98 -1~5~880 : Alternati~ely, a signal level converter ci~cuit ~hich has the l~gic threshold voltage ~f 1.4 V can be obtalned by ~mploying the c~r¢u~t sh~ igu~e 13 a3 the a~pli~ier (A~? in Figur~ 45. The l.~phase input (+) ~ is grounded as shown in Figu~e 14, and an address slgnal Ao - A4 ls applled to the antiphase l~put (-).
As the translstors Tl a~d T~ depletion type MOS FETs are used, By making the threshold ~olt,~ges ~t~l an~
V~h2 of the respectlve F~Ts unequal, thle operational.
10 amplifier is e~dowed with an lnput offs~ Yoltage of 1.4 V.
Lo~ic Threshold Sta~illzlng Circuit A cl~lt in Figure 46 intends to al~ays ho d the logic threshold Yoltages of loglcal circuits such a~
in~erter c~nstant agalnst ~hanges ln the servl~e supply 15 voltage, the t~reshold voltages ~f ~IOS trar~slstors, tem-perat;ures~ eto.
An lnverter 1 composed f Q2 and Q3 and an inverter 2 co~posed of ~5 a~d ~6 are e~pe~lally provided wl~h ~IOS
FETs Ql and Q4 for controll~ng l~gl~ thresholds, respec-- 20 ti~ely.
A logic threshold dete¢tor ~ir~uit 3 ~hi¢~ is composed of a controlllng MOSFET Q7 and a~ ln~erter (Q~, Qg) wl~h it~ input and output couple~ is constructed ~o as to be ~imllar ~o the inYerter3 1 and 2 s~ated abo~e ~he pattern size ratlos of MOSFETs are e~ual)~ ~lng to the coupli~g of ~he lnput and outpu~ of ~he i.~erter (Q8~ Q9)~
~ust ~he logic threshold ~o~age ls obtai~e~.
C~ dicates the oo~parator circ-~ ~ prev~usly ~ated with re~erence to Flgures13 and 14 which has the reference ~lta~e Vref as ~he of,set o~ the differe~tial _ 9~

~15~88~

clrcuit~ T~e comparator circuit CMPl compares the logic threshold and the reference ~oltage possessed therein, and controls the g te ~oltage of the con.trolling MOSFET
Q7 so that the dlf~eren~e of both the voltages may be¢ome substantially O (zero).
More speclfically, i~ the logic ~hreshold ~ the re~eren~e ~oltage (Vre~3, the outp~t ~f CMPl becomes a high level, and ~he e~ul~aient resls~ance of Q7 increases and this t~ansistor functlons ln the directlon ~f iowerlng the log1c ~hreshold. I~ case where the 1061C ~hresh~ld < t~e reference voltage tVref),- the ¢onYerse ls true~
Both ~he ~oltages fall into t~e e~ullibrlum state when they are equal.
The ga~e voltage~ of the controlll~g ~;OSF~Ts Ql and Q4 arç ~ommoa with the gate Yoltage of the oontrolling MOSF~T ~9 a~d ~he former translstors and the latter translstor are ln the slmllar rel~ti~nshlp. Th~s, the loglc ~hresholds o~ the inYerters 1 and 2 beco~e equal to the referen~e voltage, and ~ery stabl~ erter chara~
teristlc~ are exhlbl~ed.
As state~ at the beglnnlng, thls is ~ot restrlcted o~ly to ~he in~erter~, but ls slmilarly applicable to the other logical ~irGult~ su~h as ~N~ and NOR.
This is readily applicable to the ca~ of i~verters ; 25 and the like logical clrcu~t~ of or ~ single-channel types, no~ ~he CMOS construction.
i These cirGults are useful as input ln~erface clrcu~ts wh~ch can dlg~tally proces~ slgnals rellably especially when the ranges o~ input le~els and logic ampli-tudes are narrowO
- loo l~S~O

There w~ll now be explained specl~$~ examples in which the reference voltage generator me~ns accordi~g to this invention is applled to a s~atus setting ~¢ult (an auto-clear eircuit~ for electronle de~i¢es~
~lgure 48 ls a circuit dlagram sh~wi~g an example of a status setting circuit, whlch is a ~lip-fi~p clrcult constructed of two in~erters ea~h inclu~ing tWG MQSFETs.
Referring to ~he figuret ln case where potentlals at points a and b are O ~zero), ~oth ~he MOSFE~s Tl and T3 falls into the "ON" state upon closure of a power supply (-VDD) ~ecause they are N-channel MOSFETs. 31multaneously wlth the closure of the supply voltage, the pol~s a and b change towards the supply ~oltage ~-VDD). A~ thls time, the Fermi le~els of the gate semiconductors of the N-channel MOSFETs Tl a~d T3 dlf~er from each o~her, and the threshold ~ol~age Y~h3 of the MOS~FET T3 ls abou~ three tlme~ greater than that Vthl of the MOSFET Tl (example:
Vthl 8 0-45 V, Vth3 ~ 5 Y). Therefore~ h~ course o~ the fall of the supply ~ol~age the ~IOSF~T T3 t~rns ~OFF" previously. Since the MOSFET Tl Go~tln~es to be in the "ON" s~ate, ~he points b and a are respectiYely stabi- :
llzed at ~V~D and ~he gr~und p~tential~
In ca~e where, wi~h ~he power supply ( ~DD) disconnec-tedl the polnt a i3 at O V and charg2~ remal~ at about 1 at thQ point b, T3 ~s in the ~OFF" s~ate tlll VDD ~ Vth3 in the course of the f~ll of ~he supply ~oltage, and the MOSFET Tl falls ~nto ~he "ON'I state at ~D - Vthl.
Therefore, even when the point a ha~ been O ~ and the point b ha~ been about 1 Y (or up to VthN of T3~ ~ the lnltial sta~e, the point b become~ VDD and ~he poi~t a ~S488V

becomes O V ln the stable state. Further, slnce all the FETs are constructed of E(enhanoement)-~lOSFETs in the present circuit~ the current c~nsumption i~ ~he stable - state is almost zero.
Figure 49 is a clrcuit diagra~ whloh shows an example of a statuq setting circuit having heretofore been proposed. Re~erring to the figure, the threshol~ vol~age Y~h of MOSFETs T2 and T4 are equal to each other, and an N-channel D (deple~ion)-MOSFET Tl ls lnserted in order to increase ~he stability o~ a latch ~ircultO Owlng to ~he D-~IOSFE~, upon closure of the power supply (-VDD), : the point a falls simultaneou~ly with ~he power supply without fail, and the polnt b does not turn "ON~ unless the supply voltage falls to Vth of the MOSF~T T4, so that the polnt a and ~he polnt b be~ome -VDD and O ~ 1~ the stable state respectively, S~.nce, however, the r-MOSFÆT ls inserted between the poi~t a and -VDD ln ~he presen~ clr-cult, the P-MOSFET T3 turn~ "ON" when the state in whlch the point b ls -YDD and the poin~ a ls O ~ (~æS~T) is sub-sequen~ly established ~rom some reaso~, and a D~C. path due to Tl and T3 arises to result ln a hi~h current co~sumption, In contrast, wi~h the statu3 setti~g clrcult of ~hls in~ention a~ shown ~n Figure 48, the s~atu5 : sstting can be reliably done and the ~urrent con3umption is Yery low as de~cr~bed abo~e, a~d hence9 effective ~ status settlng means ~an be provided~
Now, an embodlment in whlch this inve~ivn ls a~plied `~
to a ~emico~ductor random ac¢ess memory (R~l) wlll be described.
~o In general, ln a ~orage device construc~ed o~
`'- .

,, .

~15~880 a stat~c RAM, the trol~age control of lo~ering a supply voltage is carried out ln order to reduce power dlssipa-tion at the t~me when ~he storage devlce 15 n~t used (stand-b~t status)O This is called the data rets~tion ~ode.
In ~hls case, a signal voltage is lowered ~im~ltane-ously wlth the supply ~ol~age. I~ this regard, ~ince a power supply llne has a greater ~ime co:nstant than a signal line, the sig~al vol~age lowers to a predetermined ~alue fas~er. Usu~l~y, in a seml~ondu~r RAM, a read control sign~l is set at a supply vol~age le~el, a wrlte control slgnal at a reerence ~ol~age le~el, and a chlp selec~ slgnal at a re~erenc~ potentlal le~el, In the data retentlon ~ode, ~eref~re, ~he level of ' the control si~nal lowers ~aster t~an t~e supply ~olt~ge, so that the read control slgnsl becomes the write control signal le~el lnstantaneously and that the chlp select sl~nal ls formed, For thl~ reason, the write operation ls effected instantaneously, and the information of a blt sele~ted at ~hat time ~s destroyed.
In order to sol~e this problem~ in a ~AM ~on~tructed of field-ef~ect transist~rs of a slngle channel, lt is considered to dispose a time constænt ~lrcult for maki~g the time con~tant o~ the slgnal llne greater, '~llth ~hls measure, howe~er, an external clr~it ls re~u~xed, a~d the control sl~nals are ad~ersely affected.
In a ~-MOS (complementary ~S~S) integrate~ circult?
a p-n-p-n ~lement i~ prone to be fo~med on a~¢o~n~ of the structure tbereof. Therefore, ~rhen t~e si~nal vol~age ls made hlg~er than the supply voltage~ s~ch a p-n-p-n 3~ element operates~ and a greatlcurrent flows between 10~ -~ 880 the supply ~oltage and the reSerence pote~tlal. ~or this reason, a time constant cir~ui~ wlth whi¢h ~he signal vol~age and the supply voitage lower at the same time must be selected for ~he C-MOS me~ory.
These ~ac~s are serioug pro~lems ~ the deslg~ and manufac~ure of storage deYioes o~ ~he side o the user of memory chlps.
In ~hls regard, it ls desirable that a clrcuit for sensing the lowerlng of the supply voltage is co~tained in ~he same chlp as that of the R~l. Howe~er, MOSFETs on the semlconductor chip have the temperature depen~ency o~ threshold ~oltages Vth, manufacturing de~iatlo~s, etc.
and lt has been dlfficult to obtain a detectio~ wltaga necessary for the sensin~ at high precision.
Hereunder, thls inYentlon will be concretely desorlbed ~long an embodlment.
Figure 52 ls a block dlagram of a static type seml-conductor memory integrated circult device showlng an embodiment of thls ln~ntlon.
In the flgure~ 1 designates a memory matrix (64 x 64 bits) clrcuit which ~s cons~ructed of static ~emory c-ells.
2 designates an X-decoder ~ircuit. It discerns an lnformation patter~ asslgned by a row select ~ignal (Ao - ~4) and applled through a ~uffer ~lrcult B:{l to assign a row-(X3 llne of 1/64.
3 indicates a Y-decoder and input/output ~ircui~ :
Thl~ clrcult 3 discerns an in~orma~ion patter~ assigned by a column select slgnal (A5 ~ ) and 8ppl~ ed ~hrough a buffer circuit BY, ~o assign a ~olumn (Y) line o~ 1/64.

llS~8~

It al~o gives ~he assigned column llne of the ~emory matrix an input data appl1ed through gates '~. It also provides an outpu~ data ~rom the assigned column line ~o ter~'nals (1/01 - 1/04) ~hrough gates ~B.
4 indi~ates an input da~a ~ontrol circuit, which gives ~he input/output circult the input da~a ~o-be-written, (1/01 - 1/04) indicate input/~utput t~rmlnals, (~) denotes a chp select slgnal, which i~di~ates the selection of this chlp by the "0" level i.e. reference 1~ potentlal level.
(W~) denotes a write/read control signal. It si~nifies the wr~te operatlon whe~ lt is at the "0" level l.e. t~e reference potential level, while it si~ni~les the read .~ ' operation when it is at the "1" level l,e. ~upp}y vol~age level.
.~ 5,6 designate gate circuits which are alternately controlled by the control slgnals, That ls, onl~J when (~) is "0", the gate circults are controlled by either "0" or "1" of (W~), to execu~e ; 20 the write or read operation.
7 designates a voltage detector ci~cuit. It detects the data retentlon mode on the basis of the ~act .

that the supply voltage has beco~e below a predetermlned voltage, and lt controls the gate cir~uit 5 so as ~o 25 inhibl t the (W~) at; I;hat tlme . Thus, the ~alfunctlon as presrlously described i5 pre~elited., An example ~f the concrete arrangement of the vol tage deteGtor clrcuit 7 is sho~n in ~igure 53 ~a) .
Resistors ~Rl, ~2~ conneeted in serles c~nst~.tute 3O a c~rcuit for dividlng a supply Yoltage (Y~c)~ The Yoltage ~ 1~5~88-~

divider circuit applies a divided voltage (a) to the gate of an N~channei MISFET tQ2). The supply voltage (VCC) ls applied ~ the gate of an ~I-channel MISFET (~4).
A MISFET (Q5) has its gate supplied wi~h ~ suitable blas Yoltage from (d), and co~structs a constant-current source. It constitutes an operational ampl' fier, together wlth load MISFETs (Ql) and (Q3) and the two differen~ial inpu~ MISF~Ts ~Q2) an~ (Q4).
The d~f.~erenti~ lnput ~IISFETs (Q~) asld (~4) are 10 ~rmed on, for example, ~J-ty~e silicon laye-s of equal conducti~ities, and t.~e respecti~e gate e}ectrodes are made of different materials so that the threshold volea~es may become unequal. The gate electrodes of the two klISFETs (Q2) and (Q4) are made of, for exa~ple, sillcon, and their conductlvity ~ypes are made diff erent, The ~IISFET (Q2) has the N-type ~ilic~n gate, whereas the ~SF~T (Q4) has the P-type sllicon æate. As a result~
the threshold ~oltage (Vth4) of the MISFET (Q4) becomes greater than the threshold voltage (Vth2) of the MIS~ET
(Q2) by the d~fference of the ~ermi levels of the P-type and ~I~type sillcon gates, Accord~ngly, ~he opera~lonal amplifier has a~ of~set voltage e~u~l t8 ~he difference ~f the threshoid vol~age~, Under the s~ate under whlch the supply voltage Vcc ls comparatlvely great in ~he ~irCui~ of Figure ~3(a), ~he k~SFET (Q4) ls ~ the "on" state and ~Q2) is i~ ~he "off" sta~e, ar.~ the pote~tial o~ a polnt c 1s at ~he low ~evel. Due to the lowering of ~he supply ~rolta2e VcC. the potentlal of the point ta) ~hanges as indlcated by a curve a in Figure 5~(b). '~hen, due to ~he lowering ..,,; ,..
~ lOG -. . ~ :

~ 80 of the supply ~oltage Vcc, the potential ~ifference between the supply voltage Vcc and the potentlal of the point a has become smaller than the offset voltage, the MISFET (Q4) falls into the "off" state an~ (Q~) ~alls into the "on'l state. In ~onseque~e, the potentlals of the points D and c ~n the clrcuit o~ Fi~ure 53(a) change as indica~ed by curves b a~d c in ~igure 53(b), respectively. That is, the potential of ~he point c becomes the hlgh level when the supply vol~age Vcc has lowered to a predetermlned ~alue.
As described above, the detection le~el of t~.e clrcuit of Figure 53(a) is de~ermined ~y ~he offset voltage o~ting to the MISFETs (Q23 and (;~4~ and the divided voltage owlng to the resistors ~1 and R2. I~ is ~ot affected by the threshold voltages o~ ~he respe~ti~e MISFETs.
The of~set voltage ls at a comparatlvely hlgh preci-sion because it ls declded by the dl~ference of the Ferml levels of the gate electrodes o~ the two MISFETs (Q2) and (Q4) as stated previou~ly~ Since, ln a semiconductor integrated clrcult, the relative values of the resis~ces of reslstor elements are a~ a comparatively hlgh precision, ~he volta&e dlvlslon ratlo owing to ~he reslstors (Rl) and (R2) is at a comparatlYely high precision.
As a result, the detection level o~ t~e ~lrcult of Figure 53(a) can be set comparati~ely accuratel;~
In Fl~ure 53(b), a wa~eform (d') indicates the outpu~ of ~he gàte cireuit (5) during the data rete~tion m~de during whlch the gate circ~t ~5) is not co~trolled 3~ by the detectio~ out~ut.

~ 107 -In the data retention mode, the ~nput control slgnals (~) and (~E) lower faster than the supply voltage (~cc) of the gate circult (5). There~sre, when the dlf~erence of both the vol~ages ~as bec~me aboYe the log~c threshold, the output wavef~rm (dt) as stated above is generated.
Thls forms the cause o~ the malfun~lon explained be~ore.
According to the circuit of.the ~rese~t embodiment, however, the control -~ignal (c) ls applied to the input o~ the gate circuit (5) 9 SO tnat ~he waveform (d') is lnhiblted ~rom being proYided~ Thus, the erroneous w~ite ln the data retention mode can be preven~ed, and data stored in the Qatrix memory ~re no~ destroyed.
In accordance with the embodiment se~ forth abo~e, the erroneous write ln the data retention mode can be perfectly prevented. Moreover, the detector clrcult oa~
be construc~e~ wl~h the simple clrcult arranger~ent and can be co~talned in the memory chip. It is there~or2 : unnecessary ~o care for ~he preventlon of malf~ctions on the slde of the user of the semlconductor memory de~lce.
~ar example, ~he gate circul~ which is controlled by the voltage detection output may obtaln the chlp select signal. All the memory cell select signals may be lnhlbi~ed so as to select no mem~ry cell.
~hi ls because the erro~eous write can be pre~ented when one o~ condltions necessary for the executio~ of the write opera~lon is inhibi~ed.
m e ~oltage dl~ider clrcuit whlch constitutes the ~roltage detector clrcult ln the pre~ious embo~lment may ut,ilize reslstance by means of MISF~:Ts instead o.
~0 the resistor elemen~s. Desirably, the resistance o~ thls - 1~8 -8~0 ,, ~oltage di~ider circult is made a large value in order to make the power disslpation low, The tw~ MISFETs of the foregolng embodi~e~t which have silicon gate electrodes of conductivlty types opposite to each o~her are fabrica~ed wlth~n a sil~con monoli~hic semlconductor integrated circuit ¢hlp. 5ince these FETs are manufa¢:tured under subs~antlally the same condltions except the condu¢~iv~ty types o~ ~he ga~e ~:
electrodes, the dif~erence of the threshold vol~ages Y~
of both the FETs becomes approxlmately equal to the dif-ference of the Fermi levels of P-type silicon and N-type sillco~, The P-type and ~-type ga~e electroAes are doped with respective impurities to the ~lci~itles of the sa~ura-tlon dens~ties, and the difference becomes appro~lmately equal to ~he energy gap Eg of sllicon (abou*:l.l V), whlch is u*illzed as a re~erence vol~age source~
The reference voltage generator device based on such a constructlon is low i~ the temperature dependency and sm~ll in the manufacturing devlatlons.
m e voltage de~ector circuit 7 can be modi~ied variously, That is, the reference voltage so~rces whiah exploit the difference of the ~ermi levels of semico~duators ~orming ~he gate elec~rodes of two MOS FETs as show~ ln ~lgure 6tb~, Figure 8, Figure 9p Figure lO~a~, ~lgure ll(a), Flgure 1~, Figure 13, Figure 14, ~igure 15, Flgure 16 and F'gure 17 are effectiv~ as the reference ~oltage source ~or the ~oltage de~ector cir~ult of ~hl5 i~entlon.
To ~hl~ end, ~here can be emplo~ed two FETs whlch have semiconductor gate electrodes of dl~e:rent conductivity - ' 109 -~ : :

` ~S~8~0 types as already explained with re~erence ~o Figure 59, for examp}e, a MOS translstor with lts gate eie~trode made of a P~-type semiccnductor or a P~-gate MOS translstor and a MOS translstor with lts gate electrode made of 5 an N~ type semiconductor or an ~+-gate MOS transistor. As already descrlbed wit~
reference to ~igures 7~(a) to 73(f), the above two ~ETs can be m~nufactured without the change or addltion of any step by +~he conventlonal CMOS manu~acturlng processO
In case of employlng the con~entional CMOS manufac-turing process, ~he self-allg~ment structure as shown ., ln ~igures 65(a) and 65(~) and Flgures 66(a) and 66(b) is obtained as s~ated below. 3ince the MOS translstors are o~ the P-channel in thls ¢ase, a P-~ype l~purity is 15 diffused into both end parts o~ a gate electrode ad~oining ., the source and drain in both the P~-gate MOS and ~he N~-gate MOS~ In a central part o~. the gate electrode, a P-type ~mpurity ls diffused for the P~-gate MOS, and a~ N-type imp~ritr is dlffused for the N~gate MOS~
Between ~he cent~al reglon and both thè end parts ad~oin-: ~ng the source and dra~n9 regions i in which no impur~ty is dlffused ~r~ disposed. m us, lt ls considere~ ~hat the .- dlf~erence o~ the P~-ga~e MOS and ~he N~-gate M~S is only t~e conducti~.rlty type (P or N) o:~ the semiconductor formi~g the ce~tral reglon of the gate.
. Further, ln order ~o reduce to the utmost ~he de~ia-tion (dlfference~ of the effeotive ch ~ el le~g~hs of ~he MOS transi~tors attributed to the fact that the reglons o~
the gates whlch are formed for the self~ali ~ e~t and in whlch ~he P-~ype lmpurlty is diffused shlft onto elther <(~ - 1 1 0 ~lS~88() ~, the left or right side ~source side or drain side) during manufacture o~ account of the error of the mas~
alignment~ the columns of ~he source regions and the drain reglons are alternately arranged, and the left hal~ and the right half are put into a line sy~metry wlth respect to the channel direction as a whole. Accordlngly, e~en when the misregistration of ~e mask ali~nment wi~h respect to ~le ch ~lel direction (left~rard or rlghtward shifting) changes the effective channel len~ths of ~he F$Ts ln +~he respecti~e columns~ the avera~e effecti~e channel lengths of the P+-gate MOS and ~he N~-gate ~IOS
in the respective columns connected in ~arallel ha~e the s~if~ing canceled as a whole and beco~e substantlally ' constant, Besldes by making the composl~ions of ~he gate el~c-trodes different, ~nequal threshold voltages are re~l.ized by the ion lmplantation into channels as descrlbed with reference to Flgure 7, by utllizi~g a ~opPd gate o~lde, by changing the ~hlckness of ~a~ lnsulating f~lm~, etc.
A~ example 1n Flgure 54 is ~he ~xample in whi~h ~he battery checker of the example o~ Figure 20 is applied to an elec~ronic timeplece.
Tl~ T2~ T41 - T4g ~nd R41 and R42 constltute a clrcuit whi~h chec~s the voltage le~el of a mercury bat~ery El ha~i~g a nominal ~oltage of 1.5 Y, A transis~or pair (Tl, T2) in a dlf~erential portion is constructed of a P+ gate N-channel ~OS Tl and an N~ gate N-chan~el ~IO~
T2 . the channel pcrtlons of which are subjected ~ ion implantatio~ so that the threshold ~oltages of both the transistors may lie within 1.0 V to 1.5 ~ beinO the ~4~8V
., operating power supply range o ~he electronic timepiece.
The difference of the threshold voltages t~ serve as a reference ~oltage is about 1,1 V in case of a silicon semiconductor. In order to set at about 1~4 V a level for detecting ~hat the voltage of the battery El has lowered, an adJustment ls made by the resistance ratlo of the resistance means R41 and R42, In order to make the current consump~lon ne~li2~ble in practical use, the battery checker is intermlttently operated by a clock signal ~ whlch is obtained from a frequency divlder circu~t FD and a timing circuit 5 An output o~ the battery checker is sta~ically held by a latch whlch is composed of NAND gates ~
and N~2, mhe timing clrcui~ ~- is controlled by a logic level o~ an ou~put from the latch clrcult, whereby a drivlng output of a motor is changed and the method of moving hand of the timepiece ls changed so as to indlca~e the lowering of ~he battery ~oltage. The luwering of the battery Yoltage can ~lso be indicated without chang-lng the mo~ement~ of the hand and by, for examplel fllcker-ing an electrooptlc device such as a lig,uld orystal and light e~itting diode.
In t~e fig~e, OSC l~clicates a cryst~l oscillatorcircui~ which is constructed of a C~fiJOS irlverter and 25 whlch also lrlcludes components outslde the IC, a c~ystal '~W. and capacltar~ces CG and CD~ WS indicates a waveform shaping ~rcult t~rhich converts the oscllla.,ion output from a sinusoidal wave into a rectangular wa~;e. C~,l indicates an exci~tion coll o~ a step m~tor for driving 30 the second hand. BFl and BF2 i~dlcate bu:~ers l,rhlch are - 112 ~

~lS488 constructed of CMOS in~erters and ~Yhich serve to drive the excitation coll ~I while lnverting the polaritles every second. ~.
All the clrcults withl~ the IC are operated by 5 ~he mercury battery ~1 of the nominal 1.5 V, ~1 is the tlming pulse generator clr~ult which revei~es a plu~allty o~ frequ~ncy di~lsion outputs of di~ferent frequencies from the fre~uency divlder clrcuit .~D an~
the control output of the latch composed of MAl and NA2 and ~hi~h generates pulse~ having a~y desired period and pulse wldth. The IC is of a monollthi~ ~i sem~conductor chlp for a hand type electronlc wrist ~hatch whlch ic fabrlcated by the Sl gate CMOS process already e~plalned ' with refererce to ~lgures 73(a) ~ 73 ~f).
Figure 55 shows an example of the co~struction of a circult system for an electronic wrist watch con- :
taining a battery checker therein. In thls example, the conductances o~ FETs Q4 and Q5 of a differe~tl ~ clrcuit are made unequal aa in Flgure 39, and ~he detectlon leve}
can be finely adJusted by mea~s of an adJust~ng reslstor R~ outs1de the IC~
Owing to ~he re~istor RJ, deviatio~s in ~he manu-fac~ure ca~ be perfectly avoided ~ use~
Now, an example i~ whlch the voltage regulator as shown in Figure 36ta) is applled to an electronic time-piece will be explai~ed wi~h reference to Flgure 56.
In Figure 56, OSC designates a crys~al oscilla~or, WS a waveform shapi~g clrcult whlch converts a sinusoldal wa~e oscillatio~ output lnto a rectangular wave, ~3 a frequency di~ider clrcuit, TM a ti~lng pulse generator .

B') circuit which prepares pulses of pr~determined period and width from frequency dlvlslon ~utputs, LF a level shlft circuit which converts a signal c~f low level into a signal of high level, BC a batte~y llfetlme detector, VC a ~oltage comparator, VR a voltage regulator ~ich uses the voltage compara~or VC, H a ho].d circult, DT
an oscillation state detector~ and LM ch~ excltat1on coil of a step motor for dri~ing a second hc~a.
The detector DT detects it through the f equency dlvlder FD and the tlmlng clrcult TM t~t the ~sc:Lllator OSC has oscllla~ed In case o~ ~he osclllatio~, lt actuates the v~lta~e regulator V~ to drop the operating voltage VOp of the oscillator OSC as well as '.~S, FD, I~l etc. into a value below the battery voita&e (-1 5 V).
The moment a battery E is turned "on", the Input node of an l~verter I7 becomes ~e earth potential (logic "0"~ owlng to a dlscharging resistor R104, so that an N-channel FET Q201 is brought i~to the "0~"
state and that the output of the regulator is made -1 5 V being the battery voltage At this time, a F~T ;~
Q203 is al~o t~rned ~ON", and the gate node of a FET Q202 ls charged. This ls to the end of previously making the negative feedback loop of the regulator active lest the regulator output should drop t~le moment the FET Q201 is subsequen~ly switched "OFF".
Wher. the oscillator has started operatlng, the o~her logical clrcults are alread~J ~n ~he operatlve state, so that a pulse ~B is supplied from the tlming circuit TM to the detectar DT~ ~ exclusi~e OR circuit EXl d~tects ~he issue of ~he pulse P'B One lnput thereof , . ..

;

~ 880 recelves the pulse ~B delayed by inverters I4 and I5 and an integration cir~uit C101 and Rlo~ wi~h respect to the other, Upon the issue of the pulse ~B 9 accord-ingly, a pulse of a width corresponding to the delay time ~s provided at the output of the gate ~Xl, This pulse is integrated by a rectifler cirsuit made up of a FE~
Q225~ an ~nverter I6 and a capacitor C~02, and ~urns "OFF" the N-channel FETs Q201 and ~03 p a short time ~ro~ the beglnnlng of the lssue of ~B.
Thus, the regulator V~ generates a pr~determined vo~tage (less than 1,5 V) at the source electrode of t'.~e con- :
troll~ng P-channel FET Q202 by the negative feedback cor.trol :
loop, ~nd it contributes to reduce the power dissipatlon , of the electronic timepiece.
Hereunder, the operation of the regulator, especially the voltage comparator VC will be explal~ed. Slnce this comparator VC effects an operation 3imilar to ~la~ of the comparator CP de~crlbed with reference to the principle dia~ram of Figure 35(a) Rnd the c~aracteristic dia~ram of Figure 35(b), only a brief explana~ion ~11 be gi~en~
Regarding P-channel MOSFETs Q206 and Q207' to obtain the offset voltage Yo~f, the gate of QZ06 is made ~he P~ ~ e as ln l of Flgure 60 and ~iO~ures 67(a) and 67(b), and the gate of Q207 is made tAe i type (intrinsic sem~conductor) as in Q2 of ~lO~ure 60 and ~iO~ures 68(a) and 63(b3. Accordingly, the threshold ~oltage Vth f Q207 becomes hlgher ~han '~at ~ Q20~ by about O.55 V
wnlch serves as the aforecited ofset voltage Voff.
On the other hand.~ since both an N channel FET Q~08 and ~0 a P-channel FET Q209 are diode connected, the sum of ~-1548fl~

both the threshold voltages Yth l.e. (V~hp + Vth~ ) is applled to the gate of Q207 being the non-invert~g lnput ~+) of the comparator VC, and the sum serves as the voltage Vref2 as indicated in the curve d in Figure 35(b).
On the other hand, the gate of the FET Q206 being the lnvertlng inpu~ (-) of the comparator is connected to the source o~ the controlllng P-channel FET Q~02 of the source ~ollower type, Accordlngly, the output voltage VOUt of the voltage -egula~or VR whlch ls generated at the source of the con-trolling FET Q202 under the control action of this co~trol ling FET Q20~ driven by -~he comparator VC becomes VOUt =
Vthp ~ Vthn ~ ~Voff (ln case where Yin ;~ Vthp +
~ Vthn + ~Voff)~ When ~he input vol~age Vin is low, the output voltage becDmes YoUt ~ V~n as ln the foregoing.
0~ course, the ou~put voltage VOUt of the voltage regu-lator YR ls utilized as the operating vol~age VOp of the oscll~ator OS~ as well as WS, FD, ~M, etc.
In order to render the power dissipation low, thls ~o comparator has ~he operating time limlted by a timlng signal ~A owing to the on-off opera~ion of the driYen ~ET
211- ~ course, the same applies to the c~rcuit for obtalning voltage Vref2~ To thls end, a oapacitor:C104 i~ connected to the gate of Q207 and a capacltance C10~ i~ c~nnected to the gate of Q20~ so as to hold the ~oltage of the reference voltage~ef2 and to ~ --hold the gate voltage of Q202' respectl~ely. Th~se capaci-tances C104 ~nd C105 are added sepa~a~ely fr~m para3itic capacltances such a~ ga~e capaoitance~. A capacitor C
~0 serves to prevent any oscillatlon which is attrlbuted to 8~3V

a phase rotatlon caused by the cascade connection of sev-eral ~ETs in the feedback loop, Since ~he battery checker BC has a construc~ion similar to that ln ~igure 54, the explanation is oml~ted.
At the output stage of the IC, ~rivers I2 and I3 ~or the exci~ation ooil dlrectly use the battery of 1.5 V as the power supply in order to make the driving capabllity hlgh Flgure 57 shows an example ln which the voltage regulator ~R and the battery checker BC accordlng ~o this inventlo~ are applled to a digital display electronic tlmepiece.
In the figure, parts OSC, '~t3 and FD use an adJusted voltage lower than 1,5 V as a power supply as in the example of Figure 56, and also loglcal clrcults withln an IC such as decoder DC and time correctlon clrcult TC
uqe the lower voltage as a power supply.
DB designates a voltage doubler circuit whlch boosts ~he voltage of 1~5 V to 3.0 V, ~hich is used-as a driYe v~ltage for a liquld crystal display DP (a drlver is ~ot shown). Each of LSl and LS~ ~ndicates a level shift circul~, whlch co~verts a low slgnal level lnto a high o~e DOC.-wlse and supplies lt to circults of high supply voltages. ~`~
It ls effectl~e for renderlng the power dlssipation low and the expansion of a servic power supply range that, as thus far described, the low opera'~ g power supply ls used for the ordlnary lo~ical circults wlthln the IC whlch operAte at low operatl~g volta~;es, while the high opera~ing power supply iq used for 1:he dlsplay ~ 80 driver etc. a~ the input/outp~t interface of the IC
which requlre high operating ~oltages.

Claims (4)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A method of manufacturing a semiconductor device with at least a pair of insulated gate field-effect transistors having semiconductor gate electrodes of different conductivity type, comprising the steps of:
preparing a semiconductor substrate having a semi-conductor region of a first conductivity type extending to a major surface of said semiconductor substrate;
forming an insulating film over said major surface at a first portion of said semiconductor region and at a second portion of said semiconductor region, and forming a semiconductor layer over said insulating film overlying said first and second portions of the semiconductor region;
forming a mask over a first portion of said semi-conductor layer overlain at said first portion of the semiconductor region except for a second portion of said semiconductor layer overlain at said second portion of the semiconductor region;
introducing an impurity of the first conductivity type into said first portion of the semiconductor layer except into said second portion thereof using said mask, to form a region of the first conductivity type having an impurity density at that portion;
removing said mask over said first portion of the semiconductor layer;
removing said semiconductor layer to form first and second semiconductor gate electrodes at said first and second portions of the semiconductor region respectively;
and selectively introducing an impurity of a second conductivity type opposite to the first conductivity type into said first and second portions of the semiconductor region with an impurity density lower than said impurity density of the first conductivity type at said first portion of the semiconductor layer using said first and second gate semiconductor electrodes as masks to form source and drain semiconductor regions of the second conductivity type on opposite sides of each of said first and second gate electrodes and to provide the second conductivity at said second semiconductor gate electrode while said first semiconductor gate electrode is held at the first conductivity type.

2. A method according to claim 1, wherein before the step of introducing the impurity of said second conductivity type, an insulating film is formed on said first semi-conductor gate electrode to serve as a mask to the impurity of said second conductivity type while an insulating film is formed on said second semiconductor gate electrode with a thickness thinner than that of said insulating film on said first semiconductor gate electrode.

3. A method according to claim 1 or 2, wherein said first conductivity type is the N-type, and said second conductivity type is the P-type.

4. A method according to claim 1 or 2, wherein said semiconductor layer is made of polycrystalline silicon.