CA1145063A - Reference voltage generator device - Google Patents
Reference voltage generator deviceInfo
- Publication number
- CA1145063A CA1145063A CA000395811A CA395811A CA1145063A CA 1145063 A CA1145063 A CA 1145063A CA 000395811 A CA000395811 A CA 000395811A CA 395811 A CA395811 A CA 395811A CA 1145063 A CA1145063 A CA 1145063A
- Authority
- CA
- Canada
- Prior art keywords
- voltage
- gate
- type
- semiconductor
- mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
REFERENCE VOLTAGE GENERATOR DEVICE
Abstract of the Disclosure The method is for manufacturing a semiconductor device with at least a pair of insulated gate field-effect transistors having semiconductor gate electrodes of different conductivity types. A semiconductor layer of one conductivity type is selectively removed to provide patterns of first and second gate electrodes, and a mask is formed over the first gate electrode except for the second gate electrode.
Thereafter, an impurity of the opposite conductivity type is introduced into the surface of a semiconductor substrate, over which the first and second gate electrodes are formed, to form source and drain semiconductor regions on opposite sides of each of the first and second gate electrodes and to convert the conductivity type of the unmasked second gate electrode to the opposite conductivity type. The method has the advantage of enabling manufacture of an improved semi-conductor device without increasing the number of fabrication steps.
Abstract of the Disclosure The method is for manufacturing a semiconductor device with at least a pair of insulated gate field-effect transistors having semiconductor gate electrodes of different conductivity types. A semiconductor layer of one conductivity type is selectively removed to provide patterns of first and second gate electrodes, and a mask is formed over the first gate electrode except for the second gate electrode.
Thereafter, an impurity of the opposite conductivity type is introduced into the surface of a semiconductor substrate, over which the first and second gate electrodes are formed, to form source and drain semiconductor regions on opposite sides of each of the first and second gate electrodes and to convert the conductivity type of the unmasked second gate electrode to the opposite conductivity type. The method has the advantage of enabling manufacture of an improved semi-conductor device without increasing the number of fabrication steps.
Description
~:~45~63 This application is a division of Application Serial No. 321,955 filed February 20, 1979 and relates to a method of manufacturin~ a semiconductor device.
In generating reference voltages in various semi-conductor electronic circuits, it is necessarv to utilize a physical quantity having the dimension of the voltage.
As such physical quantities, there have until now been solely utilized the forward voltage drop VF or reverse breakdown voltage (Zener voltage) Vz of a PN-junction diode, the threshold voltage Vth of an insulated gate field-effect transistor (often represented by an IGFET or MOSFET), etc.
These physical quantities do not indicate vol-tage values which are absolutely fixed, since their voltage values are subject to fluctuations due to various fac-tors. In order to make use of these physical quantities for reference voltage generator devices of various elec-tronic circuits, accordingly, attention must be paid to the factors which cause the fluctuations of the voltage values and the allowable limits of the fluctuations.
First of all, the voltages VF and Vth usually have a temperature-dependency of approximately ~ - 3 mV/C. The fluctuation of the reference voltage attendant upon the temperature change reaches such a magnitude that their application has to be given up in some uses.
By way of example, when a battery checker for pro-viding an alarm when the voltage of a battery has fallen below a predetermined reference value is intended to be realized in an electronic timepiece which employs a silver oxide battery having a nominal voltage of 1.5 V, whether the battery voltage is high or low needs to be judged with ~ 3~
the boundary (detection level) or the detection reEerence value at about 1.4 V.
When a reference voltage generator device is to be constructed by exploiting the threshold voltage Vth of a ~OSFET or the ~orward drop voltage VF of a diode which is about 0.6 V, the detection level aimed at 1.4 V has a temperature-dependency of:
0 6 (V) x {2 ~ 3 (mV/C)} = 4.67 ~ 7.0 (mV/C).
Accordingly, even when the practical operating tem-perature range is estimated to be as narrow as 0C to50C, the detection level fluctuates as much as 1.23 V
to 1.57 V, and a satisfactory battery checker cannot be obtained.
Furthermore, the physical quantities suffer from dispersions or deviations in the manufacture. For example, the threshold voltage Vth of a MOSFET has a dispersion of about +0.2V, which is greater than the temperature fluctuation. Accordingly, when the above-stated battery checker is put into the form of an IC
(integrated circuit) by exploiting the voltage Vth, not only is there the difficulty of providing the external components and external connection pins (external connec-tion terminals) necessary for adjusting the reference voltage, but also additional labor is required to carry out the adjust~ent after the fabrication of the IC.
The lower voltage limit of the Zener voltage Vz is about 3 V, and it is impossible to generate a reference voltage to be used in a low voltage range of 1 to 3 V or so. When using the Zener voltage or the forward drop voltage of a diode as a reference voltage, a current of the order of several mA to several tens of mA needs to be caused to flow, which is inappropriate from the point of view of lowering the power dissipation of the reference voltage generator device.
It is apparent from the above explanation, that the S conventional reference voltage generator devices exploiting the voltages Vth, VF and Vz have not always been suited to all the uses when the temperature characteristics, the dispersions or deviations in manufacture, the power dissipation, the voltage leve] etc.
are taken into account. For uses requiring very severe characteristics, it has often been the case that the practical use or the mass production must be relinquished.
The inventors of this invention have thus appreciated that improvements in the conventional reference voltage generator devices are subject to physical limitations and carried out research in order to develop a reference voltage generator device based on a new idea or concept.
To this end the invention consists of a method of manufacturing a semiconductor device with at least a pair of insulated gate field-effect transistors having semiconductor gate electrodes of different conductivity type, comprising the steps of: prepariny a semiconductor substrate having a semiconductor region of a first conductivity type extending to a major surface of said ~5 semiconductor substrate; forming an insulating film over said major surface at a first portion of said semi-conductor region and at a second portion of said semi-conductor region, and forming a semiconductor layer of a first conductivity type over said insulating film over-~0 lying said first and second portions of the semiconductorregion; removing said semiconductor layer to form first ~5~3 and second semiconductor gate electrodes at said first and second portions of the semiconductor region respectively;
selectively forming a mask over said first semiconductor gate electrode except for said second semiconductor gate electrode; and selectively introducing an impurity of a second conductivity type different from said first conductivity type and opposite to the conductivity type of said semiconductor region into said first and second portions of the semiconductor region using said mask, to form source and drain semiconductor regions of the second conductivity type on opposite sides of each of said first and second gate electrodes, and to convert the first conductivity type of said second semiconductor gate electrode to the second type as well as to convert the first conductivity type of the periphery positions of said first semiconductor gate electrode to the second conductivity type.
Various preferred embodiments of this invention to be described later and of inventions disclosed herein and 2Q claimed in the parent application referred to above and other divisional applications filed simultaneously herewith have the following advantages:
(1) ~ reference voltage generator device having small temperature variations can be provided.
~5 (2) There can be provided a reference voltage generator device in which the fluctuations of the voltage value to be obtained are small with respect to the fluctuations in manufacturing conditions, for example, the manufacturing dispersions (deviations) among various lots are ~uite 3Q small.
- 5a -~4S~3 (3) There can be provided a reference voltage generator device in the form of an integrated circuit which can diminish the manufacturing dispersions to such an extent that no adjustment after manufacture is necessary.
(4) There can be provided an electronic circuit device in the form of an integrated circuit including a reference voltage generator device which can be manufactured with a large tolerance relative to a specification aimed at.
(S) There can be provided an electronic circuit device in the form of an integrated circuit including a reference voltage generator device which has a high manufacturing yield, i.e. a high efficiency percentage.
(6) A rèference voltage generator device which is suited to an IGFET integrated circuit can be provided.
~7) A reference voltage generator device and a voltage comparator which are of low power dissipation can be provided.
~8) There can be provided a reference voltage generator device which can produce a low voltage (of or below 1.1 V) of very good precision.
(9) There can be provided a reference voltage generator device which is suited to a power source of a comparatively low voltage (approximately 1 to 3 V), for example, a silver oxide battery of 1.5 V or a mercury battery of 1.3 V.
(10) It is possible to provide a reference voltage generator device which is suited to a semiconductor integrated circuit.
(11) It is possible to provide a voltage comparator 4~
~ a stabilized power supply device, a constant-current circuit and a battery checker which have high precision.
(12) It is possible to provide a semiconductor integrated circuit device for an electronic timepiece which contains a battery checker of high precision therein and which has a small number of external terminals.
(13) It is possible to provide an IGFET integrated circuit in wliich the threshold voltage of an IGEET with a back bias applied thereto can be maintained at a substan-tially constant voltage independent of dispersions in manufacture and changes in temperature, whereby the yield of manufacture can be enhanced.
(14) It is possible to provide a reference voltage generator device whicn is compatible with a complementary type insulated gate field-effect transistor integrated circuit (CMOS IC) or with an N-channel MOSIC or P-channel MOSIC, and a method of manufacturing the same.
(15) It is possible to provide a constant-voltage output circuit which is suitable for making the power dissipation low. That is, there can be provided a constant-voltage output circuit which produces a stabilized voltage with a low absolute supply voltage, such as the battery voltage, and which has a low power dissipation.
(16) It is possible to provide a reference voltage generator device which is compatible with the so-called silicon gate insulated-gate field-effect transistor integrated circuit employing siJicon for the gate electrodes, and a method of manufacturing the same.
(17) There can be provided a method of manufacturing a reference voltage generator device without increasing the number of fabricating steps in the fabrication of a silicon gate P-channel IGFET integrated circuit.
(18) There can be provided a reference voltage generator c;rcuit which e~ploits the difference of the Fermi levels of aluminum and intrinsic silicon, which does not employ P-type silicon containing a P-type impurity, such as boron, liable to be introduced into a channel portion through a gate insulating film and which undergoes small dispersions in manufacture.
(19) It is possible to provide a method of manufac-turing a reference voltage generator device which can prevent an acceptor impurity forming a P-type silicon gate such as B, A~ and Ga from being introduced into a channel portion through a gate oxide film to change the threshold voltage of an IGFET whose gate electrode is made of the P-type silicon.
(20) It is possible to provide a semiconductor memory which has the function of preventing any erroneous writing in a data retention mode. That is, when a supply voltage ~0 has become below a set detection voltage, at least one of control signals required for a writing operation can be inhibited.
(21) It is possible to provide a Schmitt trigger circuit which is constructed of MISFETs (insulated gate field-effect transistors) and whose hysteresis curves have a width which varies little due to the fluctuations of a supply voltage, the manufacture dispersions of the MISFETs, the changes of the temperature, etc.
This invention has been made by going back to the starting point of the physics of semiconductors and taking special notice of the energy gap Eg~ the Fermi level Ef, etc.
It is well known that semiconductors have energy gaps Eg and various levels such as donor, acceptor and Fermi levels. However, until now there have been no proposals to produce a reference voltage generator device utilizing the physics of semiconductors, especially the energy gap Eg and the Fermi level Ef, despite remarkable develop-ments achievèd in extensive fields since the discovery of semiconductors.
Based upon actual results, the inventors thought of utilizing the energy gap Eg, the Fermi level Ef, etc.
for reference voltage sources and have succeeded in this realization. It is not difficult in theory to use the energy gap Eg~ the Fermi level Ef, etc. for reference voltage sources, and the results will be readily under-stood. However, the success achieved by the inventors is believed to be unprecedented, particularly from the point of view that the inventors have gone back to the starting point of the material properties of semiconductors, bearing in mind that the history of the semiconductor industry is no longer short. This development is therefore believed to be creative and epochal, and is expected to contribute greatly to further advancements of electronic circuits and the semiconductor industry in the future.
According to the invention there is provided a reference voltage generator device comprising means for detecting à voltage substantially equal to or smaller than an energy gap of a semiconductor or a voltage based on an energy level of a semiconductor, a voltage based on the detected voltage being used as a reference voltage.
According to a preferred embodiment of this invention, two IGFETs which have silicon gate electrodes of conduc-tivity types opposite to each other are fabricated within a silicon monolithic semiconductor integrated circuit chip. Since these FETs are manufactured under substan-tially the same conditions except for the conductivity types of the gate electrodes, the difference of the threshold voltages Vth of both the FETs becomes approximately equal to the difference of the Fermi levels of P-type silicon and ~I-type silicon. The gate electrodes are doped with respective impurities in the vicinities of the saturation densit-ies, and the difference becomes approximately equal to the energy gap Eg of silicon tabout 1.1 V), which is utilized as a reference voltage source.
Since the reference voltage generator device based on such a construction has low temperature-dependency and small manufacture deviations, it can be used as a reference voltage generator device in various electronic circuits.
The invention, and in particular the preferred embodiments thereof, are discussed in detail in the following with reference to the accompanying drawings, in which:-Figure 1 is a diagram showing the band gaps Eg of GaAs, Si and Ge and their temperature-dependencies;
Figures 2(a) to 2(d) are diagrams showing the band structures and Fermi levels Ef of semiconductors, in which Flgures 2(a) and 2(b) illustrate an example of an N-type semiconductor and Figures 2(c) and 2(d) illus-trate an example of a P-type semiconductor;
Figure 3, which appears on the same sheet as Fig. 1, ~S~;3 is a diagram showing the temperature characteristics oE
the Fermi levels of N-type and P-type Si with the impurity densities being a parameter;
Figures 4(a), 4(h) and 4(c) are diagrams showing the distributions of energy levels possessed by Ge, Si and GaAs semiconductors and various donor and acceptor impurities, respectively;
Figures 5`(a) and 5(b) are diagrams showing the energy state and the states of charges of a P+-type semiconductor -insulator - N-type semiconductor structure respectively, while Figures 5(c) and 5(d) are diagrams showing the energy state and the states of charges of an N+-type semiconductor -~ ~ ~ S~ ~ 3 lnsulator - N-type semlconductor stru ture respectively;
Figures 6(a) and 6(b) are a characteri~t~c dlagram and a circult dlagram of a MOS diode circul~ for derlvlng the dlfference of Vth of two F~Ts having unequal thresho`d voltages Yth respectively;
~igure 7 is a characteri~tic diagram showing ~i~é
situation in which a threshold voltage is ~hanged by ion implantation .-Figures 8 and 9 are diagrams each showin~ an exam?le of a reference voltage generator circuit which explolts the difference of threshold voltages Vth, ~igure lO(a) ls a circuit dia~ram of a reference voltage gene~tor cir~^ult showlng an embodi~nt of thls inventlon, whlle Flgure lO(b) ls an operatlng wavefor~ diP~ram of the circuit ln ~ure lO(a);
Figure ll(a~ shows a furth~r exam?le o 8 reference voltage generator circult, whlle ~igure ll(b) shows timing slgnal waveform~ thereo~; ~
~igure 12 shows a referenc~ Yoltage generator clrcuit which 1~ ba3ed o~ another embodiment;
~igure 13 ~hows an op~rational ampllfler circuit whlch ha~ an offset voltage in accordance wlth thi3 inYention;
Figure 14 ~how~ a re~erence Yoltage generator circult whlch u~ilize~ the operational ampliflar circult of Figure 13;
a5 Flgure~ 15, 16 and 17 show reference voltage generat.or circults which utilize operational amplir~er circuits accor~-lng to other embodiment.~;
~igures 1~ and 1~ ~how volta~e deteGtcr oircults each of which employa a re$'e~ence vol~a~e produced fro~ the 3Q reference volta3e ge~erator circult a¢cordlng to thi in~en~on, - 12 ~
~ 3 Flgure 20 shows a ~oltage detector clrcult which utilizes an o,oeratlonal a~plifier clrcul~ havln~ an offset voltage ln accordance wlth th'~ inventlont ~i.3ure 21 shows a ~Joltage comoarator whlch is for~.ed ~y connecting MOSFETs of unequ~l thres~.old voltages ~h in the dlfferent~al type in accordance witn this invent1 on;
Fizu.e 22 3hows a differential a~Qplifier clrcult whlch employs ilOSF~s of unequal threshold voltages Yth ln accordar.ce with thls inventlon;
~l~ure 23 shows the drain current - ~ersus - ~ate volta~e characteristlcs of the diff~rentlal pair ~OS tra~sistors of the differentlal am?lifier circult show~ ~n Fl~ure ~2;
~igure 24 shows an offse. ~ype vo'tage cG~oarator clrcuit whlch is const~u¢ted of a voltage eo~?aratGr clrcult and source follower circults employlng two MCSF~Ts of threshold ~olta2es dlf~erent fro~ each other in accordan~e wlth thls invention Figure 25 shows an offset type voltage ~o~parator circuit whlch is constructed of a voltage comparator clrcuit ~0 and ~rounded-source clrcuits e~ploying two S~IOS~ETs of threshold voltages dlfferent from each other in accordance with th's lnvention;
Figure 26 showe an example of a co~stant-current clrcult whlch is used in the offset type voltage comparator clrcult o~ Figure 24;
Flgure 27 show3 a refere~ce Yoltage ~en~rator sircuit which employs the differentlal amplifier clrcuit ~hown ln Fi~ure 22 Fl~u~e 28 shows the detalls of tne off~e~ typ~ ~oltage 3 0 co~parato, circuit ~hown ln Fi~ure 24, and lllustrates a case ~5~3 in which a reference voltage generator circuit is constructed by employing this voltage comparator circuit.
~igurQ 29 shows a constant-currel~t circuit whlch exploits the di~ference o~ the th~eshold volta~es of ~o S MOS~Ts in accordance wlth this lnvention~
Fi~ure 30 shows a constant-current circuit ~o whicn is applled a reference ~oltage generator ci.cuit that produces a reference ~oltage on the basis of the ~lfference of tne threshold voltages of two ~iO~_Ts in accord~nce with thls inv~ntion, ~igure 31 shows a constant-current circuit i~ w~ich a current mirror circult is added to t~e ca~sta~t-current ~-ircult shown in FiOure 30;
~igures 3~ and 33 are circuit ~ r~s e2ch ~howinO
a stablllzed power sup~ly circult to whi¢~ is applied a reference volta~e generato, clrcuit that produces a reference volta3e based on the dl~ference of the threshold Yolta~es of ~tOS~Ts in accordance wlth thi~ invention, ~igure 34 shows a ~tabillzed power supply ~ircult to which is applled an operatlonal ampllfier that ha~ the difference of the threshold volt2ges of MOSF3Ts as 1~ off~
set voltage in accordance with this lnventlon, Fi~ure 35(a) is a circuit diagram for explaining an exa~ple of a voltage regulator to whlch an off~et type a s operational amplifier cireuit accordlng to thi3 invention ls applied, while ~l~ure 35(b) 1~ a~ electr~cal char~cterlstic diagram for explalning the operatlon of the voltage re~ulator, ~igure 36(a) ls a ~ircu1t dlagram for explaln~n5 a ~oltage regulator accord~n6 to another emoodlment o~ tnl3 ln ention, 3 O while ~ure 36(b) is an electri¢al ¢haracteristlc diagra~
SI~i3 for explaining the operation of the volta2e regulator;
r igure 37 is a circuit diagram showing an example ln the case in which this invention is applied to a battery life~iQe detector circuit;
Figure 38 i~ a diagram o~c~ circuit for a clocX-drlven battery checker accordin~ to another embodi.~ent, ~igure 39 is a diagra~ of a reference voltage generator circuit whos-e"'reference voltage can be flnely adJusted w1th a resistor outside an IC, l~ Figure 40(a) shows a Schmit~ trlgger circult to ~hich the princlple o'f thi~ in~entlon is applied, while Figure 40(b) shows the hysteresis charac~eris~ic of the Schmitt trigger clrcuit, Figure 41 shows ~ Schmitt trlgger circuit according to another embodlment, Figure~ 42 and 43 are diagra~s each showing an oscillator circult to which the Schmltt trig~er clrcult ac~ordin~ to this invention is applied, ~igure 44 3hows a differen~lal ampllfler whlch e~ploys a o MOSFETs Figure 45 shows a TTL - MOS signal level shifter clrcult according to this inventio~;
~igure 46 shows a logiG threshold stabllizer circult according to thlx invention a 5 Figure 47 shows a substrate bia~ senerator circuit according to thl~ lnvention;
~igure 48 ~how~ a status settlng ¢lrcult accordlng to this invention r i~ure 49 3h~w~ a ~tatus settlng ~ircuit ~,~hlch has hitherto beer. proposed;
~ ~ ~ 5~ ~ 3 Flgure 50 shows a MOS memory which employs the substr2te bi~s generator circuit shown i~ Fi~ure 47;
~igure 51 shows a memory cell in the ~IOS memory o~' ~igure 50, ~lgure 52 ~hows a sem$conductor random acce~s memory accord~ng to thlq lnvention;
Fl~ure 53(a) ~hows a voltage detector circuit which ls used i~ the semiconductor ra~dom acce~s me~ory ac~ordln~ to thi~ invent-i-on, wh~le ~igure 53(b) shows the operatlng ~ave-forms of the ~oltage detector circuit~
Flgure 54 shows an electronic timeplece to whlch ~he battery checXer shown ~n ~igure 20 ls applled;
Flgure 55 shows an electronic timep~ece to ~h~ch a similar battery checker 15 applled;
Fl~ure 5~ shows an electro~ic timepiece to wh~ch the ~oltage re~ulator as shown in ~igure 36(a);
~lgure 57 shows an elec.roric ti~epiece to which a siQllar volt~ge regul2tor is applled;
Figure 58, wh~ch appears on the same sheet as Fig. 61, is a structural sectional view of two MOSFETs which have threshold voltages different from ea¢h other in accordan~e with this invention;
~i2ure 59 schematically show sectlonal structures of p~ gate and N+ gate ~IOSFETs usable ror derlving the dlfference L5 (Ern - Efp) of the ~ermi level3 of N-type and 2 type se~i-conductors, in which the left hal~ shows a P-channel F~T
whlle the ri8ht half shows an N-channel ?ET
~i~ure 60 also scheQatic211y shows ~ectlonal s-ructures of p+ gate and ~ ~ate MOS~-~Ts usable ~or deriving the dif'erenCe (Et~n ~ Erp) 0l the ~ermi leYels of N~type ~nd P-type sem~conduct~rs, in which ~he left hal~ sho~s a ~5~3 P-channel Fr.T while the rlght half show_ an ~-channel ~T
Flgure 61 si~ilarly shows a structure of two P-channel ~OSFETs whlch have threshold volta~es different from eac~
other;
`~ ~ Flgures 62 and 63 are sectional views each showln~ ~he essential portion~ of MOSFET wh~ch are required for the constructlon of thls invention and whlch ha~e ~ate electrodes of different ~ermi levels Figure 64 ls a sectlonal vlew of the essential portions l~ o~ ~SOS-r~.Ts whlch constltute a reference volta~e ~enerator devlce according to thls lnvention;
Flgureq 65(a) and 65(b) are plan view an~ a ~ectional vl~w o~ an ~+ gate P-channel ~3~ET respecti~ely the sectlon21 views being ta'~en along lines indlcated by arrows Ln the l5 .- correspondlng plan vlews;
Flgures 66(a) and 66(b) are a plan vlew and a sectional ~lew of a P~ gate ?-channel ~tOSF~T, respect~vely;
~lgur~67~a) and 67(b) show a plan vlew and a sectlonal vie~ of a P~ gate P-channel M03FET, respectlvely, ~0 Flgure3 68( A) and 68~b~ show a plan view and a sectlonal vlew of an i ~ate P-channel MQS~T, respecti~ely;
Flgures 69(a) and 69tb) show a plan view a~d a section21 vlew o~ an ~1~ gate P-channel MOS~ET, respecti~ely, Figures 70(a) and 70(b) how a plan vlew and a se¢tional ~5 view of an N~ gate N-channel MOSFET, re~pectlvely;
Figures n (a) and n (b) qhow a plan vlew and a sectlonal view of an i gate ~-channel MOS~T, respect~Yely;
Fi~ures 72(a) and 72(b) ~how a plan view and a sectional Yiew of a P+ gate N-ch~nnel MCS~5., respectively Figures 7~(a) to ?3~) illustr~te that ;~ ~ate (~ar. B3 ~ ~ ~ 5~ ~ 3 and P+ ga~e (part A) P-cha~nel MOS~ET~ are fabricated together with a P-channel ~ET (part C) and an N-channel FET (part D) which const~tute a conventlonal co~ple~entary ;.OS device;
~lgures 74taj to 74~d), ~lgures ?5ta) to 75~d), ~i~ures 76(a) to 76(d) and Figures 77(a) to 77td) show sectional ~iew l.n the prlncipal steps in .he case o~ ~anufac-turln3 two MOS?ET~ according to this invention .o~ether w'th a co~plementary ~OS device, respectively, Flgures 7~(a) ~o ?8(e) ~how secti~nal views ~n the various step~ of manuf'acture in the Gase Or ~-¢hannel MOa~ Ts;
~i~ure~ 79(a) to 79(e), Figure~ ~O(a) ~o ~Q~d) 2nd F~gures 81(a) to 81(d) a~e sectional v-iews in vari~us steps for explainlng a method o manufacturLng ilOSF~T~ ~or use in a re~erence voltage generator circult devlce accord'ng to this invention, respectlvely, and Figures 82(a) and 82(b) and Figure~ 83(a~ to 83(d) show sectional ~lews ln Yar~ ou3 ~tep~ f~r ex~laining another method of manufacturin.~ MOSFETs ~or use in a reference ~O ~oltage genera~or clrcuit device a¢cordln~ to thls invention, respectively.
The physics of semiconductors which begins with the crystalline structure of a semicondu~tor and which develops into the energy band o~ a semicondu~tor and phenomena brought about by donor and acceptor impurities are well explained in the literature.
It ~s, of course, well ~nown th2t semiconductor~ Or dlfferer.t composit~ons ha~e energy ~aps ~g Lnherent thereto and that the energy gap ~g exp~essed in eV has the dimension ~0 ~5~3 of a voltage. As previously stated, however, there has never been any suggestion of using the energy gap Eg as a reference voltage source based on the fact that the energy gap Eg exhibits a low temperature-dependency.
The present invention has been made by starting from the fundamentals of the physics of semiconductors. There-fore, the detailed description of this invention will be commenced by briefly referring to the pertinent points of the physics of semiconductors. Since the material pro-perties of semiconductors are explained in extensivedetail in many publications, reference will be made to one such publication, namely "Physics of Semiconductor Devices" by S. M. SZE, published by John Wiley & Sons in 1969, especially Chapter 2 "Physics and Properties of Semiconductors" on pp. 11 - 65.
Application of Energy Gap E
g Semiconductors have a variety of compositions. The semiconductors typically utilized industrially at present are non-compound semiconductors of germanium (Ge) or silicon (Si), and gallium-arsenic (GaAs) compound semi-conductors. The relationship between the energy gaps Eg of these semiconductors and temperature are explained on page 24 of the publication referred to above, and is reprinted in Figure 1.
As seen from Figure 1, the energy gaps Eg of Ge, Si and GaAs are 0.80 (eV), 1.12 (eV) and 1.43 (eV~, respec-tively, at normal temperature (300 K). Their temperature-dependencies are 0.39 (meV/K), 0.24 (meV/K) and 0.43 (meV/K), respectively. By deriving voltages of values equivalen~ to or close to the energy gaps E, accordingly, reference voltage generator devices can be obtained which -- 1~ --~ ~5~
have temperature-dependencies one order smaller than those of the forward voltage drop VF of a PN-junction diode and the threshold voltage Vth of an IGFET as stated previously. Furthermore, the voltage to be obtained is determined by the energy gap Eg inherent to the semi-conductor. With, for example, Si, it is about 1.12 tV) at normal temperature substantially independently of other factors. It is possible to obtain a reference voltage which is not affected by dispersions in the manufacturing conditions etc.
An example will now be explained as to the principle upon which the voltage corresponding to the energy gap Eg of the semiconductor can be derived.
Application of Difference of Fermi Levels (Work Functions) of N-type, i-type and P-type Semiconductors The conditions of energy levels when doping semi-conductors with donor and acceptor impurities are well known. Especially noteworthy to this invention is the phenomenon that the energy levels at which the Fermi energies of N~type and P-type semiconductors are located are separated towards a conduction band and towards a valence band with respect to the Fermi energy level Ei o~ an intrinsic semiconductor. The energy levels become more distant from the Fermi level Ei of the intrinsic semi-conductor as the densities of the acceptor and donor impurities increases, the Fermi level Efp of the P-type semiconductor comes close to the top Ev of the valence band, while the Fermi level Efn of the N-type semi-conductor comes close to the bottom Ec of the conduction band. Accordingly, when ~5~3 the di~ference (Efn ~ E~p) of.both the ~ermi levels i~ ta'~en, the energy level di~ference is substantially approximate to the ener~y gap ~ po~sessed by the semiconductor and it~
te~perature-depe~dency is also approx$mate to that of the energy gap Eg. The sPme applle~ to the dif~ere~ces tEfn ~ ~1) and (~1 - rfp) between the ~erml level-~ o~ ~he P-t~pe se.~
conductor and the intrin31c semlconductor a~d bet-~een the ~er~i levels of the N-type semlconductor and the intrinsic ~emlconductor. In th~s case, however, the a~solute value approaches Eg/2. In the following, the differences relative to the intrinsic semiconductor wilL not be described in detail on the qround that they become one half of the diference oet~een t~e P-t~e and the ~-type. ~s ~ill be stated ln detail later, the higher the impurity concentratlon, the lS lower ~he ~emperature-dependency of (Efn ~ Efp). In order to attain a 2reat energy level dlfferenGe approxlm2te to the energy ga~ Eg and to atta~n a low tempera~ure_depe~dency thereof, accordingly, it 15 ~a~orable to establish an impurlt-~
density a~ close to the ~aturation denslty as possible.
a~ The Fermi levels Efn and Efp concern not only the density o~ the donor or acceptor impurity but also ~nor or acceptor levels Ed or Eal which differ according to the impurity.
materials. As t~e level Ed or ~a ha~ an energy level nearer to the conductlon ~and or the val~nce band respecti~ely, ~he as Fermi level Efd or ~a comes clo~er theretoO In other words, as the impurity levels Ed a~d ~a of the do~or anA acce~tor have s:~a~lcwer level~, the difference ~f~ - Efp) of the ~erm.~ level~ co~es clo~er to the anergy gap ~z of tbe se~i-conductor.
As the impurity level ~d or E of the donor or acceptor ~ ~ ~ S ~ 3 is closer t the ~ermi level El of the intrlnslc semi-conductor, that ls, as tt ha~ a deeper level, the dlfference (Ef~ - ~fp) of the Fermi level~ becomes more distant from the ~nergy gap Eg o~ the semiconductor. This, however, does S not slgnify that the temperature-de2endenc~ degrade~, but signifies that the absolute value of the d~fference (~fn ~ ~p) of the Fermi levels dimlnishes. Accordingly, the dlfference ( ~ fn ~ ~fp) o~--the ~ermi levels ~r the dlfference of hork functlons is a physical q~antlty lnherent to the semiconductor ma~erial, the impurity materials, etc. ~rom another vlewpolnt, it can become a reference voltage source parailel or sl~llar to the energy gap Eg of the semiconductor. That 15, the difference (Efn - E~p) of the Fermi levels ~ se can be-come a reference voltage source whlch i5 lower in temperature-1~ dependency and less liable to be affected by the manu~a¢turing conditions than ~he forward Yoltage drop YF of a PN-Junctlon and the threshold voltage Yth of an IGFET. In consequence, the expedient of taking out the difference (Efn - E~p) of the ~erml levels by the use o~ impurity materlals exhiblting a~ donor and acceptor level~ Ed and Ea having shall~w levels c2n become one method for derivlng a Yoltage of a va}ue substantially approximate to the energy gap ~g of the semi~
conductor. n the other hand, as regards the setting of a voltage value to be obtained, when it is desire~ to obtain a~ a comparatively large rererence voltage equiYalent to the.
energy ~ap of the semiconductor, impurities whl~h exhlbit shallow levels may be used, and when it is desired to obtain a comparatively small reference volta~e, impurities which exhibit deep levels may be used.
SPecific Examples of the Selecti_n of Impurity Materials . . .
~ - 22 -~ . .
The relations between the Ferml level ~f and the donor level Ed, acceptor level 3a9 donor denslty Nd, acceptor denslty Na and the temperature T will be described in detail ~ith reference to Figure 2 and ~igure 3. ~rior to this description, the data on page 30 of the aforementioned publication as reprinted in Figure 4 wlll be referred to in order to explain what leveis various impurities present to ~he Ge, Si and GaAs semiconductors and to explain how ~he impurities are utili~ed in this invention.
1~ Figures 4(a), 4~b) and 4~c) are d1agrams ~hlch show the ener~y distrlbutions o~ various impur't1e5 for Ce, S1 and ~a.~s, respectively. The numerals in the respective diagrams lndicate energy dif~erence3 (Ec ~ Ed) ~rom the ~ottom ~c of a conduction band as to leYels located above the center of a ~ap or the ~ermi level o~ an intrinsl¢ 3emiconductor ~i drawn by a broken line, and indlcate ener~y d~f~erences (~a ~ rv) from the to? E~ of a valen¢e ba~d as to leveis located below the gap center E~, the unlt belng (eY) ln both the cases.
a~ Accordingly, an impurity material indicated by a small~
nu~erical value ln each dlagram ls such that lts level ls close to the bottom Ec of the conduction band or the top ~y of the valence band, and it ls appropr~ate as an i~purlt~
for obtalning a voltage close to the energy gap ~g~ By way ~5 of example, for S1 whlch ls used most ~reouently at present, le~el dlfference~ (~c ~ ~d) and (Ea - E~) respectlvely e~hiblted by the dcnor impurities Li, S~, P, As and Bi and the acceptor impuriti~s B, Al and Ga are the smallest, and ~cth ~he level dl~erences are below about ~ f the 3~ energy ~ap F5 of 3i. ~hen a tempe.at~r~ char~e fro~ C c,~c s ~ 3 neglected, the di~ference (E~d - E~a) of ~e ~erml levels of N-~ype Si and Ftype Si employing these lmpuritles becomes about 94 ~ - 97 % of the energy gap ~g o~ Si, whlch value is approximately equal to ~8~ ~ donor impurity and an acceptor Impurity which exhi~lt the smallest level differences (Ec ~ Ed) and (Ea - ~y) next to the above lmpurities are à
(about 16 ~ of ~g) and In (abou~ 14 ~ o~ ~g), re~pectlvely.
T~ differenc.e t~fd ~ fa) of the ~er~i levels of ~t-type Si and P-type Si employlng the respectl~e i~purities ~ecomes about 0.8~ ~g at 0 ~, and the devl~ticn from the energy gap ~g Or Sl is as great as about 15 ,'~. It is accordingly understood that the dev~atlon ls much greater than those of the aforementioned impurities.
Thus, one donor impurity selecte~ from the group con-sl~itin~ of L~, Sb~ P, As and ~1 and one ac¢eptor i~purity selected fro~ t~e group ¢onsistir.g of 3, ~1 and Ca are suitable as the impurity materlals o~ P-~ype and ~ pe ~i for obtaining a voltage sub~tantlally eq~al to the energy gap ~g of Si. The other impurities will ~e ~u~ted to the a~ end of obtaining voltages considerably smaller than the energy gap Eg of Si.
Physics of Fermi Level Er Now, the difference (Efn - Efp) of Fermi leve~s will be explained with reference to Figures 2(a~ to
In generating reference voltages in various semi-conductor electronic circuits, it is necessarv to utilize a physical quantity having the dimension of the voltage.
As such physical quantities, there have until now been solely utilized the forward voltage drop VF or reverse breakdown voltage (Zener voltage) Vz of a PN-junction diode, the threshold voltage Vth of an insulated gate field-effect transistor (often represented by an IGFET or MOSFET), etc.
These physical quantities do not indicate vol-tage values which are absolutely fixed, since their voltage values are subject to fluctuations due to various fac-tors. In order to make use of these physical quantities for reference voltage generator devices of various elec-tronic circuits, accordingly, attention must be paid to the factors which cause the fluctuations of the voltage values and the allowable limits of the fluctuations.
First of all, the voltages VF and Vth usually have a temperature-dependency of approximately ~ - 3 mV/C. The fluctuation of the reference voltage attendant upon the temperature change reaches such a magnitude that their application has to be given up in some uses.
By way of example, when a battery checker for pro-viding an alarm when the voltage of a battery has fallen below a predetermined reference value is intended to be realized in an electronic timepiece which employs a silver oxide battery having a nominal voltage of 1.5 V, whether the battery voltage is high or low needs to be judged with ~ 3~
the boundary (detection level) or the detection reEerence value at about 1.4 V.
When a reference voltage generator device is to be constructed by exploiting the threshold voltage Vth of a ~OSFET or the ~orward drop voltage VF of a diode which is about 0.6 V, the detection level aimed at 1.4 V has a temperature-dependency of:
0 6 (V) x {2 ~ 3 (mV/C)} = 4.67 ~ 7.0 (mV/C).
Accordingly, even when the practical operating tem-perature range is estimated to be as narrow as 0C to50C, the detection level fluctuates as much as 1.23 V
to 1.57 V, and a satisfactory battery checker cannot be obtained.
Furthermore, the physical quantities suffer from dispersions or deviations in the manufacture. For example, the threshold voltage Vth of a MOSFET has a dispersion of about +0.2V, which is greater than the temperature fluctuation. Accordingly, when the above-stated battery checker is put into the form of an IC
(integrated circuit) by exploiting the voltage Vth, not only is there the difficulty of providing the external components and external connection pins (external connec-tion terminals) necessary for adjusting the reference voltage, but also additional labor is required to carry out the adjust~ent after the fabrication of the IC.
The lower voltage limit of the Zener voltage Vz is about 3 V, and it is impossible to generate a reference voltage to be used in a low voltage range of 1 to 3 V or so. When using the Zener voltage or the forward drop voltage of a diode as a reference voltage, a current of the order of several mA to several tens of mA needs to be caused to flow, which is inappropriate from the point of view of lowering the power dissipation of the reference voltage generator device.
It is apparent from the above explanation, that the S conventional reference voltage generator devices exploiting the voltages Vth, VF and Vz have not always been suited to all the uses when the temperature characteristics, the dispersions or deviations in manufacture, the power dissipation, the voltage leve] etc.
are taken into account. For uses requiring very severe characteristics, it has often been the case that the practical use or the mass production must be relinquished.
The inventors of this invention have thus appreciated that improvements in the conventional reference voltage generator devices are subject to physical limitations and carried out research in order to develop a reference voltage generator device based on a new idea or concept.
To this end the invention consists of a method of manufacturing a semiconductor device with at least a pair of insulated gate field-effect transistors having semiconductor gate electrodes of different conductivity type, comprising the steps of: prepariny a semiconductor substrate having a semiconductor region of a first conductivity type extending to a major surface of said ~5 semiconductor substrate; forming an insulating film over said major surface at a first portion of said semi-conductor region and at a second portion of said semi-conductor region, and forming a semiconductor layer of a first conductivity type over said insulating film over-~0 lying said first and second portions of the semiconductorregion; removing said semiconductor layer to form first ~5~3 and second semiconductor gate electrodes at said first and second portions of the semiconductor region respectively;
selectively forming a mask over said first semiconductor gate electrode except for said second semiconductor gate electrode; and selectively introducing an impurity of a second conductivity type different from said first conductivity type and opposite to the conductivity type of said semiconductor region into said first and second portions of the semiconductor region using said mask, to form source and drain semiconductor regions of the second conductivity type on opposite sides of each of said first and second gate electrodes, and to convert the first conductivity type of said second semiconductor gate electrode to the second type as well as to convert the first conductivity type of the periphery positions of said first semiconductor gate electrode to the second conductivity type.
Various preferred embodiments of this invention to be described later and of inventions disclosed herein and 2Q claimed in the parent application referred to above and other divisional applications filed simultaneously herewith have the following advantages:
(1) ~ reference voltage generator device having small temperature variations can be provided.
~5 (2) There can be provided a reference voltage generator device in which the fluctuations of the voltage value to be obtained are small with respect to the fluctuations in manufacturing conditions, for example, the manufacturing dispersions (deviations) among various lots are ~uite 3Q small.
- 5a -~4S~3 (3) There can be provided a reference voltage generator device in the form of an integrated circuit which can diminish the manufacturing dispersions to such an extent that no adjustment after manufacture is necessary.
(4) There can be provided an electronic circuit device in the form of an integrated circuit including a reference voltage generator device which can be manufactured with a large tolerance relative to a specification aimed at.
(S) There can be provided an electronic circuit device in the form of an integrated circuit including a reference voltage generator device which has a high manufacturing yield, i.e. a high efficiency percentage.
(6) A rèference voltage generator device which is suited to an IGFET integrated circuit can be provided.
~7) A reference voltage generator device and a voltage comparator which are of low power dissipation can be provided.
~8) There can be provided a reference voltage generator device which can produce a low voltage (of or below 1.1 V) of very good precision.
(9) There can be provided a reference voltage generator device which is suited to a power source of a comparatively low voltage (approximately 1 to 3 V), for example, a silver oxide battery of 1.5 V or a mercury battery of 1.3 V.
(10) It is possible to provide a reference voltage generator device which is suited to a semiconductor integrated circuit.
(11) It is possible to provide a voltage comparator 4~
~ a stabilized power supply device, a constant-current circuit and a battery checker which have high precision.
(12) It is possible to provide a semiconductor integrated circuit device for an electronic timepiece which contains a battery checker of high precision therein and which has a small number of external terminals.
(13) It is possible to provide an IGFET integrated circuit in wliich the threshold voltage of an IGEET with a back bias applied thereto can be maintained at a substan-tially constant voltage independent of dispersions in manufacture and changes in temperature, whereby the yield of manufacture can be enhanced.
(14) It is possible to provide a reference voltage generator device whicn is compatible with a complementary type insulated gate field-effect transistor integrated circuit (CMOS IC) or with an N-channel MOSIC or P-channel MOSIC, and a method of manufacturing the same.
(15) It is possible to provide a constant-voltage output circuit which is suitable for making the power dissipation low. That is, there can be provided a constant-voltage output circuit which produces a stabilized voltage with a low absolute supply voltage, such as the battery voltage, and which has a low power dissipation.
(16) It is possible to provide a reference voltage generator device which is compatible with the so-called silicon gate insulated-gate field-effect transistor integrated circuit employing siJicon for the gate electrodes, and a method of manufacturing the same.
(17) There can be provided a method of manufacturing a reference voltage generator device without increasing the number of fabricating steps in the fabrication of a silicon gate P-channel IGFET integrated circuit.
(18) There can be provided a reference voltage generator c;rcuit which e~ploits the difference of the Fermi levels of aluminum and intrinsic silicon, which does not employ P-type silicon containing a P-type impurity, such as boron, liable to be introduced into a channel portion through a gate insulating film and which undergoes small dispersions in manufacture.
(19) It is possible to provide a method of manufac-turing a reference voltage generator device which can prevent an acceptor impurity forming a P-type silicon gate such as B, A~ and Ga from being introduced into a channel portion through a gate oxide film to change the threshold voltage of an IGFET whose gate electrode is made of the P-type silicon.
(20) It is possible to provide a semiconductor memory which has the function of preventing any erroneous writing in a data retention mode. That is, when a supply voltage ~0 has become below a set detection voltage, at least one of control signals required for a writing operation can be inhibited.
(21) It is possible to provide a Schmitt trigger circuit which is constructed of MISFETs (insulated gate field-effect transistors) and whose hysteresis curves have a width which varies little due to the fluctuations of a supply voltage, the manufacture dispersions of the MISFETs, the changes of the temperature, etc.
This invention has been made by going back to the starting point of the physics of semiconductors and taking special notice of the energy gap Eg~ the Fermi level Ef, etc.
It is well known that semiconductors have energy gaps Eg and various levels such as donor, acceptor and Fermi levels. However, until now there have been no proposals to produce a reference voltage generator device utilizing the physics of semiconductors, especially the energy gap Eg and the Fermi level Ef, despite remarkable develop-ments achievèd in extensive fields since the discovery of semiconductors.
Based upon actual results, the inventors thought of utilizing the energy gap Eg, the Fermi level Ef, etc.
for reference voltage sources and have succeeded in this realization. It is not difficult in theory to use the energy gap Eg~ the Fermi level Ef, etc. for reference voltage sources, and the results will be readily under-stood. However, the success achieved by the inventors is believed to be unprecedented, particularly from the point of view that the inventors have gone back to the starting point of the material properties of semiconductors, bearing in mind that the history of the semiconductor industry is no longer short. This development is therefore believed to be creative and epochal, and is expected to contribute greatly to further advancements of electronic circuits and the semiconductor industry in the future.
According to the invention there is provided a reference voltage generator device comprising means for detecting à voltage substantially equal to or smaller than an energy gap of a semiconductor or a voltage based on an energy level of a semiconductor, a voltage based on the detected voltage being used as a reference voltage.
According to a preferred embodiment of this invention, two IGFETs which have silicon gate electrodes of conduc-tivity types opposite to each other are fabricated within a silicon monolithic semiconductor integrated circuit chip. Since these FETs are manufactured under substan-tially the same conditions except for the conductivity types of the gate electrodes, the difference of the threshold voltages Vth of both the FETs becomes approximately equal to the difference of the Fermi levels of P-type silicon and ~I-type silicon. The gate electrodes are doped with respective impurities in the vicinities of the saturation densit-ies, and the difference becomes approximately equal to the energy gap Eg of silicon tabout 1.1 V), which is utilized as a reference voltage source.
Since the reference voltage generator device based on such a construction has low temperature-dependency and small manufacture deviations, it can be used as a reference voltage generator device in various electronic circuits.
The invention, and in particular the preferred embodiments thereof, are discussed in detail in the following with reference to the accompanying drawings, in which:-Figure 1 is a diagram showing the band gaps Eg of GaAs, Si and Ge and their temperature-dependencies;
Figures 2(a) to 2(d) are diagrams showing the band structures and Fermi levels Ef of semiconductors, in which Flgures 2(a) and 2(b) illustrate an example of an N-type semiconductor and Figures 2(c) and 2(d) illus-trate an example of a P-type semiconductor;
Figure 3, which appears on the same sheet as Fig. 1, ~S~;3 is a diagram showing the temperature characteristics oE
the Fermi levels of N-type and P-type Si with the impurity densities being a parameter;
Figures 4(a), 4(h) and 4(c) are diagrams showing the distributions of energy levels possessed by Ge, Si and GaAs semiconductors and various donor and acceptor impurities, respectively;
Figures 5`(a) and 5(b) are diagrams showing the energy state and the states of charges of a P+-type semiconductor -insulator - N-type semiconductor structure respectively, while Figures 5(c) and 5(d) are diagrams showing the energy state and the states of charges of an N+-type semiconductor -~ ~ ~ S~ ~ 3 lnsulator - N-type semlconductor stru ture respectively;
Figures 6(a) and 6(b) are a characteri~t~c dlagram and a circult dlagram of a MOS diode circul~ for derlvlng the dlfference of Vth of two F~Ts having unequal thresho`d voltages Yth respectively;
~igure 7 is a characteri~tic diagram showing ~i~é
situation in which a threshold voltage is ~hanged by ion implantation .-Figures 8 and 9 are diagrams each showin~ an exam?le of a reference voltage generator circuit which explolts the difference of threshold voltages Vth, ~igure lO(a) ls a circuit dia~ram of a reference voltage gene~tor cir~^ult showlng an embodi~nt of thls inventlon, whlle Flgure lO(b) ls an operatlng wavefor~ diP~ram of the circuit ln ~ure lO(a);
Figure ll(a~ shows a furth~r exam?le o 8 reference voltage generator circult, whlle ~igure ll(b) shows timing slgnal waveform~ thereo~; ~
~igure 12 shows a referenc~ Yoltage generator clrcuit which 1~ ba3ed o~ another embodiment;
~igure 13 ~hows an op~rational ampllfler circuit whlch ha~ an offset voltage in accordance wlth thi3 inYention;
Figure 14 ~how~ a re~erence Yoltage generator circult whlch u~ilize~ the operational ampliflar circult of Figure 13;
a5 Flgure~ 15, 16 and 17 show reference voltage generat.or circults which utilize operational amplir~er circuits accor~-lng to other embodiment.~;
~igures 1~ and 1~ ~how volta~e deteGtcr oircults each of which employa a re$'e~ence vol~a~e produced fro~ the 3Q reference volta3e ge~erator circult a¢cordlng to thi in~en~on, - 12 ~
~ 3 Flgure 20 shows a ~oltage detector clrcult which utilizes an o,oeratlonal a~plifier clrcul~ havln~ an offset voltage ln accordance wlth th'~ inventlont ~i.3ure 21 shows a ~Joltage comoarator whlch is for~.ed ~y connecting MOSFETs of unequ~l thres~.old voltages ~h in the dlfferent~al type in accordance witn this invent1 on;
Fizu.e 22 3hows a differential a~Qplifier clrcult whlch employs ilOSF~s of unequal threshold voltages Yth ln accordar.ce with thls inventlon;
~l~ure 23 shows the drain current - ~ersus - ~ate volta~e characteristlcs of the diff~rentlal pair ~OS tra~sistors of the differentlal am?lifier circult show~ ~n Fl~ure ~2;
~igure 24 shows an offse. ~ype vo'tage cG~oarator clrcuit whlch is const~u¢ted of a voltage eo~?aratGr clrcult and source follower circults employlng two MCSF~Ts of threshold ~olta2es dlf~erent fro~ each other in accordan~e wlth thls invention Figure 25 shows an offset type voltage ~o~parator circuit whlch is constructed of a voltage comparator clrcuit ~0 and ~rounded-source clrcuits e~ploying two S~IOS~ETs of threshold voltages dlfferent from each other in accordance with th's lnvention;
Figure 26 showe an example of a co~stant-current clrcult whlch is used in the offset type voltage comparator clrcult o~ Figure 24;
Flgure 27 show3 a refere~ce Yoltage ~en~rator sircuit which employs the differentlal amplifier clrcuit ~hown ln Fi~ure 22 Fl~u~e 28 shows the detalls of tne off~e~ typ~ ~oltage 3 0 co~parato, circuit ~hown ln Fi~ure 24, and lllustrates a case ~5~3 in which a reference voltage generator circuit is constructed by employing this voltage comparator circuit.
~igurQ 29 shows a constant-currel~t circuit whlch exploits the di~ference o~ the th~eshold volta~es of ~o S MOS~Ts in accordance wlth this lnvention~
Fi~ure 30 shows a constant-current circuit ~o whicn is applled a reference ~oltage generator ci.cuit that produces a reference ~oltage on the basis of the ~lfference of tne threshold voltages of two ~iO~_Ts in accord~nce with thls inv~ntion, ~igure 31 shows a constant-current circuit i~ w~ich a current mirror circult is added to t~e ca~sta~t-current ~-ircult shown in FiOure 30;
~igures 3~ and 33 are circuit ~ r~s e2ch ~howinO
a stablllzed power sup~ly circult to whi¢~ is applied a reference volta~e generato, clrcuit that produces a reference volta3e based on the dl~ference of the threshold Yolta~es of ~tOS~Ts in accordance wlth thi~ invention, ~igure 34 shows a ~tabillzed power supply ~ircult to which is applled an operatlonal ampllfier that ha~ the difference of the threshold volt2ges of MOSF3Ts as 1~ off~
set voltage in accordance with this lnventlon, Fi~ure 35(a) is a circuit diagram for explaining an exa~ple of a voltage regulator to whlch an off~et type a s operational amplifier cireuit accordlng to thi3 invention ls applied, while ~l~ure 35(b) 1~ a~ electr~cal char~cterlstic diagram for explalning the operatlon of the voltage re~ulator, ~igure 36(a) ls a ~ircu1t dlagram for explaln~n5 a ~oltage regulator accord~n6 to another emoodlment o~ tnl3 ln ention, 3 O while ~ure 36(b) is an electri¢al ¢haracteristlc diagra~
SI~i3 for explaining the operation of the volta2e regulator;
r igure 37 is a circuit diagram showing an example ln the case in which this invention is applied to a battery life~iQe detector circuit;
Figure 38 i~ a diagram o~c~ circuit for a clocX-drlven battery checker accordin~ to another embodi.~ent, ~igure 39 is a diagra~ of a reference voltage generator circuit whos-e"'reference voltage can be flnely adJusted w1th a resistor outside an IC, l~ Figure 40(a) shows a Schmit~ trlgger circult to ~hich the princlple o'f thi~ in~entlon is applied, while Figure 40(b) shows the hysteresis charac~eris~ic of the Schmitt trigger clrcuit, Figure 41 shows ~ Schmitt trlgger circuit according to another embodlment, Figure~ 42 and 43 are diagra~s each showing an oscillator circult to which the Schmltt trig~er clrcult ac~ordin~ to this invention is applied, ~igure 44 3hows a differen~lal ampllfler whlch e~ploys a o MOSFETs Figure 45 shows a TTL - MOS signal level shifter clrcult according to this inventio~;
~igure 46 shows a logiG threshold stabllizer circult according to thlx invention a 5 Figure 47 shows a substrate bia~ senerator circuit according to thl~ lnvention;
~igure 48 ~how~ a status settlng ¢lrcult accordlng to this invention r i~ure 49 3h~w~ a ~tatus settlng ~ircuit ~,~hlch has hitherto beer. proposed;
~ ~ ~ 5~ ~ 3 Flgure 50 shows a MOS memory which employs the substr2te bi~s generator circuit shown i~ Fi~ure 47;
~igure 51 shows a memory cell in the ~IOS memory o~' ~igure 50, ~lgure 52 ~hows a sem$conductor random acce~s memory accord~ng to thlq lnvention;
Fl~ure 53(a) ~hows a voltage detector circuit which ls used i~ the semiconductor ra~dom acce~s me~ory ac~ordln~ to thi~ invent-i-on, wh~le ~igure 53(b) shows the operatlng ~ave-forms of the ~oltage detector circuit~
Flgure 54 shows an electronic timeplece to whlch ~he battery checXer shown ~n ~igure 20 ls applled;
Flgure 55 shows an electronic timep~ece to ~h~ch a similar battery checker 15 applled;
Fl~ure 5~ shows an electro~ic timepiece to wh~ch the ~oltage re~ulator as shown in ~igure 36(a);
~lgure 57 shows an elec.roric ti~epiece to which a siQllar volt~ge regul2tor is applled;
Figure 58, wh~ch appears on the same sheet as Fig. 61, is a structural sectional view of two MOSFETs which have threshold voltages different from ea¢h other in accordan~e with this invention;
~i2ure 59 schematically show sectlonal structures of p~ gate and N+ gate ~IOSFETs usable ror derlving the dlfference L5 (Ern - Efp) of the ~ermi level3 of N-type and 2 type se~i-conductors, in which the left hal~ shows a P-channel F~T
whlle the ri8ht half shows an N-channel ?ET
~i~ure 60 also scheQatic211y shows ~ectlonal s-ructures of p+ gate and ~ ~ate MOS~-~Ts usable ~or deriving the dif'erenCe (Et~n ~ Erp) 0l the ~ermi leYels of N~type ~nd P-type sem~conduct~rs, in which ~he left hal~ sho~s a ~5~3 P-channel Fr.T while the rlght half show_ an ~-channel ~T
Flgure 61 si~ilarly shows a structure of two P-channel ~OSFETs whlch have threshold volta~es different from eac~
other;
`~ ~ Flgures 62 and 63 are sectional views each showln~ ~he essential portion~ of MOSFET wh~ch are required for the constructlon of thls invention and whlch ha~e ~ate electrodes of different ~ermi levels Figure 64 ls a sectlonal vlew of the essential portions l~ o~ ~SOS-r~.Ts whlch constltute a reference volta~e ~enerator devlce according to thls lnvention;
Flgureq 65(a) and 65(b) are plan view an~ a ~ectional vl~w o~ an ~+ gate P-channel ~3~ET respecti~ely the sectlon21 views being ta'~en along lines indlcated by arrows Ln the l5 .- correspondlng plan vlews;
Flgures 66(a) and 66(b) are a plan vlew and a sectional ~lew of a P~ gate ?-channel ~tOSF~T, respect~vely;
~lgur~67~a) and 67(b) show a plan vlew and a sectlonal vie~ of a P~ gate P-channel M03FET, respectlvely, ~0 Flgure3 68( A) and 68~b~ show a plan view and a sectlonal vlew of an i ~ate P-channel MQS~T, respecti~ely;
Flgures 69(a) and 69tb) show a plan view a~d a section21 vlew o~ an ~1~ gate P-channel MOS~ET, respecti~ely, Figures 70(a) and 70(b) how a plan vlew and a se¢tional ~5 view of an N~ gate N-channel MOSFET, re~pectlvely;
Figures n (a) and n (b) qhow a plan vlew and a sectlonal view of an i gate ~-channel MOS~T, respect~Yely;
Fi~ures 72(a) and 72(b) ~how a plan view and a sectional Yiew of a P+ gate N-ch~nnel MCS~5., respectively Figures 7~(a) to ?3~) illustr~te that ;~ ~ate (~ar. B3 ~ ~ ~ 5~ ~ 3 and P+ ga~e (part A) P-cha~nel MOS~ET~ are fabricated together with a P-channel ~ET (part C) and an N-channel FET (part D) which const~tute a conventlonal co~ple~entary ;.OS device;
~lgures 74taj to 74~d), ~lgures ?5ta) to 75~d), ~i~ures 76(a) to 76(d) and Figures 77(a) to 77td) show sectional ~iew l.n the prlncipal steps in .he case o~ ~anufac-turln3 two MOS?ET~ according to this invention .o~ether w'th a co~plementary ~OS device, respectively, Flgures 7~(a) ~o ?8(e) ~how secti~nal views ~n the various step~ of manuf'acture in the Gase Or ~-¢hannel MOa~ Ts;
~i~ure~ 79(a) to 79(e), Figure~ ~O(a) ~o ~Q~d) 2nd F~gures 81(a) to 81(d) a~e sectional v-iews in vari~us steps for explainlng a method o manufacturLng ilOSF~T~ ~or use in a re~erence voltage generator circult devlce accord'ng to this invention, respectlvely, and Figures 82(a) and 82(b) and Figure~ 83(a~ to 83(d) show sectional ~lews ln Yar~ ou3 ~tep~ f~r ex~laining another method of manufacturin.~ MOSFETs ~or use in a reference ~O ~oltage genera~or clrcuit device a¢cordln~ to thls invention, respectively.
The physics of semiconductors which begins with the crystalline structure of a semicondu~tor and which develops into the energy band o~ a semicondu~tor and phenomena brought about by donor and acceptor impurities are well explained in the literature.
It ~s, of course, well ~nown th2t semiconductor~ Or dlfferer.t composit~ons ha~e energy ~aps ~g Lnherent thereto and that the energy gap ~g exp~essed in eV has the dimension ~0 ~5~3 of a voltage. As previously stated, however, there has never been any suggestion of using the energy gap Eg as a reference voltage source based on the fact that the energy gap Eg exhibits a low temperature-dependency.
The present invention has been made by starting from the fundamentals of the physics of semiconductors. There-fore, the detailed description of this invention will be commenced by briefly referring to the pertinent points of the physics of semiconductors. Since the material pro-perties of semiconductors are explained in extensivedetail in many publications, reference will be made to one such publication, namely "Physics of Semiconductor Devices" by S. M. SZE, published by John Wiley & Sons in 1969, especially Chapter 2 "Physics and Properties of Semiconductors" on pp. 11 - 65.
Application of Energy Gap E
g Semiconductors have a variety of compositions. The semiconductors typically utilized industrially at present are non-compound semiconductors of germanium (Ge) or silicon (Si), and gallium-arsenic (GaAs) compound semi-conductors. The relationship between the energy gaps Eg of these semiconductors and temperature are explained on page 24 of the publication referred to above, and is reprinted in Figure 1.
As seen from Figure 1, the energy gaps Eg of Ge, Si and GaAs are 0.80 (eV), 1.12 (eV) and 1.43 (eV~, respec-tively, at normal temperature (300 K). Their temperature-dependencies are 0.39 (meV/K), 0.24 (meV/K) and 0.43 (meV/K), respectively. By deriving voltages of values equivalen~ to or close to the energy gaps E, accordingly, reference voltage generator devices can be obtained which -- 1~ --~ ~5~
have temperature-dependencies one order smaller than those of the forward voltage drop VF of a PN-junction diode and the threshold voltage Vth of an IGFET as stated previously. Furthermore, the voltage to be obtained is determined by the energy gap Eg inherent to the semi-conductor. With, for example, Si, it is about 1.12 tV) at normal temperature substantially independently of other factors. It is possible to obtain a reference voltage which is not affected by dispersions in the manufacturing conditions etc.
An example will now be explained as to the principle upon which the voltage corresponding to the energy gap Eg of the semiconductor can be derived.
Application of Difference of Fermi Levels (Work Functions) of N-type, i-type and P-type Semiconductors The conditions of energy levels when doping semi-conductors with donor and acceptor impurities are well known. Especially noteworthy to this invention is the phenomenon that the energy levels at which the Fermi energies of N~type and P-type semiconductors are located are separated towards a conduction band and towards a valence band with respect to the Fermi energy level Ei o~ an intrinsic semiconductor. The energy levels become more distant from the Fermi level Ei of the intrinsic semi-conductor as the densities of the acceptor and donor impurities increases, the Fermi level Efp of the P-type semiconductor comes close to the top Ev of the valence band, while the Fermi level Efn of the N-type semi-conductor comes close to the bottom Ec of the conduction band. Accordingly, when ~5~3 the di~ference (Efn ~ E~p) of.both the ~ermi levels i~ ta'~en, the energy level di~ference is substantially approximate to the ener~y gap ~ po~sessed by the semiconductor and it~
te~perature-depe~dency is also approx$mate to that of the energy gap Eg. The sPme applle~ to the dif~ere~ces tEfn ~ ~1) and (~1 - rfp) between the ~erml level-~ o~ ~he P-t~pe se.~
conductor and the intrin31c semlconductor a~d bet-~een the ~er~i levels of the N-type semlconductor and the intrinsic ~emlconductor. In th~s case, however, the a~solute value approaches Eg/2. In the following, the differences relative to the intrinsic semiconductor wilL not be described in detail on the qround that they become one half of the diference oet~een t~e P-t~e and the ~-type. ~s ~ill be stated ln detail later, the higher the impurity concentratlon, the lS lower ~he ~emperature-dependency of (Efn ~ Efp). In order to attain a 2reat energy level dlfferenGe approxlm2te to the energy ga~ Eg and to atta~n a low tempera~ure_depe~dency thereof, accordingly, it 15 ~a~orable to establish an impurlt-~
density a~ close to the ~aturation denslty as possible.
a~ The Fermi levels Efn and Efp concern not only the density o~ the donor or acceptor impurity but also ~nor or acceptor levels Ed or Eal which differ according to the impurity.
materials. As t~e level Ed or ~a ha~ an energy level nearer to the conductlon ~and or the val~nce band respecti~ely, ~he as Fermi level Efd or ~a comes clo~er theretoO In other words, as the impurity levels Ed a~d ~a of the do~or anA acce~tor have s:~a~lcwer level~, the difference ~f~ - Efp) of the ~erm.~ level~ co~es clo~er to the anergy gap ~z of tbe se~i-conductor.
As the impurity level ~d or E of the donor or acceptor ~ ~ ~ S ~ 3 is closer t the ~ermi level El of the intrlnslc semi-conductor, that ls, as tt ha~ a deeper level, the dlfference (Ef~ - ~fp) of the Fermi level~ becomes more distant from the ~nergy gap Eg o~ the semiconductor. This, however, does S not slgnify that the temperature-de2endenc~ degrade~, but signifies that the absolute value of the d~fference (~fn ~ ~p) of the Fermi levels dimlnishes. Accordingly, the dlfference ( ~ fn ~ ~fp) o~--the ~ermi levels ~r the dlfference of hork functlons is a physical q~antlty lnherent to the semiconductor ma~erial, the impurity materials, etc. ~rom another vlewpolnt, it can become a reference voltage source parailel or sl~llar to the energy gap Eg of the semiconductor. That 15, the difference (Efn - E~p) of the Fermi levels ~ se can be-come a reference voltage source whlch i5 lower in temperature-1~ dependency and less liable to be affected by the manu~a¢turing conditions than ~he forward Yoltage drop YF of a PN-Junctlon and the threshold voltage Yth of an IGFET. In consequence, the expedient of taking out the difference (Efn - E~p) of the ~erml levels by the use o~ impurity materlals exhiblting a~ donor and acceptor level~ Ed and Ea having shall~w levels c2n become one method for derivlng a Yoltage of a va}ue substantially approximate to the energy gap ~g of the semi~
conductor. n the other hand, as regards the setting of a voltage value to be obtained, when it is desire~ to obtain a~ a comparatively large rererence voltage equiYalent to the.
energy ~ap of the semiconductor, impurities whl~h exhlbit shallow levels may be used, and when it is desired to obtain a comparatively small reference volta~e, impurities which exhibit deep levels may be used.
SPecific Examples of the Selecti_n of Impurity Materials . . .
~ - 22 -~ . .
The relations between the Ferml level ~f and the donor level Ed, acceptor level 3a9 donor denslty Nd, acceptor denslty Na and the temperature T will be described in detail ~ith reference to Figure 2 and ~igure 3. ~rior to this description, the data on page 30 of the aforementioned publication as reprinted in Figure 4 wlll be referred to in order to explain what leveis various impurities present to ~he Ge, Si and GaAs semiconductors and to explain how ~he impurities are utili~ed in this invention.
1~ Figures 4(a), 4~b) and 4~c) are d1agrams ~hlch show the ener~y distrlbutions o~ various impur't1e5 for Ce, S1 and ~a.~s, respectively. The numerals in the respective diagrams lndicate energy dif~erence3 (Ec ~ Ed) ~rom the ~ottom ~c of a conduction band as to leYels located above the center of a ~ap or the ~ermi level o~ an intrinsl¢ 3emiconductor ~i drawn by a broken line, and indlcate ener~y d~f~erences (~a ~ rv) from the to? E~ of a valen¢e ba~d as to leveis located below the gap center E~, the unlt belng (eY) ln both the cases.
a~ Accordingly, an impurity material indicated by a small~
nu~erical value ln each dlagram ls such that lts level ls close to the bottom Ec of the conduction band or the top ~y of the valence band, and it ls appropr~ate as an i~purlt~
for obtalning a voltage close to the energy gap ~g~ By way ~5 of example, for S1 whlch ls used most ~reouently at present, le~el dlfference~ (~c ~ ~d) and (Ea - E~) respectlvely e~hiblted by the dcnor impurities Li, S~, P, As and Bi and the acceptor impuriti~s B, Al and Ga are the smallest, and ~cth ~he level dl~erences are below about ~ f the 3~ energy ~ap F5 of 3i. ~hen a tempe.at~r~ char~e fro~ C c,~c s ~ 3 neglected, the di~ference (E~d - E~a) of ~e ~erml levels of N-~ype Si and Ftype Si employing these lmpuritles becomes about 94 ~ - 97 % of the energy gap ~g o~ Si, whlch value is approximately equal to ~8~ ~ donor impurity and an acceptor Impurity which exhi~lt the smallest level differences (Ec ~ Ed) and (Ea - ~y) next to the above lmpurities are à
(about 16 ~ of ~g) and In (abou~ 14 ~ o~ ~g), re~pectlvely.
T~ differenc.e t~fd ~ fa) of the ~er~i levels of ~t-type Si and P-type Si employlng the respectl~e i~purities ~ecomes about 0.8~ ~g at 0 ~, and the devl~ticn from the energy gap ~g Or Sl is as great as about 15 ,'~. It is accordingly understood that the dev~atlon ls much greater than those of the aforementioned impurities.
Thus, one donor impurity selecte~ from the group con-sl~itin~ of L~, Sb~ P, As and ~1 and one ac¢eptor i~purity selected fro~ t~e group ¢onsistir.g of 3, ~1 and Ca are suitable as the impurity materlals o~ P-~ype and ~ pe ~i for obtaining a voltage sub~tantlally eq~al to the energy gap ~g of Si. The other impurities will ~e ~u~ted to the a~ end of obtaining voltages considerably smaller than the energy gap Eg of Si.
Physics of Fermi Level Er Now, the difference (Efn - Efp) of Fermi leve~s will be explained with reference to Figures 2(a~ to
2(d). These figures are diagrams illustrative of the ener~y levels of ~emiconductors. FigureQ 2(a) and 2(b) ~how the energy level model Or an t~-type 3emiconduct~r and the temperature characteris-1¢ thereo~ respectlvely, whil A
Figures 2(c) and 2~,d) ,show the ene~gy le~el ~odel of & ~-t~e
Figures 2(c) and 2~,d) ,show the ene~gy le~el ~odel of & ~-t~e
3~ se~iconductor and th~ ~emperature characteristlc thereof re~pectively~
Carriers in a qemiconductor cons1st of the sum between electron~ nd created by lo~izat~on of donor lmpurlt1es ~d and electron-hole palrs e~cited ~rom a ~alence band.
't~en the donor impurity dens~ty Nd is sufficiently high, the number of the exclted electron-hole pairs is negllgible, and the ~umber o~ conductlon electron~, n becomes:
n ~-~d ~..................... ,... (~) nd and n are respect~vely evalua.ed from the probab~llty at whlch electrons are trapped by ~he donor level and the number of electrons whlch exist ln a ~onducti~n band, and become:
_~
n ~ N 1 - ~d ~F
d d 1 + exp t ~ ) kT
S
Nd . . 1 Ed ......... ~(2) kT
and n ~ Nc~exp ( Ec) .,,...... (3) ~ere, the effective den~lty of states in the conductlon band, Nc become~:
Nc ~ 2( ~ kT) ~5 where h: Planck'~ constant, m: effective mass of electron, k: ~olt2mann's con~tant, and T: lattlce temperature.
~rom Equations (1), (2) and (3), Nc exp ( F~T ) ~-- e~
1 ~ exp (~
kT
36~
~nd d ~ exp ( ~ ) ~ exp ( ~ ) .................... (5) S Here, since the Fermi level ls supposed to lle at a position proximate to the bottom o~ the conductlon band ~c~
the first term of Equation (5) is negligible, -~o that:
~ / (Ed Ec) 1/2 ~T~n-~ ........................ (6) 1~ This equation (6) ~ignlfie~ the follow~ng. In the case where the impurity concentration denslty Nd ~s high, not only at a low temperature, but al o at normal temperature, NC/Nd approximates.l (o~e) and ~ ~ ~ O, so .hat the Fermi level E~ lies at the intermedlate point between .he bottom 1s - r C of the conduction b~nd and the donor le~el -d and the temperature-dependency becomes substantlally equal to the temperature characteristic of F,c.
However, when the temperature has become sufficiently high, the electron~hcle pairs excited ~rom the valence ao band predominate, the influe~n¢~s Q~ the impurities lessen and ~he Fermi level E~n in the ~I-type semiconductor comes close to the level E~ of the intrinsic semiconductor.
The above relation~hlp 1~ lllustrated ln Figure 2(~)~
Qulte the same applie3 to the case o~ a P-type semiconductor a~s contalning only an acceptor i~purlty as shown in F~gure 2(c~.
When the temperature is low and when the a¢cepto~ lmpurity den-sity is hi~h, the Fermi level EFp in the P-~ype semiconductor lies at a substantially interme~iate position between the top Ev of the valence band the a¢ceptor level Ea. When ~he 3 ~ temperature is raised, the Fermi level EFp ~omes close to the .- 26 -~ ~ ~ 5~ 6 3 Fermi level ~i of the l~tr~nslc ~emlconductor.
The temperature-dependency of the ~er~1 le~el EFp ln the ~-type semiconductor ls lllustrated ln Figure 2(d).
.~elation between Temperature ~haracterlstlc of ~ermi S Level Ef and I~purity Density tSPeCific Example) The relationa between the temperature-dependencle~ of the Fermi levels Efp and Ef~ and the impurlty densities have been expl,ained in terms of physical properties. Now, by taking as a specific example the Si semiconductor, 1~ which is used most frequently in practice at present, the difference of the Fermi levels (Efn - Efp) and its temperature-dependency in practical use will be explained with reference to data on page 37 of the aforementioned publication. The data are reprinted in Figure ~.
I~S ~ In conventlonal processes f~r ~anufa~turlng a ~i semi-conductor integrated circuit, boron (B) and phosphorus (P) are solely used as the impurity materials. Their high impurity den-sities are 102 (atoms/cm3). However, even when the donor and acceptor impurity densities Nd and Na are lol8 lato~s/cm3), which is lower by two orders, the difference (E~n - Efp) of the Ferml levels of the N-type semlconduotor and the ? type semlconductor is 0.5 - (-Q.5) ~ 1.0 (eV) at 300 K as read from Figure 3, and it ~s a value comparativelv clQse to the energy gap Eg ~ 1.1 eY at the ~a~e temper~ture~ The changes a~ of the dlfference versus temperatures are Xrom about 1.04 (eV) to 0.86 (eV) ln a range of ~rom 200 K to 4C0 K (-70 C
to 1~0 C), and th~ ch~glng rate ls ~.9 ~'/C). This ls a qmall ~alue of approxi~ately 1/3 ln ~omp2rlqo~ with 2 to 3 mV/C
of the rates of chanses versu~ temper~tures of the threshold 3~ vol~age Yth cf an IaF~T and t~e forwar~ drop volta~e YF of a ~, - 27 -,... ~
~ ~ ~ 5 ~6 dlode as stated prev~ously.
~en the lmpurity densltle~ are 10~ cm 3 or hlgher, the Ferml level dif~ere~ce becomes substant~ally equal to the sillcon energy g~P (~g)Si ~ 1.1 (V), and the ci~angir.g rate versus temperatures becomes about 0.2 ~Y~C, whlch 1 a sufficiently small value.
Accordln~ly, if the impurity conce~trations are about 1018CQ 3 or hl~her, a temper~ture-depender.¢y whlch ls, at least, reduced to 1/2 - 1/3 of those of the prior art can be attained. ~'.ore preferably, the impur~ty ~oncentratlons are 102cm 3 or hi~her (a redu~tion of about 1/10), and most preferably, they are the saturat~on dens~tles or degenerate denslties.
Prlnci~le of DeriYin Difference of Fermi Levels and . ~
Actual Exam~le Upon what principle ~an the voltage corresponding to the dlfference of the Fermi level3 (Efn ~ Efp)D (E~n ~ El) be taken out? ~n example is to util~ze the dl~Lerence o~
the threshold voltages Yth of two MOSFETs o~ channels of a o the same conductiYity type which ha-re se~i~o~ductor gate electrodes that are formed on gate ~nsula~ing fil~s for~ed under -~ubstantially the sa~e condltion~ on dlfferent surface areas of an identical semiconductor body and that are made of materials being of an ldentlcal ~e~i¢on~uGtor s~s~ance (for example, sllicon) ~ut havlng different conducti~lty ~ypes. A specific example of this will now be described.
Each of ~igures 59 and 60 depicts the conceptual sectlonal structures o~ the respecti~e F~T~ formed within a ¢om~lemer.tary MOS integrated circuit ~CMOSI~). Hereinafter, for the ~aXe 3~ o~ brevit;, the MOS tran~lstor whose gate electrode is made ~ ~5~3 of a P~-type semiconductor shall be called the "?~ gate MOS", ~he MOS tran-~i~tor whose gate electrode 1~ made of ~n N+-type semiconductor shall be called the "N~ gate MOS", and the ~IOS
transl~tor whose gate electrode ls made of a~ lntrinsic or i-type ~emlconductor ~hall be called the ~i zate ~IOS". In Figure 60, the left half shows P~, i and N+ gate P-ckannel .'tOS transistor~, while the right half shows P~, 1, and N' gate N-channsl- MOS transi tor~. ' The differences of threshold voltages a~ong the ~'OSFETs 1 tQl) - (Q3) and (Q4) ~ (Q6) in Flgure 60 is as in the following t~ble:
Table ~Unit: volt~
i Ql Q2 Q3 Q4 a5 ~6 5 . . -~ . _ ~ __________ l `~ 0.55 1.1 _ ~ _ _ Q2 .55 " ~ 0.55 _ _ _ Q3 1,1 0.55 .. ~ _ _ ~ .. _ . . _.~ ~ .. .. ,, _ . _ ._ Q4 _ _ _ ~ 0.55 1.1 . . - . . .. . . ~ . - .. .. _ 2 ~ Q _ _ . ~ 0.55 `~ \ 0.55 .~- v . ~_ - ___ - -- ~-- .
~6_ _ _ 1.1 0.55 \
As wlll be de~cribed ln detail later, Figures 73(a) S to 73(f) illu~trate sectional v~ews of prlncipal steps w~lch show that the P+ gate MOS and the N~ yate MOS can be fabricated without altering or adding to any of the steps of a conventional process for manufacturing a comple-mentary MOS integrated circuit (CMOS IC).
3 ~ Flgures 65(a) and 65(b) or ~i~ures 6~a) and 66(~) S~t~3 depict a plan view and sect.ional s~ructural vlew of N
gate or P~ gate P-c~a~nel MOS transi~tors to be aotually used in clrcult structures, respectively.
Referring to Figures 65(a) and 55(b) or ~i~ures 66(a) and 66(b), ln order ~o form a self-alignment structure, a P-type impuri~y i~ dlffused in both tho.~e end parts ~S and r~ of the gate electrode G ~orme~ of a~ 1 ty~e or 1~trinsic ~emlconductor~which are close to a sourGe (S) and a drain (3), for both the P+ ~ate MOS and the N~ gate ~ S because the I O ~OS transistor is of the P-channel ln this ~ase. In 2 central part Cp of the gate eleGtrode G, a P-type impurlty is diffused for the P+ gate ~.OS, and an N-type impuri~y ls di~fused for the ;Y~ ~ate MOS. A region l~in which no i~purity is dlfL~sed~
ls provided between the central re~Gn and bo~h ~:qe end par~s IS ES and ~D close to the source and the dra1n. It is thus considered that the point of difference between the ?~ gate MOS and the N+ gate ~IOS is only whether the region of the central region part Cp o~ ~he gate is of the ?-type semiconductor or the N-type se~conductor.
ao In Figures 65(a) and 65(b) or ~lgure~ 66~a) and 66(b), numeral 101 designates an N slllcQn substrate, numeral 108 a P+ source region~ numeral 113 a P drain reslon, numeral 105 a gate oxide film, numeral 104 a thlcX fleld oxlde film, and numeral 111 another oxide film. As can be understood from Figure 65(a) or Figure 66(a), a plurality of P~ source regions 108 are electrically connected in common with one another by an lnterconnectlon layer 114, a plurallty of P+ drain regiors 113 are electrically co~necte~ ln com~on wi~h e~h other by an lnterconne¢tion layer ~12, snd a ~luralit~ of 3~ gate electrodes C.are electrically connected l~ ~ommon with ~5~3 one another by an interconnection layer 115.
Further, in order to reduce as much as possible varlation of the effect~e channel lengths o~ the MOS
tra~slqtors attrlbuted to the ~'a~t that ~he :~-type impurlty di~fus~d reglons at both the end parts CS and ED ~ the gate electrodes ~ formed for the self-aligr.ment may shift onto eLther the lef~ or right side (source side or d~ln side) during manufaCture on account of the error of mask alignment, the columns of the source region~ and the dr~ln resions are l~ alterrlatQly arranged, and the columns are arranged so that the left hal~ and the r~ght hal~ m?.y be put into line symmetry with re~pect to the channel dlrection as a wnole.
Accordin~ly, even wh~n the sh1ftlng 5~ the ~25~. align~ent wlth respect to the chanr.ei direction ~lef.w~rd or ri~.t~;ard shlfting) changeq the effective channel len~ths ~f tne ?~Ts in the respectlYe columns, ~he average effective charnel lengths of the P+ gate ~IOS and the N~ gate MOS in the respec-ti~e columns connec~ed 1~ parallel ~.a~e the chan~e~ cancelled as a whole and become ~ubstantlally constant.
Flgures 73(a) to 73(f) lllustrate how the P~ gate MOS and ~he N~ gate MO~ are constructed ~y the use of the conventional manufacturing process for a silicon gate C~CS IC.
In ~igure 73ta), ~umeral lOl designates an N-type sllicon ~emico~ductor having a specific re~i~ta~ce of 1 ~ c~
2S to 8Qcm, on which a thermal oxidation film 102 i5 grown to about 4,000 A to 16,000 A. A window for selective diffusion is provided in the film by a photoet¢hing technique. Boron, to serve as a P-type impurity, is ion-implanted in a quantity f approximately loll to lol3 cm-2 at an e 50 KeV to 200 KeV, whereupon it is thermally diffused for ~ - 31 ., ~
Carriers in a qemiconductor cons1st of the sum between electron~ nd created by lo~izat~on of donor lmpurlt1es ~d and electron-hole palrs e~cited ~rom a ~alence band.
't~en the donor impurity dens~ty Nd is sufficiently high, the number of the exclted electron-hole pairs is negllgible, and the ~umber o~ conductlon electron~, n becomes:
n ~-~d ~..................... ,... (~) nd and n are respect~vely evalua.ed from the probab~llty at whlch electrons are trapped by ~he donor level and the number of electrons whlch exist ln a ~onducti~n band, and become:
_~
n ~ N 1 - ~d ~F
d d 1 + exp t ~ ) kT
S
Nd . . 1 Ed ......... ~(2) kT
and n ~ Nc~exp ( Ec) .,,...... (3) ~ere, the effective den~lty of states in the conductlon band, Nc become~:
Nc ~ 2( ~ kT) ~5 where h: Planck'~ constant, m: effective mass of electron, k: ~olt2mann's con~tant, and T: lattlce temperature.
~rom Equations (1), (2) and (3), Nc exp ( F~T ) ~-- e~
1 ~ exp (~
kT
36~
~nd d ~ exp ( ~ ) ~ exp ( ~ ) .................... (5) S Here, since the Fermi level ls supposed to lle at a position proximate to the bottom o~ the conductlon band ~c~
the first term of Equation (5) is negligible, -~o that:
~ / (Ed Ec) 1/2 ~T~n-~ ........................ (6) 1~ This equation (6) ~ignlfie~ the follow~ng. In the case where the impurity concentration denslty Nd ~s high, not only at a low temperature, but al o at normal temperature, NC/Nd approximates.l (o~e) and ~ ~ ~ O, so .hat the Fermi level E~ lies at the intermedlate point between .he bottom 1s - r C of the conduction b~nd and the donor le~el -d and the temperature-dependency becomes substantlally equal to the temperature characteristic of F,c.
However, when the temperature has become sufficiently high, the electron~hcle pairs excited ~rom the valence ao band predominate, the influe~n¢~s Q~ the impurities lessen and ~he Fermi level E~n in the ~I-type semiconductor comes close to the level E~ of the intrinsic semiconductor.
The above relation~hlp 1~ lllustrated ln Figure 2(~)~
Qulte the same applie3 to the case o~ a P-type semiconductor a~s contalning only an acceptor i~purlty as shown in F~gure 2(c~.
When the temperature is low and when the a¢cepto~ lmpurity den-sity is hi~h, the Fermi level EFp in the P-~ype semiconductor lies at a substantially interme~iate position between the top Ev of the valence band the a¢ceptor level Ea. When ~he 3 ~ temperature is raised, the Fermi level EFp ~omes close to the .- 26 -~ ~ ~ 5~ 6 3 Fermi level ~i of the l~tr~nslc ~emlconductor.
The temperature-dependency of the ~er~1 le~el EFp ln the ~-type semiconductor ls lllustrated ln Figure 2(d).
.~elation between Temperature ~haracterlstlc of ~ermi S Level Ef and I~purity Density tSPeCific Example) The relationa between the temperature-dependencle~ of the Fermi levels Efp and Ef~ and the impurlty densities have been expl,ained in terms of physical properties. Now, by taking as a specific example the Si semiconductor, 1~ which is used most frequently in practice at present, the difference of the Fermi levels (Efn - Efp) and its temperature-dependency in practical use will be explained with reference to data on page 37 of the aforementioned publication. The data are reprinted in Figure ~.
I~S ~ In conventlonal processes f~r ~anufa~turlng a ~i semi-conductor integrated circuit, boron (B) and phosphorus (P) are solely used as the impurity materials. Their high impurity den-sities are 102 (atoms/cm3). However, even when the donor and acceptor impurity densities Nd and Na are lol8 lato~s/cm3), which is lower by two orders, the difference (E~n - Efp) of the Ferml levels of the N-type semlconduotor and the ? type semlconductor is 0.5 - (-Q.5) ~ 1.0 (eV) at 300 K as read from Figure 3, and it ~s a value comparativelv clQse to the energy gap Eg ~ 1.1 eY at the ~a~e temper~ture~ The changes a~ of the dlfference versus temperatures are Xrom about 1.04 (eV) to 0.86 (eV) ln a range of ~rom 200 K to 4C0 K (-70 C
to 1~0 C), and th~ ch~glng rate ls ~.9 ~'/C). This ls a qmall ~alue of approxi~ately 1/3 ln ~omp2rlqo~ with 2 to 3 mV/C
of the rates of chanses versu~ temper~tures of the threshold 3~ vol~age Yth cf an IaF~T and t~e forwar~ drop volta~e YF of a ~, - 27 -,... ~
~ ~ ~ 5 ~6 dlode as stated prev~ously.
~en the lmpurity densltle~ are 10~ cm 3 or hlgher, the Ferml level dif~ere~ce becomes substant~ally equal to the sillcon energy g~P (~g)Si ~ 1.1 (V), and the ci~angir.g rate versus temperatures becomes about 0.2 ~Y~C, whlch 1 a sufficiently small value.
Accordln~ly, if the impurity conce~trations are about 1018CQ 3 or hl~her, a temper~ture-depender.¢y whlch ls, at least, reduced to 1/2 - 1/3 of those of the prior art can be attained. ~'.ore preferably, the impur~ty ~oncentratlons are 102cm 3 or hi~her (a redu~tion of about 1/10), and most preferably, they are the saturat~on dens~tles or degenerate denslties.
Prlnci~le of DeriYin Difference of Fermi Levels and . ~
Actual Exam~le Upon what principle ~an the voltage corresponding to the dlfference of the Fermi level3 (Efn ~ Efp)D (E~n ~ El) be taken out? ~n example is to util~ze the dl~Lerence o~
the threshold voltages Yth of two MOSFETs o~ channels of a o the same conductiYity type which ha-re se~i~o~ductor gate electrodes that are formed on gate ~nsula~ing fil~s for~ed under -~ubstantially the sa~e condltion~ on dlfferent surface areas of an identical semiconductor body and that are made of materials being of an ldentlcal ~e~i¢on~uGtor s~s~ance (for example, sllicon) ~ut havlng different conducti~lty ~ypes. A specific example of this will now be described.
Each of ~igures 59 and 60 depicts the conceptual sectlonal structures o~ the respecti~e F~T~ formed within a ¢om~lemer.tary MOS integrated circuit ~CMOSI~). Hereinafter, for the ~aXe 3~ o~ brevit;, the MOS tran~lstor whose gate electrode is made ~ ~5~3 of a P~-type semiconductor shall be called the "?~ gate MOS", ~he MOS tran-~i~tor whose gate electrode 1~ made of ~n N+-type semiconductor shall be called the "N~ gate MOS", and the ~IOS
transl~tor whose gate electrode ls made of a~ lntrinsic or i-type ~emlconductor ~hall be called the ~i zate ~IOS". In Figure 60, the left half shows P~, i and N+ gate P-ckannel .'tOS transistor~, while the right half shows P~, 1, and N' gate N-channsl- MOS transi tor~. ' The differences of threshold voltages a~ong the ~'OSFETs 1 tQl) - (Q3) and (Q4) ~ (Q6) in Flgure 60 is as in the following t~ble:
Table ~Unit: volt~
i Ql Q2 Q3 Q4 a5 ~6 5 . . -~ . _ ~ __________ l `~ 0.55 1.1 _ ~ _ _ Q2 .55 " ~ 0.55 _ _ _ Q3 1,1 0.55 .. ~ _ _ ~ .. _ . . _.~ ~ .. .. ,, _ . _ ._ Q4 _ _ _ ~ 0.55 1.1 . . - . . .. . . ~ . - .. .. _ 2 ~ Q _ _ . ~ 0.55 `~ \ 0.55 .~- v . ~_ - ___ - -- ~-- .
~6_ _ _ 1.1 0.55 \
As wlll be de~cribed ln detail later, Figures 73(a) S to 73(f) illu~trate sectional v~ews of prlncipal steps w~lch show that the P+ gate MOS and the N~ yate MOS can be fabricated without altering or adding to any of the steps of a conventional process for manufacturing a comple-mentary MOS integrated circuit (CMOS IC).
3 ~ Flgures 65(a) and 65(b) or ~i~ures 6~a) and 66(~) S~t~3 depict a plan view and sect.ional s~ructural vlew of N
gate or P~ gate P-c~a~nel MOS transi~tors to be aotually used in clrcult structures, respectively.
Referring to Figures 65(a) and 55(b) or ~i~ures 66(a) and 66(b), ln order ~o form a self-alignment structure, a P-type impuri~y i~ dlffused in both tho.~e end parts ~S and r~ of the gate electrode G ~orme~ of a~ 1 ty~e or 1~trinsic ~emlconductor~which are close to a sourGe (S) and a drain (3), for both the P+ ~ate MOS and the N~ gate ~ S because the I O ~OS transistor is of the P-channel ln this ~ase. In 2 central part Cp of the gate eleGtrode G, a P-type impurlty is diffused for the P+ gate ~.OS, and an N-type impuri~y ls di~fused for the ;Y~ ~ate MOS. A region l~in which no i~purity is dlfL~sed~
ls provided between the central re~Gn and bo~h ~:qe end par~s IS ES and ~D close to the source and the dra1n. It is thus considered that the point of difference between the ?~ gate MOS and the N+ gate ~IOS is only whether the region of the central region part Cp o~ ~he gate is of the ?-type semiconductor or the N-type se~conductor.
ao In Figures 65(a) and 65(b) or ~lgure~ 66~a) and 66(b), numeral 101 designates an N slllcQn substrate, numeral 108 a P+ source region~ numeral 113 a P drain reslon, numeral 105 a gate oxide film, numeral 104 a thlcX fleld oxlde film, and numeral 111 another oxide film. As can be understood from Figure 65(a) or Figure 66(a), a plurality of P~ source regions 108 are electrically connected in common with one another by an lnterconnectlon layer 114, a plurallty of P+ drain regiors 113 are electrically co~necte~ ln com~on wi~h e~h other by an lnterconne¢tion layer ~12, snd a ~luralit~ of 3~ gate electrodes C.are electrically connected l~ ~ommon with ~5~3 one another by an interconnection layer 115.
Further, in order to reduce as much as possible varlation of the effect~e channel lengths o~ the MOS
tra~slqtors attrlbuted to the ~'a~t that ~he :~-type impurlty di~fus~d reglons at both the end parts CS and ED ~ the gate electrodes ~ formed for the self-aligr.ment may shift onto eLther the lef~ or right side (source side or d~ln side) during manufaCture on account of the error of mask alignment, the columns of the source region~ and the dr~ln resions are l~ alterrlatQly arranged, and the columns are arranged so that the left hal~ and the r~ght hal~ m?.y be put into line symmetry with re~pect to the channel dlrection as a wnole.
Accordin~ly, even wh~n the sh1ftlng 5~ the ~25~. align~ent wlth respect to the chanr.ei direction ~lef.w~rd or ri~.t~;ard shlfting) changeq the effective channel len~ths ~f tne ?~Ts in the respectlYe columns, ~he average effective charnel lengths of the P+ gate ~IOS and the N~ gate MOS in the respec-ti~e columns connec~ed 1~ parallel ~.a~e the chan~e~ cancelled as a whole and become ~ubstantlally constant.
Flgures 73(a) to 73(f) lllustrate how the P~ gate MOS and ~he N~ gate MO~ are constructed ~y the use of the conventional manufacturing process for a silicon gate C~CS IC.
In ~igure 73ta), ~umeral lOl designates an N-type sllicon ~emico~ductor having a specific re~i~ta~ce of 1 ~ c~
2S to 8Qcm, on which a thermal oxidation film 102 i5 grown to about 4,000 A to 16,000 A. A window for selective diffusion is provided in the film by a photoet¢hing technique. Boron, to serve as a P-type impurity, is ion-implanted in a quantity f approximately loll to lol3 cm-2 at an e 50 KeV to 200 KeV, whereupon it is thermally diffused for ~ - 31 ., ~
4~63 about 8 to 20 hour~ thereby to form a P~ well reg'o~ 10~
which serves a~ a substra~e o an N-channel ~lOS translstor.
In Figure 73(b), the thQrmal o~ldation f~l~s 102 ls fully removed, a new-thermal oxldatior, fil~s 104 ~s formed at ; about 1 ~m to 2 ~m" and a region of ~his film corresponding to the source, draln and gate of the i~,OS transistQr is reDoved by etching. Ther~after, a gate oxide f~lm lO~ wh~ch is about 300 A _ 1,500 A thick ;s formed. On the resultant substrate, polycrystalline Sl 106 ~ing of the i-type or ~ntrlnsic seQiconductor 1~ grown to about 2,000 A ~o 6,000A.
By etching, lt ls removed with the gate p~rt C of the ;~IOS
transistor left behlnd.
In ~igure 73(c~, a mask oxide f~lm 107 ls for~ed oy vapor 6rowth, an~ lts regions under whlch a P-type im~urity is to be diffused are removed by the ph~oetchlng technlque.
Thereafter) boron,bein~ the ~-type impurity~l~ diffu~ed at a hign density of about 102 to 1021 cm 3 to form a source re~lon 108 and a drain region 113 of the ?-channel MOS translstor and simultaneously to form a gate electrode of a P~type ~0 semiconductor.
In ~igure 73~), as ln the foregolng, a mask oxl~e film lO9 is formed by vapor gÆowth, and its regions under which an ~-type lmpurity ls to be dif~used are removed by the photoetching technl~ue. Thereafter, phosphorus,be~ng ~5 the N-type lmpurity,l~ dlffused at a hlgh denslty of about 102 to 1021 cm 3, to ~orm a source reglon llO and a drain re~lon 116 o~ the N-channel klOS transistor and slmultan~ously to ~orm a gate electrode of a~ N-type se~o~,ductor.
In Fl~ure 73(e), the oxide r~ lm lO9 1~ remoYed. ~n O oxide film 111 whlch 1~ approximately 4,000 A to 8,0CO A
~45~;3 thlck is formed by the vapor growth, and lts re~ion correspondlng to an electrode leading out portion is re~oved by the photoetchin~ technique. Therea~ter, a metal (Aluminum) ls eYaporated~ and an electrode lnterconnectlon portion 112 is formed by the photoetcnin~ ~echnlque.
In ~i~ure 73(f), the resultant substrate ls covered with an oxide film bein~ 1 ~m to 2/um thick by vapor ~rowth.
Now, the thre3hold voltage of the ~.OS translstor employing the se~iconductor for the gate electrode will be descrlbed with reference to ~igures 5(a) to 5(d). ~lrst, in the case of the P~ gate ~10~, the following ls indicated from an energy band diagram of Figure 5(a):
q VG + q~ C ~ ~ ~ VO ~ q ~ f ~ ~si where VG: Potential differen¢e between a semiconductor ~ubstrate and a gate electrode (P~ semiconductor), ~ : Electron af~lnity, E : ~nergy gap, as g rf: Surface potential o~ an ~I-type se~lcond~ctor substrate, ~p: ~ermi potential o~ a ~-type ~emicon~uctor w~th rofere~ce to th~ Fermi potenclal of an lntrinsic se~ on~uctor, ~B: ~erml potential o~ the ~'-type semiconductor ~ubstrate ~ with reference to the Fermi potential of the i~trlnsic semiconductor ~ ~ ~ 5~ ~ 3 q- Unit charge of electron, YO: Potential difference applied to an in~ulator, Ec: ~ottom Or a conduction band, Ev: Top of a ~alence band, Ei: Fermi level o f the lntrlns$c semiconductor.
In Equa~ion (7), the work funotlon of the gate electrode i5 denoted a~ ~MP ~ ln potentlal, and the work function of the semlconductor ~s similarly denoted as ~Si- Then, ~p ~ X + 2~ + ~FP ....~...(8) ~Si ~ + 2q ~F
Therefore, ~5 VO ~ -VG + ~MP ~S~ ~Sr~ ............... .(10) From the relation of ~harges in Figure 5(b), OX VO QSS + Ql ~ QB ~ ~............. .(li) ~here COx: Capacitance Or the insulator per unlt area, QSS: Fixed charge~ ln the insulator, QB: Fixed charge~ due to ionizatlon of impuritie~
in the semlconductor substra~e, Qi: Carriers formed a~ a channel.
From (10) and (11), ~COX ~ YG + ~ ~Si ~5rf) ` ~ QSS ~ Qi ~ QD ~ ~ .................. ~(1~) The gate voltage VG at the time when the channel Ql 1 formed is the thresho}d volta~e, ~h~refore, le~ting Y~hp~
denote the thresho'd voltage of th~ P~ gate MOS, V ~ ~ YCl ~ ~MP ~ ~Si PSrf ~ CO~ ~OX
- 3~ -~ 6 At thi5 tlme, ~Srr ~ 2 ~F-Like~ise, in the N+ gata MOS transistor, only the work function ~tN+ of the gate el~ctrode dlffer~ as follows:
~MN ~ + 2q ~ dFN ................. ~....... (14) S Accordlngly, the threshold voltage VthN~ of the N~ gate MOS becomes:
. . .
MN Si Srf C C
OX OX
where ~Srf ~ 2'~F-Thu~, the dif~erence Vthp~ - Yt~y~ of the threshold o voltage~ of the P~ gate MOS and the N+ gate MOS becomes:
thP V~hN ~ ~MP ~ ~MN ~ dFP ~ ~,y+ ~...(1~) whlch i5 equal to the diiference of the Fermi p~tentlals of the semlconductors mak~ng up the gate electrodes.
Thi~ can be readily under~tood from the fact that, when ~5~ Flgures 5~a) and 5Ic) are compared, the gate voltage at the tlme when the same charge.proflle i established i~ equal to the di,fference of the w~rk functions of the ~ate electrode~.
and the dif~erence of the Fermi le,vels.
Whllè the above description has been made by taking ~O ~he P -channel ~IOS trar,sistor as an example, qulte the ~ame applles to the ca~e o~ the N = chan~el MOS tran~i~torr From the above, it can be understood that a voltage substantially equal to the energy gap Eg can be derlved as t~e difference of the threshold voltage~ of the P~ gate MOS
d5- and ~he N+ gate ~tOSo. As another method, the voltage of the energy gap Eg c~n be derlved with the dlfI'erence of the thre~hold voltage of a MOS who~e gate elect~ode i~ mada of .
an lntrlnslc semlconductor (hereinbelow, written as the "i gate MOS") and the thre~hold ~olta~e of the P+ gate MOS
or the N~ gate MOS.
Letting Ythi denote the threshold voltage of the i gate M05, ~ince the Ferml level of the intrlnslc semicor.ductor ls O (zero) (a~ the ~ermi level o~ the lntrinslc semiconductor ls made the reference), the di~ference of the threahold ~oltages of ~e i gate MOS and the P~ gate MOS is:
IYthi - YthP ¦ ~ lo - ~FP ¦- 1/2 3g ....... ~.. (17) The difference of the thre~hold voltages of the i Bate MOS
and the N+ gate MOS becomes:
¦ thi YthN ~ FN - O ¦ ~ 1/2 Eg ............... (18) It can be readily understood that the difference becomes a voltage of just a half of the energy gap E9.
The ~oltage which is obtalned owing to the d~fference of the thre~hold volta~es o~ the i gate MOS and the P+ gate or N+ gate MOS i~ very use~ul in that lt i5 approxl~ately 0.55 Y and suitable for a low reference voltage source, and that~as wlll be stated later, a referenGe voltage source o~ high precision i~ easily obtained, not only by the manu~ac-turing process of the CMOS integrated circult, b~t also by t~e manufacturing proce ~ o~ single-channel MOS lntegrated circult because the doping ~f gate electr~des wlth an impurity ca~ be carried out by one ~tep.
~5 Figures 67(a) and 67(b) to Flgures 72(a) and 72~b) depict plan pattern~ and ~ectlonal struGtureq along llnes A - A of the plan patterns, of P~ ~ate, i gate a~d N+ gate P-channel and N~channel ~OS transistor~ to ~ actually u~ed in circult str~ctures.
3~ In the various igures, as in Figures 65(a) ~ 36 -S~3 and 65(b) or Figures 66(a) and 66(b), the P- or N-type regions o~ a source and a drain are formed by tne diffusion of an impurity by employing polycry~talllne Si for a mask. In order to allow a margin for th~ mask a" ~n~e~t between the mask for selectively diffusi~g a F-t~pe 1~purity or an N-type impurity and the source and drain re~iors, the same impurlty as that o~ the source and drain regions i~ dif~u~ed in both end part~ ES and ED of a ~ate electrode G adJolning the source S and drain D in bo~h the P+ gate MOS and the N+ gate ~IOSO In, for example, the ?-channel ;~'~S , boron which is the ?-type impurlty i~ diffu~ed. In a central part of the gate electrode, a P-type lmpurity ls d~ffused for the P+ gate ~IOS, and ~ N-type lmpurity ls d1ffused for the N~ g~te MOS.
~i~ures 67(a) and 67(b), Flgure~ 68(a) and 68(b) and Flgures 69(a) and 69~b) represent plan vlews and sectional vlews of P-charnel MOS tran~lstors of the P~ ~ate, i gate and N~ gate, respectively, whlle Figures 70(a) and 70~b), Fi~ure~ 71(a) and 71(b) and Flgure~ 72(a) and 72(b) represent ~0 N-channel MOS transistors o~ the N~ gate, i gate and P~ ga~e, respectlvely.
In ~igures 67~a) and 67(b) to Fl~ures 72~) and 72(b), ln order to r~duce to the utmo3t the lrarlation of the erfectlve chan~el Iength-~ o~ the M~S translstors attrlbuted ~5 to the fact that those reglon~ at both the end parts Es and ED of the gate electrode~ G, whlch are ~or~ed for the ~elf-nment, and ln which the ~ me impurity as that o~ the ~ource and draln regt ons is diffu~ed, ~hlft to eith~r the lef~
or right side (source side or drain side) during manufac-ture on account of errors of the mask ali~nment, the columns ~s~
of the source regions and the drain reglons are alternately arranged, and the columns are arrqnged so that the left hal~
and the rlght half may be put into a llne sym~etry wlth respect to the channel directlon as a whole. Accordingly, even when the shlfting of the mask alignment with respect to the channel directlon (leftward or rlghtward shlftlng) changes the effective channel lengths of the FFTs ln ths respective col~mns, the a~erage effecti~e channel len~ths of the P+ gate MOS, i gate MOS and the N~ gate MOS in the l~ respectl~e columns connected in parallel have the change~
cancelled as a whole and become substarltially constant.
~ igures 74(a) to 74(d) lllustrate how the ?+ gate MOS
and the N+ gate ~IOS are constructed in the con~entional sillcon gate CMOS manufacturlng proce3s.
1~ ;n Figure 74(a~, numeral 101 designate~ an N-type silicon ~e~iconductor haYlng a speciflc re lstance of lQ cm to 8ncm, on which a thermal oxidation film 102 is grown to O O
about 4,000 A - 16,000 A. A window for selective dif~usion is provided in an area of the film by the photoetching technique. Boron, to serve as a P-type impurity, is ion implanted in a quantity of approxlmately 1011 - 1013 cm 2 at an energy of 50 KeV - 200 xeV, whereupon it is thermally diffused for about 8 - 20 hours, thereby forming a P well ~eg~on 10~ whlch serYes as a substrate of an N-chan~el MOS
transl~tor.
In Figure 74(b), the thermal oxidation film 102 is en-tirely removed, a new thermal oxidation film 104 is formed to about 1 ym - 2 ~m, and a region of this film corre r~nd~r.g to the ~ource, drain ard gate of the MO~ transis,or 's removed by etchlng. Thereafter, a gate ~xlde film 105 which ~ ~ ~ S~ 3 i~ about 300 g - 1,500 g thlck is formed. On the resultant substrate, polycry3talline Si 106 being Or the 1-type or intrinslc ~emiconductor i9 grown sbout 2,0C0 2 5,000 A.
By etching, it ls re~oved with the ga~e ~art G of the MOS
transistor left behlnd In Flgure 74(c), a mask oxide film 107 1~ for~ed by vapor growth, and its regions under which a P-type ~mpur1ty is ~.Q be diffu3ed are removed by the photoetcr.ing technique Thereafter, boron to become the P~type lmpurlty /0 at a hieh density o~ about 102 - 1021 cm 3 ls di~fu3ed, to for~ ~ sourca region 108 and a draln region 113 of the ?-channel MOS transistor and simultaneously t~ f~rm ~ gate electrode of a P-type semicondu~tor.
In Flgure 74(d), as in the fore~oing, a ~as~ oxide f~lm 109 is formed by ~he ~apor growth, and it regions under which an N-type impurity i3 to be di~fused are re~oved by the photoetching technlque. Thereafter, phosphorus to become the N-type impurity at a high concentratlon of about 102 - 1021 cm 3 i9 diffused, to form a s~urce reglon 110 ao and a drain reglon 116 of the N channel MOS transistor and simultzneously to form a gate electrode of an N-type semlconductor.
Subsequently, the ox~de fllm 109 is removed. An ox~de film which ls approximat~ly 4,000 A - 8,000 A thic~ ormed ~S by the vapor growth, and i~s part correspondlng to a~ electrode leading-ou~ portion 1-~ remoYed by the photoetching tec~nique.
Thereafter, a metal(aluminum) ls eY~porated, and an electrode lnterconnection portion is formed by ~he phot~etching techni~ue.
Subsequently, the r~sultant ~ubstrate ls covered with 3~ an oxide film being 1 ~m - 2 ~m thlck by vapor growth.
_ ~9 _ ~ ~ ~ 5~ ~ 3 Here, in Figure 74(d), Q3 and Q4 indlcate ~OS transistors whlch cons~i~ute a conventlonal C~IOS inverter, and Ql and Q2 indlcate P~ gate and N~ ga~e M03 translstors for genera~-lng a reference voltage.
Figures 75(a) to 75(d) show 3ectlons ~n the ~anufactur-ing process of P~ gate M03 and i gate MOS tran~istors of the P-channel type. In this exam~le, the steps up to Figure 75(c) are thë same aq those up to ~igure 74(~). In Fi~ure 75~d), however, the N-type lmpuri~y 1~ dlffused without ~0 removlng an oxide fllm lO9b overlying the gate of th~
MOSF~T Q2.
Figureq 76(a) to 76(d) sh~w sections in the manufacturlng proce~s Or P+ gate MOS and N+ gate MOS tran3istors of the N-channel type.
)5 ~lgures 77(a) to 77(d~ ~how se~tlo~ in the manufacturin~
procesq of N+ gate M05 and 1 gate MOS transistors of the N-channel type, Now, a process in an N-channel MOS qemlconductor integrated circult w$11 ~e explalned with reference to ~0 Qectlons lllu~trated in Figure~ 78(a) to 78(e).
(1) A P-type semlconductor substrate 101 havlng 2 speciflc reqistance of 8 - 20~ cm lq prepared, and a thermal oxidation fllm 102 which 1~ thlck is fsr~ed on the surface of the substrate.
2~ (23 In order to expose ~he semiconductor ~ubstrate surface correspondlng to portlons ln whlch ir~SFETs are to be formed, selected parts of the thermal oxldation film are etched.
(3) ThereafterJ a ga~e oxide f~lm (S10~) 103 which ~s 3~ 750 to ~,000 A th~ck ls formed on the ~xposed semlconductor ~5~3 substrate surface (Figure 7a(a)).
(4) That part of the ~ate oxlde fllm 103 whlch ls to come i~to direct contact wlth a polycryqtalllne sllicon layer is selectively etched, to form a dlrect contact hole 103a. (Flgure 78(b)).
which serves a~ a substra~e o an N-channel ~lOS translstor.
In Figure 73(b), the thQrmal o~ldation f~l~s 102 ls fully removed, a new-thermal oxldatior, fil~s 104 ~s formed at ; about 1 ~m to 2 ~m" and a region of ~his film corresponding to the source, draln and gate of the i~,OS transistQr is reDoved by etching. Ther~after, a gate oxide f~lm lO~ wh~ch is about 300 A _ 1,500 A thick ;s formed. On the resultant substrate, polycrystalline Sl 106 ~ing of the i-type or ~ntrlnsic seQiconductor 1~ grown to about 2,000 A ~o 6,000A.
By etching, lt ls removed with the gate p~rt C of the ;~IOS
transistor left behlnd.
In ~igure 73(c~, a mask oxide f~lm 107 ls for~ed oy vapor 6rowth, an~ lts regions under whlch a P-type im~urity is to be diffused are removed by the ph~oetchlng technlque.
Thereafter) boron,bein~ the ~-type impurity~l~ diffu~ed at a hign density of about 102 to 1021 cm 3 to form a source re~lon 108 and a drain region 113 of the ?-channel MOS translstor and simultaneously to form a gate electrode of a P~type ~0 semiconductor.
In ~igure 73~), as ln the foregolng, a mask oxl~e film lO9 is formed by vapor gÆowth, and its regions under which an ~-type lmpurity ls to be dif~used are removed by the photoetching technl~ue. Thereafter, phosphorus,be~ng ~5 the N-type lmpurity,l~ dlffused at a hlgh denslty of about 102 to 1021 cm 3, to ~orm a source reglon llO and a drain re~lon 116 o~ the N-channel klOS transistor and slmultan~ously to ~orm a gate electrode of a~ N-type se~o~,ductor.
In Fl~ure 73(e), the oxide r~ lm lO9 1~ remoYed. ~n O oxide film 111 whlch 1~ approximately 4,000 A to 8,0CO A
~45~;3 thlck is formed by the vapor growth, and lts re~ion correspondlng to an electrode leading out portion is re~oved by the photoetchin~ technique. Therea~ter, a metal (Aluminum) ls eYaporated~ and an electrode lnterconnectlon portion 112 is formed by the photoetcnin~ ~echnlque.
In ~i~ure 73(f), the resultant substrate ls covered with an oxide film bein~ 1 ~m to 2/um thick by vapor ~rowth.
Now, the thre3hold voltage of the ~.OS translstor employing the se~iconductor for the gate electrode will be descrlbed with reference to ~igures 5(a) to 5(d). ~lrst, in the case of the P~ gate ~10~, the following ls indicated from an energy band diagram of Figure 5(a):
q VG + q~ C ~ ~ ~ VO ~ q ~ f ~ ~si where VG: Potential differen¢e between a semiconductor ~ubstrate and a gate electrode (P~ semiconductor), ~ : Electron af~lnity, E : ~nergy gap, as g rf: Surface potential o~ an ~I-type se~lcond~ctor substrate, ~p: ~ermi potential o~ a ~-type ~emicon~uctor w~th rofere~ce to th~ Fermi potenclal of an lntrinsic se~ on~uctor, ~B: ~erml potential o~ the ~'-type semiconductor ~ubstrate ~ with reference to the Fermi potential of the i~trlnsic semiconductor ~ ~ ~ 5~ ~ 3 q- Unit charge of electron, YO: Potential difference applied to an in~ulator, Ec: ~ottom Or a conduction band, Ev: Top of a ~alence band, Ei: Fermi level o f the lntrlns$c semiconductor.
In Equa~ion (7), the work funotlon of the gate electrode i5 denoted a~ ~MP ~ ln potentlal, and the work function of the semlconductor ~s similarly denoted as ~Si- Then, ~p ~ X + 2~ + ~FP ....~...(8) ~Si ~ + 2q ~F
Therefore, ~5 VO ~ -VG + ~MP ~S~ ~Sr~ ............... .(10) From the relation of ~harges in Figure 5(b), OX VO QSS + Ql ~ QB ~ ~............. .(li) ~here COx: Capacitance Or the insulator per unlt area, QSS: Fixed charge~ ln the insulator, QB: Fixed charge~ due to ionizatlon of impuritie~
in the semlconductor substra~e, Qi: Carriers formed a~ a channel.
From (10) and (11), ~COX ~ YG + ~ ~Si ~5rf) ` ~ QSS ~ Qi ~ QD ~ ~ .................. ~(1~) The gate voltage VG at the time when the channel Ql 1 formed is the thresho}d volta~e, ~h~refore, le~ting Y~hp~
denote the thresho'd voltage of th~ P~ gate MOS, V ~ ~ YCl ~ ~MP ~ ~Si PSrf ~ CO~ ~OX
- 3~ -~ 6 At thi5 tlme, ~Srr ~ 2 ~F-Like~ise, in the N+ gata MOS transistor, only the work function ~tN+ of the gate el~ctrode dlffer~ as follows:
~MN ~ + 2q ~ dFN ................. ~....... (14) S Accordlngly, the threshold voltage VthN~ of the N~ gate MOS becomes:
. . .
MN Si Srf C C
OX OX
where ~Srf ~ 2'~F-Thu~, the dif~erence Vthp~ - Yt~y~ of the threshold o voltage~ of the P~ gate MOS and the N+ gate MOS becomes:
thP V~hN ~ ~MP ~ ~MN ~ dFP ~ ~,y+ ~...(1~) whlch i5 equal to the diiference of the Fermi p~tentlals of the semlconductors mak~ng up the gate electrodes.
Thi~ can be readily under~tood from the fact that, when ~5~ Flgures 5~a) and 5Ic) are compared, the gate voltage at the tlme when the same charge.proflle i established i~ equal to the di,fference of the w~rk functions of the ~ate electrode~.
and the dif~erence of the Fermi le,vels.
Whllè the above description has been made by taking ~O ~he P -channel ~IOS trar,sistor as an example, qulte the ~ame applles to the ca~e o~ the N = chan~el MOS tran~i~torr From the above, it can be understood that a voltage substantially equal to the energy gap Eg can be derlved as t~e difference of the threshold voltage~ of the P~ gate MOS
d5- and ~he N+ gate ~tOSo. As another method, the voltage of the energy gap Eg c~n be derlved with the dlfI'erence of the thre~hold voltage of a MOS who~e gate elect~ode i~ mada of .
an lntrlnslc semlconductor (hereinbelow, written as the "i gate MOS") and the thre~hold ~olta~e of the P+ gate MOS
or the N~ gate MOS.
Letting Ythi denote the threshold voltage of the i gate M05, ~ince the Ferml level of the intrlnslc semicor.ductor ls O (zero) (a~ the ~ermi level o~ the lntrinslc semiconductor ls made the reference), the di~ference of the threahold ~oltages of ~e i gate MOS and the P~ gate MOS is:
IYthi - YthP ¦ ~ lo - ~FP ¦- 1/2 3g ....... ~.. (17) The difference of the thre~hold voltages of the i Bate MOS
and the N+ gate MOS becomes:
¦ thi YthN ~ FN - O ¦ ~ 1/2 Eg ............... (18) It can be readily understood that the difference becomes a voltage of just a half of the energy gap E9.
The ~oltage which is obtalned owing to the d~fference of the thre~hold volta~es o~ the i gate MOS and the P+ gate or N+ gate MOS i~ very use~ul in that lt i5 approxl~ately 0.55 Y and suitable for a low reference voltage source, and that~as wlll be stated later, a referenGe voltage source o~ high precision i~ easily obtained, not only by the manu~ac-turing process of the CMOS integrated circult, b~t also by t~e manufacturing proce ~ o~ single-channel MOS lntegrated circult because the doping ~f gate electr~des wlth an impurity ca~ be carried out by one ~tep.
~5 Figures 67(a) and 67(b) to Flgures 72(a) and 72~b) depict plan pattern~ and ~ectlonal struGtureq along llnes A - A of the plan patterns, of P~ ~ate, i gate a~d N+ gate P-channel and N~channel ~OS transistor~ to ~ actually u~ed in circult str~ctures.
3~ In the various igures, as in Figures 65(a) ~ 36 -S~3 and 65(b) or Figures 66(a) and 66(b), the P- or N-type regions o~ a source and a drain are formed by tne diffusion of an impurity by employing polycry~talllne Si for a mask. In order to allow a margin for th~ mask a" ~n~e~t between the mask for selectively diffusi~g a F-t~pe 1~purity or an N-type impurity and the source and drain re~iors, the same impurlty as that o~ the source and drain regions i~ dif~u~ed in both end part~ ES and ED of a ~ate electrode G adJolning the source S and drain D in bo~h the P+ gate MOS and the N+ gate ~IOSO In, for example, the ?-channel ;~'~S , boron which is the ?-type impurlty i~ diffu~ed. In a central part of the gate electrode, a P-type lmpurity ls d~ffused for the P+ gate ~IOS, and ~ N-type lmpurity ls d1ffused for the N~ g~te MOS.
~i~ures 67(a) and 67(b), Flgure~ 68(a) and 68(b) and Flgures 69(a) and 69~b) represent plan vlews and sectional vlews of P-charnel MOS tran~lstors of the P~ ~ate, i gate and N~ gate, respectively, whlle Figures 70(a) and 70~b), Fi~ure~ 71(a) and 71(b) and Flgure~ 72(a) and 72(b) represent ~0 N-channel MOS transistors o~ the N~ gate, i gate and P~ ga~e, respectlvely.
In ~igures 67~a) and 67(b) to Fl~ures 72~) and 72(b), ln order to r~duce to the utmo3t the lrarlation of the erfectlve chan~el Iength-~ o~ the M~S translstors attrlbuted ~5 to the fact that those reglon~ at both the end parts Es and ED of the gate electrode~ G, whlch are ~or~ed for the ~elf-nment, and ln which the ~ me impurity as that o~ the ~ource and draln regt ons is diffu~ed, ~hlft to eith~r the lef~
or right side (source side or drain side) during manufac-ture on account of errors of the mask ali~nment, the columns ~s~
of the source regions and the drain reglons are alternately arranged, and the columns are arrqnged so that the left hal~
and the rlght half may be put into a llne sym~etry wlth respect to the channel directlon as a whole. Accordingly, even when the shlfting of the mask alignment with respect to the channel directlon (leftward or rlghtward shlftlng) changes the effective channel lengths of the FFTs ln ths respective col~mns, the a~erage effecti~e channel len~ths of the P+ gate MOS, i gate MOS and the N~ gate MOS in the l~ respectl~e columns connected in parallel have the change~
cancelled as a whole and become substarltially constant.
~ igures 74(a) to 74(d) lllustrate how the ?+ gate MOS
and the N+ gate ~IOS are constructed in the con~entional sillcon gate CMOS manufacturlng proce3s.
1~ ;n Figure 74(a~, numeral 101 designate~ an N-type silicon ~e~iconductor haYlng a speciflc re lstance of lQ cm to 8ncm, on which a thermal oxidation film 102 is grown to O O
about 4,000 A - 16,000 A. A window for selective dif~usion is provided in an area of the film by the photoetching technique. Boron, to serve as a P-type impurity, is ion implanted in a quantity of approxlmately 1011 - 1013 cm 2 at an energy of 50 KeV - 200 xeV, whereupon it is thermally diffused for about 8 - 20 hours, thereby forming a P well ~eg~on 10~ whlch serYes as a substrate of an N-chan~el MOS
transl~tor.
In Figure 74(b), the thermal oxidation film 102 is en-tirely removed, a new thermal oxidation film 104 is formed to about 1 ym - 2 ~m, and a region of this film corre r~nd~r.g to the ~ource, drain ard gate of the MO~ transis,or 's removed by etchlng. Thereafter, a gate ~xlde film 105 which ~ ~ ~ S~ 3 i~ about 300 g - 1,500 g thlck is formed. On the resultant substrate, polycry3talline Si 106 being Or the 1-type or intrinslc ~emiconductor i9 grown sbout 2,0C0 2 5,000 A.
By etching, it ls re~oved with the ga~e ~art G of the MOS
transistor left behlnd In Flgure 74(c), a mask oxide film 107 1~ for~ed by vapor growth, and its regions under which a P-type ~mpur1ty is ~.Q be diffu3ed are removed by the photoetcr.ing technique Thereafter, boron to become the P~type lmpurlty /0 at a hieh density o~ about 102 - 1021 cm 3 ls di~fu3ed, to for~ ~ sourca region 108 and a draln region 113 of the ?-channel MOS transistor and simultaneously t~ f~rm ~ gate electrode of a P-type semicondu~tor.
In Flgure 74(d), as in the fore~oing, a ~as~ oxide f~lm 109 is formed by ~he ~apor growth, and it regions under which an N-type impurity i3 to be di~fused are re~oved by the photoetching technlque. Thereafter, phosphorus to become the N-type impurity at a high concentratlon of about 102 - 1021 cm 3 i9 diffused, to form a s~urce reglon 110 ao and a drain reglon 116 of the N channel MOS transistor and simultzneously to form a gate electrode of an N-type semlconductor.
Subsequently, the ox~de fllm 109 is removed. An ox~de film which ls approximat~ly 4,000 A - 8,000 A thic~ ormed ~S by the vapor growth, and i~s part correspondlng to a~ electrode leading-ou~ portion 1-~ remoYed by the photoetching tec~nique.
Thereafter, a metal(aluminum) ls eY~porated, and an electrode lnterconnection portion is formed by ~he phot~etching techni~ue.
Subsequently, the r~sultant ~ubstrate ls covered with 3~ an oxide film being 1 ~m - 2 ~m thlck by vapor growth.
_ ~9 _ ~ ~ ~ 5~ ~ 3 Here, in Figure 74(d), Q3 and Q4 indlcate ~OS transistors whlch cons~i~ute a conventlonal C~IOS inverter, and Ql and Q2 indlcate P~ gate and N~ ga~e M03 translstors for genera~-lng a reference voltage.
Figures 75(a) to 75(d) show 3ectlons ~n the ~anufactur-ing process of P~ gate M03 and i gate MOS tran~istors of the P-channel type. In this exam~le, the steps up to Figure 75(c) are thë same aq those up to ~igure 74(~). In Fi~ure 75~d), however, the N-type lmpuri~y 1~ dlffused without ~0 removlng an oxide fllm lO9b overlying the gate of th~
MOSF~T Q2.
Figureq 76(a) to 76(d) sh~w sections in the manufacturlng proce~s Or P+ gate MOS and N+ gate MOS tran3istors of the N-channel type.
)5 ~lgures 77(a) to 77(d~ ~how se~tlo~ in the manufacturin~
procesq of N+ gate M05 and 1 gate MOS transistors of the N-channel type, Now, a process in an N-channel MOS qemlconductor integrated circult w$11 ~e explalned with reference to ~0 Qectlons lllu~trated in Figure~ 78(a) to 78(e).
(1) A P-type semlconductor substrate 101 havlng 2 speciflc reqistance of 8 - 20~ cm lq prepared, and a thermal oxidation fllm 102 which 1~ thlck is fsr~ed on the surface of the substrate.
2~ (23 In order to expose ~he semiconductor ~ubstrate surface correspondlng to portlons ln whlch ir~SFETs are to be formed, selected parts of the thermal oxldation film are etched.
(3) ThereafterJ a ga~e oxide f~lm (S10~) 103 which ~s 3~ 750 to ~,000 A th~ck ls formed on the ~xposed semlconductor ~5~3 substrate surface (Figure 7a(a)).
(4) That part of the ~ate oxlde fllm 103 whlch ls to come i~to direct contact wlth a polycryqtalllne sllicon layer is selectively etched, to form a dlrect contact hole 103a. (Flgure 78(b)).
(5) Slllcon ls deposited by ~he CVD (Chemlcal Yapor Deposltlon) proces~ on~o the whole maJor sur~ace of the semiconductor--suostrate 101 having ~he oxlde fil~ 102, the gate ox1de film 10~ and the co~tact hole 103a, to for~ .~he l~ polycrystalline sil~con layer which is 3,000 to 5,000 A.
(6) Selected p~rts of the polycrystalllne s11icon layar 104 belng of the l-type or intrinsic semicon~uctor are etched.
~Flgure 78 (c)).
~Flgure 78 (c)).
(7) A CVD-mask SiO2 fllm is depoqlted to a thlckne3~ of 2,000 to 3,000 A on the whole ma~or surface of the ~em1 conductor ~ubstrate 101 by the CVD ~roce~.
(8) The CVD-mask SiO2 fllm 105 is ~electively left only at high resistance parts such as memory cell load reslstors, and on the polycrystalline s1 licon layer of intrinslc level ~0 gate portions 104a. (~igure 78(d)).
(9) Phosphorus is diffused into ~he semlconduc~or sub-strate 101, to ~orm source regions and draln regions 106 a~
an lmpurity density of 102 atom~/cm3~ At this time ! the lmpurlty ls al~o introduced i~to the polycry talline silicon 2S layer, ~o form gate electrodes 104b, a direct contact 104c and a polycrystalllne sllicon interconnection portion 104d.
(~igure 78(d)).
an lmpurity density of 102 atom~/cm3~ At this time ! the lmpurlty ls al~o introduced i~to the polycry talline silicon 2S layer, ~o form gate electrodes 104b, a direct contact 104c and a polycrystalllne sllicon interconnection portion 104d.
(~igure 78(d)).
(10) A P3G (Phospho-SLlicate-Glass) ~ 107 is .'ormed at a thieXne~s of 7,000 to 9,000 A on the entlre maJor surface 3~ o~ the semiconductor ~ubstrate 101.
~ 41 -~ 3 tll) Al (aluminum) iq thereafter evaporated on the whole area of the maJor ~urface of the semiconductor sub~trate 101, to form an Al f~lm 108 whlch lq 1 ~m thlck.
(12) The ~1 film is ~electlvely etched to form lnter-connection reglons 108. (Flgure 78(e)).
The princi~le o~ derlving the difference of Fer~l levels described above and actual e~am~les will be brlefly explalned ag~in. Xlements shown ln Figure 58 are enhanc~ment type p-channel I~ISFET~ (Ql) and (Q2) whlch are formed on an /~ n-type semlconductor substrate 1. The ga~e electrodes of the respectlve MISF~Ts are made of conductor layers which are constructed ln such a way that polycryqtalline sillcon layerq are doped with semiconductor lmpurltles of dlfferent conductlvlty type~. ~ore qpeclfic211y, the MIS~Ts (Ql~ G2 are fabricated as ~ollows. As ~hown in ~igure 58, p+-type semlconductor reg~onq 4,5 to ~orm the sources and drains of ~ FETs are selectively formed on an n-type ~e~iconductor subqtrate 1. Gate insulating films 2 are formed on the areas of the surface of the semlconductor ~ubstratP between 2~ the opposing source and draln reglons 4,5, and poly-crystalline silicon layers 6 and 6' are formed on the gate inqulating film~ 2. The polycrystalline silicon layer to con~itute the gate 6' of one MIS~ET (Ql) is doped wi~h a semlconductor l~purity of the qame conductlvity type a~ as that of the substrAte (n-type). The polycrystalllne silicon layer to con~tltute the gate 6 of the other MIS~T (Q2) i~ doped with a ~e~lconductor impurity of the conducti~ity type op~os'te to th2t of the substrate (p-.ype).
The threshold volta~es (VthGl, Yth~2) 3a MISFET_ (Ql' ~) in the abo~e constructi~n are evaluated ~; .
~5~3 from the following equatlons (19) and (20):
Qss QD
Ql ~Mn ~ COx ~ Cox ......... (19) thQ2 = ~Mp ~ ss + D ~ ,...... .(20~.
ox c~x Here, ~Mn and ~Mp denote the work functions between the gates of the respectlve MIS~ETs (Qlg Q23 an~ tne substrate, COx the gate capacltanoe oer unit ares, Qss the surface charge, and QD the charge of a substrate depletion layer.
~ 'hen the dlffere~ce of tAe threshold voltages of both the MISFETs (Ql' Q2) ls eval~ated, lt beco~es the difference (~lp - ~) bet~een the work functlons whlch are the irst terms of the right-hand sides of ~quatlons (19) and (2~), ar.d it can be derived as a voltage which corresponds to the energy gap of sillcon. Slnce this voltage becomes a volta~e stipulated by the energy gap of sil~con, dev~atlo~s ln the manufac~ure are not involved. In addition, the temperature-dependency is ex~remely small. The reason why the threshold voltages of MISF~Ts exhiblt great deviations ls that the second terms (~ss/Qox) and the thlrd terms (QD/CoX) on the right-ha~d si~es o~ Equations (19) and (20) fluc~uate depending upon the conditions of ~anufacture. In this embodlment, the the MISF~Ts (~1~ Q2) are ~anufactured un~er the saQe oondl-tlons, whereby the 3econd term~ and thlrd terms ~n the rl~ht- hand slde~ o~ Equat~on~ 19 and 20 are made qub-stantially equal. By evaluatln~ th~ difference betweer. t.~e rlght-hand sidea, the second and thi-d terms are can~ellQd Thus, the magnitude equlvalent to the energy gap ls used as ~5~3 an output voltage~
Since the MISFET (Q2) ha~ the source, draln and gate electrode formed by the u~e of the semlconductor l~purlty of an ldentlcal conductlv~ty type, the conventlonal manufactu.-~5 ing technology of a sllicon gate MISFET in whlch the semi-conductor lmpurity diffusions o~ lt~ source and draln and lts gate electrode are simultaneously carried out can be e~ployed. O~ the other hand, the gate electrode of the MISFET (Ql) canno~ be formed slmultaneously with the source J~ and drain thereof and accordingly needs to be formed ~y 2 separate ~tep. In this regard, a method ls consldered wherein the MISF~Ts ~Ql' Q2) as above ~escribed are formed while e~ploying the conventlonal manufacturing technolo~y cf th~ sillcon gate MISrET in ~hich a gate insulating fil~ and a ~ield insulating film are used a~ a ma3kO ~lternatlvely, the measure illustrate~ in Figure 61 may be considered. More specifically, those parts 6a, 6a' of gate electrodes 6, 6' of MISFETs (Ql' Q2) whlch are proximate to ~ources and drains are made ~ate electrode portlons ln which a p-type semi-a~ conductor impurity o~ the qame conductlYlty type as that ofthe sources and dralns is diff~ed. The ¢entral parts OL the gate electrodeq whlch are not doped with any ~emicor.~uctor impurity, that is, whlch are made o~ the ~ntrinslc semi~
conductor (l-type) are ~electively formed wlth a gate eiec~rode ~5 portion 6b in which a p-type impurity is diffused and a gate electrode portion 6b' in which an n-type semiconductor impurity is diffused, respective7y. The parts doped with no semicond~lctor ic,purity have been d~spo~ed ln con-s~deration of the misre~i3tration of the ma~k ali gn~ent _ _ _ 3~ when forming the gate electrode portions 6b, 6b' ~ ~ ~ 5 ~ 3 of the dif~erent semlconductor lmpurltieq ln ~he selected re~lon~, In thl~ me~hod, the gate elect~ode portlonq ;6a, 6b of the MISFET (Q2) are formed by the same s~ep as that for the diffusion of the source and draln.
S Ea h of the MISFE~s in the above conqtruc~ion haq a ~ate electrode whlch 1~ made up of the plurality of gate electrode portions. The plurality of gate electrode portlons are connected in common and ~he dlfference of ~hreshold voltages of both the MIS~ET~ (Ql' ~2) are taken, whereby l~ threshold ~oltage components based on .}~e electrode portlons of the same qtructure~ (gate electrode por~ions 6a and 6a', and l-type electrode portlons) in bo~h the riISFET~ (Q~ 2) are canceled. In addltlon, regarding the ~IS~T owln~ to the gate electrode portlons ~b, 6b'~, the second an~ third l~ terms on the right-hand ~ides of Equatlons ~19) and (20) are not cancelled. As the differe~ce ~oltage, there is obtalne~
the voltage which corresponds ~o the slllcon energy gap being the dlfference Or the work function between the central parts 6b, 6b' of the gate electrodes an~ the substrate as ao descrlbed prevlously, and which is approximately l.l Y.
Figure 62 ~hows a complementaty insulated Oate field-ef~ect translstor integrated circult (CMOSIC) accordin~ to another embodlment of thi~ inventlon. P-channel MOS tran~'~tora A, B and C are formed on an N-type sllicon body 1, whlle N-a S channel MOS transistor~ D, E and F are ~ormed on a well layer 2 ln which a P-type lmpurlty is diffused at a low concentra~ion. A reference voltage ge~erator de~ice is constructed by exploltin~ the dl~'~erence o~ the threshold volt2~eq of the .~OS trans'stors A and Bl the ~tOS tran~i~tor_ ~0 A and ~ or the MOS transi~tors B and C, or the di~'ference of ~ q~ 3 the threshold voltage~ o~ the MOS transl~ors D and E, the MO~ transistors ~ and F or the MOS tra~sistors E and ~.
Here, numeral ~ designates a thlck field oxide film (SiO2), and numeral 4 a gate oxide film (SiO2). Numeral 5 desl~nates S a P type semlconductor region for the source or draln of the P-channel MOSFET, and numeral 6 an N-type semiconductor reglon for the source or drain of the N-channel MOS~T.
~umeral 7 lndlca~es P-type polycrystalilne sllicon, n~eral 8 N-type ~olycrystalline sillcon, and numeral 9 ~he lntrlnsic ~emiconductor or i-type polycrystalllne slll~n. ~he reference voltage generator de~$ce derlves the ~erml level dif~erence amon3 the materlals 7, 8 and 9 ln the form Or ~he voltage.
~ igure ~3 show an embodlment which is a further improve-ment on the embodi~ent of ~igure 62. P-type lmpur1ty layers lO shown in Fi~ure 63 are dispo~ed under the gate oxide films 4 ln a manner to overlap with the central parts 8 and 9 of the gate electrodes o~ the respectiYe ttan3ist~rs ~ and C ln Figure 62,. and the transistor A is also proYlded w~th a ?-type lmpurity layer lO so as to have an effective a~ channel length equal to those of the translstors B and C.
Further, N-type impurity layers ll shown in ~l~ure 63 are disposed under the gate oxide films 4 in such a manner as to overlap with the central parts 7 and 9 of the gate electro~es of the re~pectlve transi~tor~ E and F in ~igure 62, and the ~5 transistor D ls also provlded with an N-type lmpurity layer
~ 41 -~ 3 tll) Al (aluminum) iq thereafter evaporated on the whole area of the maJor ~urface of the semiconductor sub~trate 101, to form an Al f~lm 108 whlch lq 1 ~m thlck.
(12) The ~1 film is ~electlvely etched to form lnter-connection reglons 108. (Flgure 78(e)).
The princi~le o~ derlving the difference of Fer~l levels described above and actual e~am~les will be brlefly explalned ag~in. Xlements shown ln Figure 58 are enhanc~ment type p-channel I~ISFET~ (Ql) and (Q2) whlch are formed on an /~ n-type semlconductor substrate 1. The ga~e electrodes of the respectlve MISF~Ts are made of conductor layers which are constructed ln such a way that polycryqtalline sillcon layerq are doped with semiconductor lmpurltles of dlfferent conductlvlty type~. ~ore qpeclfic211y, the MIS~Ts (Ql~ G2 are fabricated as ~ollows. As ~hown in ~igure 58, p+-type semlconductor reg~onq 4,5 to ~orm the sources and drains of ~ FETs are selectively formed on an n-type ~e~iconductor subqtrate 1. Gate insulating films 2 are formed on the areas of the surface of the semlconductor ~ubstratP between 2~ the opposing source and draln reglons 4,5, and poly-crystalline silicon layers 6 and 6' are formed on the gate inqulating film~ 2. The polycrystalline silicon layer to con~itute the gate 6' of one MIS~ET (Ql) is doped wi~h a semlconductor l~purity of the qame conductlvity type a~ as that of the substrAte (n-type). The polycrystalllne silicon layer to con~tltute the gate 6 of the other MIS~T (Q2) i~ doped with a ~e~lconductor impurity of the conducti~ity type op~os'te to th2t of the substrate (p-.ype).
The threshold volta~es (VthGl, Yth~2) 3a MISFET_ (Ql' ~) in the abo~e constructi~n are evaluated ~; .
~5~3 from the following equatlons (19) and (20):
Qss QD
Ql ~Mn ~ COx ~ Cox ......... (19) thQ2 = ~Mp ~ ss + D ~ ,...... .(20~.
ox c~x Here, ~Mn and ~Mp denote the work functions between the gates of the respectlve MIS~ETs (Qlg Q23 an~ tne substrate, COx the gate capacltanoe oer unit ares, Qss the surface charge, and QD the charge of a substrate depletion layer.
~ 'hen the dlffere~ce of tAe threshold voltages of both the MISFETs (Ql' Q2) ls eval~ated, lt beco~es the difference (~lp - ~) bet~een the work functlons whlch are the irst terms of the right-hand sides of ~quatlons (19) and (2~), ar.d it can be derived as a voltage which corresponds to the energy gap of sillcon. Slnce this voltage becomes a volta~e stipulated by the energy gap of sil~con, dev~atlo~s ln the manufac~ure are not involved. In addition, the temperature-dependency is ex~remely small. The reason why the threshold voltages of MISF~Ts exhiblt great deviations ls that the second terms (~ss/Qox) and the thlrd terms (QD/CoX) on the right-ha~d si~es o~ Equations (19) and (20) fluc~uate depending upon the conditions of ~anufacture. In this embodlment, the the MISF~Ts (~1~ Q2) are ~anufactured un~er the saQe oondl-tlons, whereby the 3econd term~ and thlrd terms ~n the rl~ht- hand slde~ o~ Equat~on~ 19 and 20 are made qub-stantially equal. By evaluatln~ th~ difference betweer. t.~e rlght-hand sidea, the second and thi-d terms are can~ellQd Thus, the magnitude equlvalent to the energy gap ls used as ~5~3 an output voltage~
Since the MISFET (Q2) ha~ the source, draln and gate electrode formed by the u~e of the semlconductor l~purlty of an ldentlcal conductlv~ty type, the conventlonal manufactu.-~5 ing technology of a sllicon gate MISFET in whlch the semi-conductor lmpurity diffusions o~ lt~ source and draln and lts gate electrode are simultaneously carried out can be e~ployed. O~ the other hand, the gate electrode of the MISFET (Ql) canno~ be formed slmultaneously with the source J~ and drain thereof and accordingly needs to be formed ~y 2 separate ~tep. In this regard, a method ls consldered wherein the MISF~Ts ~Ql' Q2) as above ~escribed are formed while e~ploying the conventlonal manufacturing technolo~y cf th~ sillcon gate MISrET in ~hich a gate insulating fil~ and a ~ield insulating film are used a~ a ma3kO ~lternatlvely, the measure illustrate~ in Figure 61 may be considered. More specifically, those parts 6a, 6a' of gate electrodes 6, 6' of MISFETs (Ql' Q2) whlch are proximate to ~ources and drains are made ~ate electrode portlons ln which a p-type semi-a~ conductor impurity o~ the qame conductlYlty type as that ofthe sources and dralns is diff~ed. The ¢entral parts OL the gate electrodeq whlch are not doped with any ~emicor.~uctor impurity, that is, whlch are made o~ the ~ntrinslc semi~
conductor (l-type) are ~electively formed wlth a gate eiec~rode ~5 portion 6b in which a p-type impurity is diffused and a gate electrode portion 6b' in which an n-type semiconductor impurity is diffused, respective7y. The parts doped with no semicond~lctor ic,purity have been d~spo~ed ln con-s~deration of the misre~i3tration of the ma~k ali gn~ent _ _ _ 3~ when forming the gate electrode portions 6b, 6b' ~ ~ ~ 5 ~ 3 of the dif~erent semlconductor lmpurltieq ln ~he selected re~lon~, In thl~ me~hod, the gate elect~ode portlonq ;6a, 6b of the MISFET (Q2) are formed by the same s~ep as that for the diffusion of the source and draln.
S Ea h of the MISFE~s in the above conqtruc~ion haq a ~ate electrode whlch 1~ made up of the plurality of gate electrode portions. The plurality of gate electrode portlons are connected in common and ~he dlfference of ~hreshold voltages of both the MIS~ET~ (Ql' ~2) are taken, whereby l~ threshold ~oltage components based on .}~e electrode portlons of the same qtructure~ (gate electrode por~ions 6a and 6a', and l-type electrode portlons) in bo~h the riISFET~ (Q~ 2) are canceled. In addltlon, regarding the ~IS~T owln~ to the gate electrode portlons ~b, 6b'~, the second an~ third l~ terms on the right-hand ~ides of Equatlons ~19) and (20) are not cancelled. As the differe~ce ~oltage, there is obtalne~
the voltage which corresponds ~o the slllcon energy gap being the dlfference Or the work function between the central parts 6b, 6b' of the gate electrodes an~ the substrate as ao descrlbed prevlously, and which is approximately l.l Y.
Figure 62 ~hows a complementaty insulated Oate field-ef~ect translstor integrated circult (CMOSIC) accordin~ to another embodlment of thi~ inventlon. P-channel MOS tran~'~tora A, B and C are formed on an N-type sllicon body 1, whlle N-a S channel MOS transistor~ D, E and F are ~ormed on a well layer 2 ln which a P-type lmpurlty is diffused at a low concentra~ion. A reference voltage ge~erator de~ice is constructed by exploltin~ the dl~'~erence o~ the threshold volt2~eq of the .~OS trans'stors A and Bl the ~tOS tran~i~tor_ ~0 A and ~ or the MOS transi~tors B and C, or the di~'ference of ~ q~ 3 the threshold voltage~ o~ the MOS transl~ors D and E, the MO~ transistors ~ and F or the MOS tra~sistors E and ~.
Here, numeral ~ designates a thlck field oxide film (SiO2), and numeral 4 a gate oxide film (SiO2). Numeral 5 desl~nates S a P type semlconductor region for the source or draln of the P-channel MOSFET, and numeral 6 an N-type semiconductor reglon for the source or drain of the N-channel MOS~T.
~umeral 7 lndlca~es P-type polycrystalilne sllicon, n~eral 8 N-type ~olycrystalline sillcon, and numeral 9 ~he lntrlnsic ~emiconductor or i-type polycrystalllne slll~n. ~he reference voltage generator de~$ce derlves the ~erml level dif~erence amon3 the materlals 7, 8 and 9 ln the form Or ~he voltage.
~ igure ~3 show an embodlment which is a further improve-ment on the embodi~ent of ~igure 62. P-type lmpur1ty layers lO shown in Fi~ure 63 are dispo~ed under the gate oxide films 4 ln a manner to overlap with the central parts 8 and 9 of the gate electrodes o~ the respectiYe ttan3ist~rs ~ and C ln Figure 62,. and the transistor A is also proYlded w~th a ?-type lmpurity layer lO so as to have an effective a~ channel length equal to those of the translstors B and C.
Further, N-type impurity layers ll shown in ~l~ure 63 are disposed under the gate oxide films 4 in such a manner as to overlap with the central parts 7 and 9 of the gate electro~es of the re~pectlve transi~tor~ E and F in ~igure 62, and the ~5 transistor D ls also provlded with an N-type lmpurity layer
11 so as tO have an e~fectl~e channel length equal to those of the transistors E and F, The e~fectlve channel le~gths of the transistors A, ~ and C or the tran31stors D, ~ and can be ~ade ~ubstantlally equal by disposi~g the P-type impurity layers lO or the N-type impurity layers ll.
~ ~ ~ 5~ 69~
Accordlngly, the charact~rlstics between the drain currents and gate voltages of the translstors A, B and C or the tran ~stors D, E and F become curves which are parallel to one another and whlch shift in the directlon of the gate voltage axis by the dl~ferences of the Fermi level~ of the polycrystalline silicon materials at the central parts of the gate electrodes o~ these tr~nsistors. Therefore, the dlfferences of the threshold voltages o. the transis~ors can be derived with high precision in referen~e voltaye 1~ generator c~rcu'ts to be described later.
The tempe.ature-d~pendencie3 of the di~Lerences of- .he threshold volta3e of the three sorts of IG~T~ are very small because the temperature~dependenc~es of the dlf~erer.ces of the ~ermi levels of the gate electrode semlconductors are low, ~ lOures 79(a) to 79(e) illustrate a method of manuf-c-turing the CMOSIC shown in Flgure 63.
(a) A low concentrat10n ~-type well reglon 102 ls formed in an N-type silicon body lO~ by the conventlonal ~ selective dlffu~ion proceC~. Subse~uently, a field oxlde fllm 103 is formed. After for~ing a gate oxlde film 104 ln recesse~ of the f~lm 103, a P-type impurlty layers 105 and an .~-type impurity layers 106 are for~ed by the con-ventional selective ion implantation processes.
~5 (b) Polycry~talline silicon gate elec~rodes 107 are ~ormed by the conventional chemical vapor depositlon and photoetching. At thls stage, the electrodes 107 are of the intrinsic semico~ductor.
~c) .~ mas~ o~id~ fil~ }08 is ~ormed on salected areas 3~ ~y the chemical ~apor depo~ition. Usi~g i~ as a ma~k, source ~ 3 and draln layers 109 of ?-channel MOSFET~ a~d ?-type polycrystalline layers 110 are ~ormed by the ~elective diffuslon o~ a ~-type impurity.
(d) A ma~k oxide fllm 108' is formed on selected areas by the chem~cal vapor deposition again~ Us~ng 1~ as a ~ask, source and drain layers 111 of ~-channel MGSFETs ar.d ~-type polycrystalllne layers 112 are formed by the selective diffuslon of an ~-type lmpurity.
(e) A phcsphosllicate glasq fll~ 113 is ~eposlted, ~0 contact holes are formed thereir.~ and alumlnum electrode3 114 are for~ed, Then, the devlce ls completed.
~l~ure 64 shows another embodiment o~ the Qtructure of ICFETq whlch constitute the reference voltage 8enera.or de~rice of thls lnventlon and whlch have gate elec~rodes o~
dlfferent Fermi levels. Here, IG~ETs A 9 B and C have a gate electrode which ls made of ?-type s~licon 7, a gate electrode whose both ends are made of P-type silicon 7 and whose central part ls made of intrlnslc slllcon 4 and a gate electrode whose both ends are made of ?-type silicon 7 and a~ ~whose central part i5 made of aluminum 12, res?ectlvely.
These gate electrodes are oYerlying on the sate oxlde films (S102) 3 which are formed on dlfferent sur~ace areas of an identical N-type slllcon body 1 under substantlally ~he same condltion~. ~urther, the IG~ETs have ~ource and drain layers 8. A~ to the threshold voltage~, when the threshold voltage YT~ of the IGFET A ls made -0.8 V, that of the ICFET B become~
approxlmately -1~40 Y, and that o~ the ICFET C beco~es appro~lmately -1.95 V. They produce dlfferences ~hich are .~ubstantlally equal ~o the differences o~ the ~er~l levels 3~ of the Sl and Al materials at the central parts of the gate electrodes~
Thls embodi~ent has been made with note taken of the fàct that the temperature-dependency of the difference of approximately 1.15 eY between the Fermi levels of the S hi~h concentratlon P-type ~ilicon and the aluDlnum or tne dlfference of approximately 0.60 eV between the ~ermi level of the intrinsic sllicon and the aluminum ls lo~.
?igure~ 80(a) to 80(d) illustrate an embodl~.ent of ~
method of manu~acturln~ a P-channel IC~ET inteOrated cl.cuit /~ wh;ch includes all the IGF~Ts A, B and C sllown ln ~i~ur 64.
(a) ~ thlck field oxlde film (SiO2) 2 havir.~ recesses ls formed on the sur~ace o~ an N-type sllicon body l, a gate oxide film 3 ls formed ln the recesse~, and a polycryst~lllne qillcon layer 4 is de~o lted by the chemical vapor deposition.
IS ~he polycrystalline silicon layer 4 ls of the intrlnsic semiconductor, Further, a ma~k oxide ~llm 6 is formed on a part of the layer 4 by the chemical vapor deposi~ion.
(b) The polycrystalline sillcon layer ls selectlvely remo~ed by the conYentional photoetch1ng process, and a P-~0 type lmpurity such as ~oron ls thermally dl~fu~ed, ~o ~orm .
source and draln layers 8 and P-type polycrystalline sllicon layers 7. At this time, the part of the polycrystalllne silicon layer 4 co~ered with the oxide fllm 6 ls held intrlnslc.
tc) An insulating film 9 such as phospho~illcate a~ glass fllm owin~ to the chemical vapor deposltlon ls de-~oslted, and contact holeY are formed thereln. nt thls time, a cor.tact hole 10 is slso formed in the central par~ of a gate electrode in an area to become an IG~ET ~.
~d) Aluminum electrodes 11 and 12 are for~ed, and a heat treatment ls conducted at ~80 to 540 C .or 30 ~lnutes ~ - 49 -~ ~ 4 S ~6 ~
to 3 hours. Then, the polycrystalline s11icon at the contact hole 10 diffuses towards the upper surface o~ the aluminum layer owing to its alloyin~ reactlon with the o~lumln~m, and a ~tructure ln which the alu~lnu~ and the 3ate oxide film lie.in direct contact is establis~ d.
The method of manufacturlng the ?-channel IG.~T integrated : circult as illustrated in Figures 8C(a) to ~O(d) 1~ also a~llcable to-~he manufacture of a complementary MIS 1nteOrated circuit substantlally as lt is.
O ~he alloying reactlon may be replaced with an e~pedient in which the central part of ~he gate electrode is removed by photoetching, whereupon alumlnu~ iQ brought lnto d~rec~.
contact with ~he gate insulatin3 fl}m.
The reference voltage gener~tor device ba~ed on such lS a cons ' ruction exhlbits a small te~perature-dependency and small manufacturlng devlatlons, so that it can be utillzed for various electronic circults.
Flgure 81(d) shows the ~tructure o~ ETq A~ B, C and D whlch have thre~hold voltage dl~erences based on the ~erml ~O level dlfferences of gate elec~rodes ln accordance w1th another embodiment of thls lnventlon. The I~FET A is a P-channel MOSFET having a gate electrode made of P-type sllicon 11, while the lGr~ET B ls a P-channel M~S~T h~ving a gate electrode whose both end parts are made of P-type silicon 11 and whose central Fart 18 made of N-type sillcon 8. The IG~ET C ~s an N-channel MOSFET havln~ a gate electrode m2de of N-type silicon 8, whlle the ICFET D ls an N-channel MCSF~T having a gate electrode whose bo~h end parts ~re made of N-type silicon 8 and who~e central part ls made of P-type 3D ~ilicon 11. A reference ~oltage generator device Is constructed ~ ~ ~ 5 ~ ~
by employing a voltage baQed on the dlfference of the thre~hold voltagas of the MOSFET3 ~:and B or the MOSF~Ts C an~ D.
~lgures 81(a) to 81~d) lllustrate a method of fabricat-~ng a ~OS lntegrated circult which includeQ the IGF~Ts A, B, C and D.
(a) A P-type well region 2 ls formed ' n an ~-type sillcon body 1, and a thlc~ ~ield oxide fllm 3 having recesses ls formed. Thereafter, a gate ox~de fllm 4 ls forQed ln the l~ rece~ses of the oxide film 3, and a fllm 5 o~ polycrystalllne slllcon bein~ the intI~inslc semlconductor i-q deposited and worked by the photoetchlng process.
(b) A mask oxide film 6 ls for~ed on ~elected areas by chemical vapor deposition. Using it as a mask, an ~5 N-type lmpurity such as phosphoru~ ls dlffusPd into selected reglons, whereby N-type reglonQ 7,tb become the source~ and drains of N-channel MOSFET~ and N-type polycrystalllne layers 8~are formed, (c~ A ma~k oxide film 9 i3 formed on selected areac ao by chemical vapor deposition. Using i as a mask, a P~type impurity such as boron is lon-~mplanted, whereby P-type regl`ons lO,to become the Qources and dralns of P-channel MOSF~Ts and P-type polycrystalllne ~ilicon layers 11, are formed. Here, when using boron, the oxide film 9 ls made about 3,000 A thi~, and an lmplantation energy of 30 to 50 KeY and an lmplantatlon qua~tlty o~ 2 x 1015 to 1 x 101~/cm2 are approprlate. The actlvatlon of the lmplanted lons 1Q suitably done by a heat t.eatment at ~COC for 10 minutes to at l,000C for 30 mlnutes.
3 ~ The diffusion of the N-type l~p~rit~ ln the step ~b) ~51;~63 may be performed after the qtep (c~. In thls case, the ,Y-type lmpurity dif~uslon indicated in the ~tep (b) had better be execu~ed by the ion lmplanta~lon Or phosphorus or the like. When using phosphorus here, the oxide fllm 6 is ~ade about 3,000 A t;~ick, and an lmplantation energy o~ 60 to 100 KeV and an lmplantatlon quantity of 2 x 1015 to 1 x 1016 /cm2 are approprlate. Sultable for the actlvatlo-n of the lmplanted lons 15 a heat treatment ~t 900C for 10 mlnutes to at 1,000C for 30 mlnute^~. By csrrylng out the doplng wlth the P-ty~e impurlty ln thl3 manner, the heat treatment after the doping with the ?-type ~mpurity can be relleved, so that the channel portions can be preYented from beln~ doped wlth the P-type lmpurlty.
(d) After depo~itin2 a pho~phoslllcate a-las~ f'lm 12 ~5 by chemical vapor deposition, contact holes are formed, and alumlnum electrode~ 13 are for~ed. Then, the devlce 1 flnl~hed.
ReIerrlng sgaln to Figure 58, another embodlment o~
thl~ inventlon will now be described. In the figure, a P-channel ~0 MOSFET ~Ql) ha~ a gate electrode made o~ N-type polycry3ta111ne ~illcon 6', and a P-channel ~OSFET ~Q2) ha~ a gate electrode made o~ P-type po~ycry~talline 3illcon 6.
Slnce these ~ETs are manu~actured under 3ubstantially the same conditio~s except the conductlv~ty type~ of the gate electrodes, the dif~erence of the thre~hold voltages Yth ~ both the FETs become substantially equal to the dlfference o~ the Fermi levels of the P type sllicon and the ~l-type slllcon. ~he gate electro~e~ are d~ped wlth .e~pectlve lmpuritles near ~he ~aturatlon denslties, and the ~0 dif~erence become~ ~ub~tantlally e~ual to the energy gap _g ~ ~ ~ 5~,~ 3 of sllicon (approxi~a~ely 1.1 V). The Vth-difference can be taken out at high precision by maklng the channel dlmenslons of both the FETs equal, and it is utilized as a refer2nce voltage source.
~lnce a re~erence voltage generator device ba~ed on quch a con~truction exhiblts a 3mall temperature-de~endency and small manufacturing deviatlon3, it can be used ~`or varlous electronlc ci~cults.
In Fi~ure 58, numeral 1 designates an ~-ty~e slllcon body, /0 nu~eral 3 ~ th1ck fleld oxlde film, numeral 2 a ~ate oxlde film, numeral 4 a P-type qource re~io~-~ and numeral 5 a ?-type draln region. ~ere, the N-type polycrys~alllne silicon gate ~' ha~ a qtructure wh~ch is doped with both an ~-~ype lmpurity and a P-type lmpurlty, the denslty o~ the N-type impurity being 1.5 time~ or more higher ~han the density of the P~type impurity. Alterna~ively, lt has a ~tructure which i~ doped with an N-type lmpurlty, almo3t ~o P-type lmpurity being contained, and neverthele~s, whlch ls self-allgned with the source and draln.
ao The rea~on why the den3ity of the N type i~purlty needs to be 1.5 time~ or more higher than the density of ~he P-type lmpurlty is as follows. In the ordlnary high-denslty impurity doping techniques, the control o~ a denslty ls subJect to ~deviations of (set value + 20 %) or ~o. ~ccordlngly, the a~ rstio between the deviations of the N-type lmpurlty densi.y and the ?-type lmpurity density become~ (1.5 ~ 0.3)/(1.1 ~ 0.2).
Slnce the minimum value of thl~ ratlo becomes 1/1, the ~er~l level o~ the polycry~talllne Qlllcon doped w'th both the N-type and P-type impuritle~ var~e~ greatly.
3~ In order to allow qome extent of manufacturin3 dlsperslon, ~ 53 -~ 3 accordin~ly, the ratlo of the ~mpurlty de~sltle~ needs to be 1.5 or greater wlthout fall.
Figures ~2(a) and 82(b) lllustrate a method of manufac~
turin~ ICFETs for settln~ the ratio of the impurlty densltles at 1.5 or greater.
(a) An N-type sllicon body 1 at a comparatively low l~pur-lty density (for example, below 5 x 1016 cm 3) is ox~dized to form a thic~ oxlde ~ilm 2 for isolating elementq.
After forming a gate oxide ~llm 3 ln reces~es of the fll~ 2, /0 an lntrln~ic semlconductor polycrystalline sillcon ~ilm at 6 and 5' i~ deposlted by chemical vapor deposition.
Further, a mask oxide film 7 13 formed on 8 ~elected area ~y the chemical vapor depo~ition. Uslng the oxlde fll~ 7 aq a mask, the polycrystalline qilicon film 6' is doped wlth an LS N-type lmpurity ~uch as phosphorus or arseni~ qelectively and at a high density (for e~ample, above 5 x 101~ cm 3).
Thus, the N-type polycrystalline slllcon fllm 6' i~ obtained.
(b) After re~oving the ma~k oxide ~llm 7, the working of a polycrystalline silicon gate elec~rode i~ done by a o photoetching, and source and drain impurity layers 4 and 5 are ~ormed at a low denslty (for example, below 3~3 x 101~ cm 3) by ~hermal diffusion of a P-type impurity such as boron.
Here, the denslty of the N-type impurity with whlch the polycrystalllne film 6' 1~ doped ln the stage (a) is made a~s 1.5 tlmes or more hlgher t~an the denslty of the P-t~pe l~purity with which the polycry~talllne ~lllcon fllm 6' i~ doped at the time of the P-type lmpurity diffu~ion in the stag (b), whereby the polycrystalline ~illcon gate 6' is held at the ~-type.
~igures 8~( a) to 83(d) lllu~trate another method of ~, 5~3 manufacture accordlng to thl~ inventlon. ~igure 83(a) show~ the same manufacturln~ step ~ ln ~igure 82~a~.
~ b) After removing the mask oxlde film 7, the proces4ing of a polycrystalline ~ilicon gate electrode is done by S photoetching. Thereafter, usin~ the polycrystall~ne silicon gates 6 and 6' a~ a mask, the gate oxlde fllm whlch overlles parts corre~pondlng to sources and dralns to be formed ~s re-moved, whereupon the resultant silicon body is sub~ected to ` oxidation in steam at 750C to 900C for 60 seconds to 600 qeconds. In ~he oxldat50n, the oxide film-~rowth rate o~ the 3ilicon ~urface depend~ upon the d~nslty ~ an impurity contained in the silicon. The oxide film-growth rate becomes very high when the impurity density is at least 5 x 1ol8cm~3, preferably 102 cm~3 or higher.
~5 Therefore, comparatively thin oxide films 8 and 10 of 20 ~o 40 A are reqpectively ~ormed on the surfaces of the parts correspondinO to the source and draln and havlng the comparatlvel~ low i~purity denslty and on the ~ur~ace of -the lntrlnslc polycrystalline sllicon 6. On the other hand, ~0 a comparatively thlck oxide ~ilm 9 of ?0 ~o 200 ~ is for~ed on ~he ~urface of the N-type polycry3talline silicon 3a~e 6' having the comparatively hlgh impurity denslty.
(c) Boron can pa~q through an oxlde film of a thickness of at most 40 g by thermal diffusion, and cannot pass a~ through an oxlde f~lm of a thlCknes~ of at least 70 A.
Therefore, boron i~ ~ub~eque~tly thermally di~fused at 950 to l,OCO C for about 20 minute~. Thu~, the boron penetrates through the comparatively thin oxide films 8 and 10 to r~rm the P-typ~ lmpurity layers 4 and 5 a,ld ~he ~-~ype 3o pol~cry~talline slllcon layer 6. At thls time, the ~ type ~5~3~;3 polycrystalline sillcon layer 6' is protected by the com-ratively thlck oxlde film 9, and it 1~ not doped wlth the ~oron. A~ an alternative expedient, before the thermal dlffusion of boron, the oxlde fllms are etched wlth an etchant consisting of HF : H20 = 1: 99 for 60 seconds, to remoYe the oxlde fllm~ 8 and lO and to leave the oxlde fll~
9 with a thickness of 40 - 50 A. Thereafter, the thermal diffuslon of boron ls carrled out. Thus, a slmllar structure ls obtalned.
JO (d) Thereafter, a pho~pho~llicate glass film ll is formed, contact holes are formed, and alumlnum electrode~
~ ~ ~ 5~ 69~
Accordlngly, the charact~rlstics between the drain currents and gate voltages of the translstors A, B and C or the tran ~stors D, E and F become curves which are parallel to one another and whlch shift in the directlon of the gate voltage axis by the dl~ferences of the Fermi level~ of the polycrystalline silicon materials at the central parts of the gate electrodes o~ these tr~nsistors. Therefore, the dlfferences of the threshold voltages o. the transis~ors can be derived with high precision in referen~e voltaye 1~ generator c~rcu'ts to be described later.
The tempe.ature-d~pendencie3 of the di~Lerences of- .he threshold volta3e of the three sorts of IG~T~ are very small because the temperature~dependenc~es of the dlf~erer.ces of the ~ermi levels of the gate electrode semlconductors are low, ~ lOures 79(a) to 79(e) illustrate a method of manuf-c-turing the CMOSIC shown in Flgure 63.
(a) A low concentrat10n ~-type well reglon 102 ls formed in an N-type silicon body lO~ by the conventlonal ~ selective dlffu~ion proceC~. Subse~uently, a field oxlde fllm 103 is formed. After for~ing a gate oxlde film 104 ln recesse~ of the f~lm 103, a P-type impurlty layers 105 and an .~-type impurity layers 106 are for~ed by the con-ventional selective ion implantation processes.
~5 (b) Polycry~talline silicon gate elec~rodes 107 are ~ormed by the conventional chemical vapor depositlon and photoetching. At thls stage, the electrodes 107 are of the intrinsic semico~ductor.
~c) .~ mas~ o~id~ fil~ }08 is ~ormed on salected areas 3~ ~y the chemical ~apor depo~ition. Usi~g i~ as a ma~k, source ~ 3 and draln layers 109 of ?-channel MOSFET~ a~d ?-type polycrystalline layers 110 are ~ormed by the ~elective diffuslon o~ a ~-type impurity.
(d) A ma~k oxide fllm 108' is formed on selected areas by the chem~cal vapor deposition again~ Us~ng 1~ as a ~ask, source and drain layers 111 of ~-channel MGSFETs ar.d ~-type polycrystalllne layers 112 are formed by the selective diffuslon of an ~-type lmpurity.
(e) A phcsphosllicate glasq fll~ 113 is ~eposlted, ~0 contact holes are formed thereir.~ and alumlnum electrode3 114 are for~ed, Then, the devlce ls completed.
~l~ure 64 shows another embodiment o~ the Qtructure of ICFETq whlch constitute the reference voltage 8enera.or de~rice of thls lnventlon and whlch have gate elec~rodes o~
dlfferent Fermi levels. Here, IG~ETs A 9 B and C have a gate electrode which ls made of ?-type s~licon 7, a gate electrode whose both ends are made of P-type silicon 7 and whose central part ls made of intrlnslc slllcon 4 and a gate electrode whose both ends are made of ?-type silicon 7 and a~ ~whose central part i5 made of aluminum 12, res?ectlvely.
These gate electrodes are oYerlying on the sate oxlde films (S102) 3 which are formed on dlfferent sur~ace areas of an identical N-type slllcon body 1 under substantlally ~he same condltion~. ~urther, the IG~ETs have ~ource and drain layers 8. A~ to the threshold voltage~, when the threshold voltage YT~ of the IGFET A ls made -0.8 V, that of the ICFET B become~
approxlmately -1~40 Y, and that o~ the ICFET C beco~es appro~lmately -1.95 V. They produce dlfferences ~hich are .~ubstantlally equal ~o the differences o~ the ~er~l levels 3~ of the Sl and Al materials at the central parts of the gate electrodes~
Thls embodi~ent has been made with note taken of the fàct that the temperature-dependency of the difference of approximately 1.15 eY between the Fermi levels of the S hi~h concentratlon P-type ~ilicon and the aluDlnum or tne dlfference of approximately 0.60 eV between the ~ermi level of the intrinsic sllicon and the aluminum ls lo~.
?igure~ 80(a) to 80(d) illustrate an embodl~.ent of ~
method of manu~acturln~ a P-channel IC~ET inteOrated cl.cuit /~ wh;ch includes all the IGF~Ts A, B and C sllown ln ~i~ur 64.
(a) ~ thlck field oxlde film (SiO2) 2 havir.~ recesses ls formed on the sur~ace o~ an N-type sllicon body l, a gate oxide film 3 ls formed ln the recesse~, and a polycryst~lllne qillcon layer 4 is de~o lted by the chemical vapor deposition.
IS ~he polycrystalline silicon layer 4 ls of the intrlnsic semiconductor, Further, a ma~k oxide ~llm 6 is formed on a part of the layer 4 by the chemical vapor deposi~ion.
(b) The polycrystalline sillcon layer ls selectlvely remo~ed by the conYentional photoetch1ng process, and a P-~0 type lmpurity such as ~oron ls thermally dl~fu~ed, ~o ~orm .
source and draln layers 8 and P-type polycrystalline sllicon layers 7. At this time, the part of the polycrystalllne silicon layer 4 co~ered with the oxide fllm 6 ls held intrlnslc.
tc) An insulating film 9 such as phospho~illcate a~ glass fllm owin~ to the chemical vapor deposltlon ls de-~oslted, and contact holeY are formed thereln. nt thls time, a cor.tact hole 10 is slso formed in the central par~ of a gate electrode in an area to become an IG~ET ~.
~d) Aluminum electrodes 11 and 12 are for~ed, and a heat treatment ls conducted at ~80 to 540 C .or 30 ~lnutes ~ - 49 -~ ~ 4 S ~6 ~
to 3 hours. Then, the polycrystalline s11icon at the contact hole 10 diffuses towards the upper surface o~ the aluminum layer owing to its alloyin~ reactlon with the o~lumln~m, and a ~tructure ln which the alu~lnu~ and the 3ate oxide film lie.in direct contact is establis~ d.
The method of manufacturlng the ?-channel IG.~T integrated : circult as illustrated in Figures 8C(a) to ~O(d) 1~ also a~llcable to-~he manufacture of a complementary MIS 1nteOrated circuit substantlally as lt is.
O ~he alloying reactlon may be replaced with an e~pedient in which the central part of ~he gate electrode is removed by photoetching, whereupon alumlnu~ iQ brought lnto d~rec~.
contact with ~he gate insulatin3 fl}m.
The reference voltage gener~tor device ba~ed on such lS a cons ' ruction exhlbits a small te~perature-dependency and small manufacturlng devlatlons, so that it can be utillzed for various electronic circults.
Flgure 81(d) shows the ~tructure o~ ETq A~ B, C and D whlch have thre~hold voltage dl~erences based on the ~erml ~O level dlfferences of gate elec~rodes ln accordance w1th another embodiment of thls lnventlon. The I~FET A is a P-channel MOSFET having a gate electrode made of P-type sllicon 11, while the lGr~ET B ls a P-channel M~S~T h~ving a gate electrode whose both end parts are made of P-type silicon 11 and whose central Fart 18 made of N-type sillcon 8. The IG~ET C ~s an N-channel MOSFET havln~ a gate electrode m2de of N-type silicon 8, whlle the ICFET D ls an N-channel MCSF~T having a gate electrode whose bo~h end parts ~re made of N-type silicon 8 and who~e central part ls made of P-type 3D ~ilicon 11. A reference ~oltage generator device Is constructed ~ ~ ~ 5 ~ ~
by employing a voltage baQed on the dlfference of the thre~hold voltagas of the MOSFET3 ~:and B or the MOSF~Ts C an~ D.
~lgures 81(a) to 81~d) lllustrate a method of fabricat-~ng a ~OS lntegrated circult which includeQ the IGF~Ts A, B, C and D.
(a) A P-type well region 2 ls formed ' n an ~-type sillcon body 1, and a thlc~ ~ield oxide fllm 3 having recesses ls formed. Thereafter, a gate ox~de fllm 4 ls forQed ln the l~ rece~ses of the oxide film 3, and a fllm 5 o~ polycrystalllne slllcon bein~ the intI~inslc semlconductor i-q deposited and worked by the photoetchlng process.
(b) A mask oxide film 6 ls for~ed on ~elected areas by chemical vapor deposition. Using it as a mask, an ~5 N-type lmpurity such as phosphoru~ ls dlffusPd into selected reglons, whereby N-type reglonQ 7,tb become the source~ and drains of N-channel MOSFET~ and N-type polycrystalllne layers 8~are formed, (c~ A ma~k oxide film 9 i3 formed on selected areac ao by chemical vapor deposition. Using i as a mask, a P~type impurity such as boron is lon-~mplanted, whereby P-type regl`ons lO,to become the Qources and dralns of P-channel MOSF~Ts and P-type polycrystalllne ~ilicon layers 11, are formed. Here, when using boron, the oxide film 9 ls made about 3,000 A thi~, and an lmplantation energy of 30 to 50 KeY and an lmplantatlon qua~tlty o~ 2 x 1015 to 1 x 101~/cm2 are approprlate. The actlvatlon of the lmplanted lons 1Q suitably done by a heat t.eatment at ~COC for 10 minutes to at l,000C for 30 mlnutes.
3 ~ The diffusion of the N-type l~p~rit~ ln the step ~b) ~51;~63 may be performed after the qtep (c~. In thls case, the ,Y-type lmpurity dif~uslon indicated in the ~tep (b) had better be execu~ed by the ion lmplanta~lon Or phosphorus or the like. When using phosphorus here, the oxide fllm 6 is ~ade about 3,000 A t;~ick, and an lmplantation energy o~ 60 to 100 KeV and an lmplantatlon quantity of 2 x 1015 to 1 x 1016 /cm2 are approprlate. Sultable for the actlvatlo-n of the lmplanted lons 15 a heat treatment ~t 900C for 10 mlnutes to at 1,000C for 30 mlnute^~. By csrrylng out the doplng wlth the P-ty~e impurlty ln thl3 manner, the heat treatment after the doping with the ?-type ~mpurity can be relleved, so that the channel portions can be preYented from beln~ doped wlth the P-type lmpurlty.
(d) After depo~itin2 a pho~phoslllcate a-las~ f'lm 12 ~5 by chemical vapor deposition, contact holes are formed, and alumlnum electrode~ 13 are for~ed. Then, the devlce 1 flnl~hed.
ReIerrlng sgaln to Figure 58, another embodlment o~
thl~ inventlon will now be described. In the figure, a P-channel ~0 MOSFET ~Ql) ha~ a gate electrode made o~ N-type polycry3ta111ne ~illcon 6', and a P-channel ~OSFET ~Q2) ha~ a gate electrode made o~ P-type po~ycry~talline 3illcon 6.
Slnce these ~ETs are manu~actured under 3ubstantially the same conditio~s except the conductlv~ty type~ of the gate electrodes, the dif~erence of the thre~hold voltages Yth ~ both the FETs become substantially equal to the dlfference o~ the Fermi levels of the P type sllicon and the ~l-type slllcon. ~he gate electro~e~ are d~ped wlth .e~pectlve lmpuritles near ~he ~aturatlon denslties, and the ~0 dif~erence become~ ~ub~tantlally e~ual to the energy gap _g ~ ~ ~ 5~,~ 3 of sllicon (approxi~a~ely 1.1 V). The Vth-difference can be taken out at high precision by maklng the channel dlmenslons of both the FETs equal, and it is utilized as a refer2nce voltage source.
~lnce a re~erence voltage generator device ba~ed on quch a con~truction exhiblts a 3mall temperature-de~endency and small manufacturing deviatlon3, it can be used ~`or varlous electronlc ci~cults.
In Fi~ure 58, numeral 1 designates an ~-ty~e slllcon body, /0 nu~eral 3 ~ th1ck fleld oxlde film, numeral 2 a ~ate oxlde film, numeral 4 a P-type qource re~io~-~ and numeral 5 a ?-type draln region. ~ere, the N-type polycrys~alllne silicon gate ~' ha~ a qtructure wh~ch is doped with both an ~-~ype lmpurity and a P-type lmpurlty, the denslty o~ the N-type impurity being 1.5 time~ or more higher ~han the density of the P~type impurity. Alterna~ively, lt has a ~tructure which i~ doped with an N-type lmpurlty, almo3t ~o P-type lmpurity being contained, and neverthele~s, whlch ls self-allgned with the source and draln.
ao The rea~on why the den3ity of the N type i~purlty needs to be 1.5 time~ or more higher than the density of ~he P-type lmpurlty is as follows. In the ordlnary high-denslty impurity doping techniques, the control o~ a denslty ls subJect to ~deviations of (set value + 20 %) or ~o. ~ccordlngly, the a~ rstio between the deviations of the N-type lmpurlty densi.y and the ?-type lmpurity density become~ (1.5 ~ 0.3)/(1.1 ~ 0.2).
Slnce the minimum value of thl~ ratlo becomes 1/1, the ~er~l level o~ the polycry~talllne Qlllcon doped w'th both the N-type and P-type impuritle~ var~e~ greatly.
3~ In order to allow qome extent of manufacturin3 dlsperslon, ~ 53 -~ 3 accordin~ly, the ratlo of the ~mpurlty de~sltle~ needs to be 1.5 or greater wlthout fall.
Figures ~2(a) and 82(b) lllustrate a method of manufac~
turin~ ICFETs for settln~ the ratio of the impurlty densltles at 1.5 or greater.
(a) An N-type sllicon body 1 at a comparatively low l~pur-lty density (for example, below 5 x 1016 cm 3) is ox~dized to form a thic~ oxlde ~ilm 2 for isolating elementq.
After forming a gate oxide ~llm 3 ln reces~es of the fll~ 2, /0 an lntrln~ic semlconductor polycrystalline sillcon ~ilm at 6 and 5' i~ deposlted by chemical vapor deposition.
Further, a mask oxide film 7 13 formed on 8 ~elected area ~y the chemical vapor depo~ition. Uslng the oxlde fll~ 7 aq a mask, the polycrystalline qilicon film 6' is doped wlth an LS N-type lmpurity ~uch as phosphorus or arseni~ qelectively and at a high density (for e~ample, above 5 x 101~ cm 3).
Thus, the N-type polycrystalline slllcon fllm 6' i~ obtained.
(b) After re~oving the ma~k oxide ~llm 7, the working of a polycrystalline silicon gate elec~rode i~ done by a o photoetching, and source and drain impurity layers 4 and 5 are ~ormed at a low denslty (for example, below 3~3 x 101~ cm 3) by ~hermal diffusion of a P-type impurity such as boron.
Here, the denslty of the N-type impurity with whlch the polycrystalllne film 6' 1~ doped ln the stage (a) is made a~s 1.5 tlmes or more hlgher t~an the denslty of the P-t~pe l~purity with which the polycry~talllne ~lllcon fllm 6' i~ doped at the time of the P-type lmpurity diffu~ion in the stag (b), whereby the polycrystalline ~illcon gate 6' is held at the ~-type.
~igures 8~( a) to 83(d) lllu~trate another method of ~, 5~3 manufacture accordlng to thl~ inventlon. ~igure 83(a) show~ the same manufacturln~ step ~ ln ~igure 82~a~.
~ b) After removing the mask oxlde film 7, the proces4ing of a polycrystalline ~ilicon gate electrode is done by S photoetching. Thereafter, usin~ the polycrystall~ne silicon gates 6 and 6' a~ a mask, the gate oxlde fllm whlch overlles parts corre~pondlng to sources and dralns to be formed ~s re-moved, whereupon the resultant silicon body is sub~ected to ` oxidation in steam at 750C to 900C for 60 seconds to 600 qeconds. In ~he oxldat50n, the oxide film-~rowth rate o~ the 3ilicon ~urface depend~ upon the d~nslty ~ an impurity contained in the silicon. The oxide film-growth rate becomes very high when the impurity density is at least 5 x 1ol8cm~3, preferably 102 cm~3 or higher.
~5 Therefore, comparatively thin oxide films 8 and 10 of 20 ~o 40 A are reqpectively ~ormed on the surfaces of the parts correspondinO to the source and draln and havlng the comparatlvel~ low i~purity denslty and on the ~ur~ace of -the lntrlnslc polycrystalline sllicon 6. On the other hand, ~0 a comparatively thlck oxide ~ilm 9 of ?0 ~o 200 ~ is for~ed on ~he ~urface of the N-type polycry3talline silicon 3a~e 6' having the comparatively hlgh impurity denslty.
(c) Boron can pa~q through an oxlde film of a thickness of at most 40 g by thermal diffusion, and cannot pass a~ through an oxlde f~lm of a thlCknes~ of at least 70 A.
Therefore, boron i~ ~ub~eque~tly thermally di~fused at 950 to l,OCO C for about 20 minute~. Thu~, the boron penetrates through the comparatively thin oxide films 8 and 10 to r~rm the P-typ~ lmpurity layers 4 and 5 a,ld ~he ~-~ype 3o pol~cry~talline slllcon layer 6. At thls time, the ~ type ~5~3~;3 polycrystalline sillcon layer 6' is protected by the com-ratively thlck oxlde film 9, and it 1~ not doped wlth the ~oron. A~ an alternative expedient, before the thermal dlffusion of boron, the oxlde fllms are etched wlth an etchant consisting of HF : H20 = 1: 99 for 60 seconds, to remoYe the oxlde fllm~ 8 and lO and to leave the oxlde fll~
9 with a thickness of 40 - 50 A. Thereafter, the thermal diffuslon of boron ls carrled out. Thus, a slmllar structure ls obtalned.
JO (d) Thereafter, a pho~pho~llicate glass film ll is formed, contact holes are formed, and alumlnum electrode~
12 are formed. Then, the fabrication of the device is completed.
~lthough the present method of manufactu~e haY been explalned as to the case of the sllicon gate P-channel MOSr; Ts, qulte the ~ame applles to the case of P-channel l~'OSF~T~ in a ~llicon gate C~IOSIC.
Now, circuits accordlng to e~bodlments o~ thls lnven~lon for deriving the dlfference of the threshold voltaæes Vth of the ~IOS translstors wlll be explaine&.
Although the clrcults described below can become ex-pedient~ for taklng out the dlfferences of the Fer~l level~
~Efn ~ Efp), (Ern - El) and (El - E~p), they are further appllcable as reference voltage generator de~ices whlch. in ~f general, utllize as a reference volta~e a voltage based on the dlfference of the threshold voltages Vth of FETs havlng unequal threshold voltage val~es.
Flgure 6(b) shows a clrcult whlch generates ~oltage~
corre~pondlng to thre~hold voltages of MOS transl3tor Tran~lstor~ Tl and T2 construct the so-called MOS.dlode~
ln ~hich dralns and gates are connected n common.
Io de~lgnates a constant-current source, and Tl and T2 lndicate MOS~Ts which have unequal thre3hold voltages ~I hl and Vth2 as indicated ln ~lgure 6~a) and substantlally equal mutual conduc~ance~ ~. Lettlng the drain volta3e~ of the respective tran~istors be ~1 and V2, Io ~ l/2 ~ (Yl ~ Vthl) 1/2 ~ (V2 Vth2) ........... (21) Therefore, 1~Yl ~ Vth~, ~ 12 Io/~
2 Vth2 + ~2 Io/~ .O........ (22) By takln5 the difference of the drain volt2ges, the dif,erence of the threshold voltage~ can be derived.
As the constant-current sources, sufflclently hlgh I5~ re31~tances may be used~ I~ their characterlstic3 are uniform, dif~usion resistanc~,polycrystalline Si resistances, resistances formed by ion implan~ation, or high resistances formed of MOS transistors can be used.
'~hen, ln this clrcuit, the N+ gate P~¢hannel MOS and the P~ gate P-channel MOS previou ly explained wlth reference to Flgures 58 and 59 respectlvely are u~ed as the tr~r.~l~tors Tl and T2, ~hat difference (~fn ~ ~p) of the ~er~i levels of the N-type semiconductor and the P-type Aemlconductor which is a value substantially equal to the difference as of tne thre-~hold vol~ages can be derived.
Besice3 by maklng the com~csitions of the gate electrode~
different, it is poqs~ble to e~dow the unequal threshold volta~es by, for èxample, implantlnO lons lnto the channels, - 57 ~
~S~3 `:
alterl~ the thicknesses of a doped gate oxlde or gate lnsulatin5 fil~s, etc. When quch a measure 1~ applied to ` the clrcult of Flgure 6(b), the difference of threshold voltages corre~ponding to the implanted quantltle~ of the lons or the dlfference of threshold voltages correspondin, to the quantlties of an lmpurity wlth whlch the gate insulat-ln~ films are doped or corre3pond!n2 to the thicknes~es of the gate lns~atlng fil.~s can be simllarly derived ~5 .he re~erence voltage, ~or example, the ion impl~ntatlon ls ~uch hl~her in the preclsion of the lmpuri~y concentratlon than the conventlonal dlffuslon because the quantity of lmplantation can be ~onltored in the for~ of current. ~13ure 7 illustrates thls situation~
_ven if, lettlng Tl denote the charzcteristlcs of ~OS trans~stors before the lmplantation of lons, they have been lndiYidually dispersed during manufacture and the threshold val~e~ are lndlvldually ~hif~ed by ~Yth on account of the lon lmplanta-tion, the ma~nitude aYth belng the difference o~ both the thre~hold voltage~ is determined by the quantlty of the lon ao implantation and is therefore dispersed to an extremely small extent. It cah accordingly be similarly used as a reference voltaqe with little dispersions of manufacture. More specifically, letting Vthl indicate the threshold voltage of the MOS transistor Tl which is not subjected to the ion ~S implantation, likewise to Equation (15):
COX COX ..~ ... (23) Lettin~ ~QB indlc~te the lncre~ent o~ fixed changes in ~he substrate due ~o the ion implantation, the thre~hold ~oltage Yth2 of the MOS transistor T2 subJected to the ~on lmplantatlon ~, ~5~63 becomes:
V~h2 ~MS 2 ~F COX COX ....... (24) Accordlngly, Vthl - Yth2 - B ,,,,, . . ( 25 ) The temperature variatlon of thls dlfference voltage between the thre-qhold vol~ages ls extremely small because QB 15 almost invariable agaln~t temperature chan~e~.
Addltlonal sreat advantages are that the reference Yoltage can be freely ~e~ by the quan~i~f of ion implantation and that the deYlce can be easlly produced even by a single-channel ~IOS manu~acturin3 proces~.
Fl~ure.~ 8 and 9,show example~ o~ clrcuits wherein an N~-~ate ~T Tl and a P~-sate FET T2 having une~ual threshold voltages as ln the ca~e of Flgures 6~a) and 6(b) are us~d, and ~he ~ET Tl ls connected ln the ~IOS dlode forQ and i~
connected in serleq with the FET T2, to derive the dlfference~ of the thre-~hold volta~es. It is ~up~o~ed thzt the F~T Tl ha~ a ~hreshold voltage V~hl, whlle the F~T T2 haq a threshold voltage Yth2.
Under the condîtions in which a resistance ~1 is su~iciently great as compared wi~h ~he impeda~e oE T
and that a resis~ance R2 is suf~iciently grea~ as compared with ~he impedance o~ T2, Yl V2 ~ Vthl .,~.~..................... ~25) Yl , Vt~l2 ,,,~,.Ø. (27) Therefore, Y2 Vthl Y~h2 ....................... (28) Flgure ll(a) ~how~ a device wh~reln volta~es correspond ~ng ~o the thre~hold voltages of a~ M~-gate ~'OS Tl and a P+-gate MOS T2 are applied to both ~erminals of a ca?acitor ~ - 59 -~5~3 , .
Cl connected to the ~.OS ~ransis~ors, and a voltage held in the capacitor is taken out as a dlfference voltage.
Flgure ll(b) depict~ the operat~ng timlngs. I~OS ?ET~ T5 and T6 are turned "on" by a clork pulse ~1~ to charge the difference voltage of the thre~hold voltages Ythl and Y~h2 of the ~.OS FET Tl and T2 ln a capacitance Cl.
After turning the MOS ~Ts T5 and T6 "off" by the pulse ~1~ a MOS FET T3 is turned nonll ~y a clock ~2 so as to 2round a node ~ of Cl. Since, at thl3 time, the di~ference ~O ~oltage of the threshold volta~e~ ls retained ln C1, the difference potential appears at a node ~ of the ca~acltance Cl as lt i~. In the case of a use for voltage detector circuit to be stated later, the potential of the node ~ at thls t'me can be employed as a reference voltago as i. ls. In or~er to permlt the use in a more ~eneral formJ howe~er, transmlssion ~ates ~6 and T7 are turned "on" by a clock ~3 wlth~n a perlod of t1me in which the high level si~nal of the clock ~2 13 entering, the potential i3 held in a capacitance C2 connected to the non-inverting input (~) of an operational am~lifier 5, ao and the potentlal is recleYed by the so-called voltage foliower ln which lOO ~ of an output is negative~y fed back to the lnverting input (-) of the operation21 amplifler 5. Then, as the output of the Yoltage follower, the dlff2ren^e of the ~ threshold ~oltage3 of Tl and T2 is obtalned a~ a reference a~ voltage when the internal impedance is su~ficiently low.
~lOure lO(a) is a circult dlagram ~howing an embodlment of a dynamlc type dlYference voltage output ~lrc~it which explolts ~he difference of th~ threshold volta3es of an 3 ~ N+-ga~e N-channel MOS Ql and a P~gate N-channel ~OS ~2 ~S~3 In this circult, the gate~ and dralns of the MISF~Ts (Ql' Q2) are lnterconnected, and they are connected to a bias power supply -VDD throu~h load resistors (Rl, R2). A capacitor (C) is interposed between the gate and drain terminals, and the difference component between the threshold voltage~ of the MIS~ETs (Ql' Q2) ls stored 'n the capacltor so as to provide an output. More specifically, a P-channel MISFET
, -~ hich is drlven by a clock pulse (~) i3 incorporated between the gate and source of tne MISFET (~1) of the s~aller 1 thre~hol~ voltage. ~he re~pectlve load re~iYtance~ of the tlIS?~Ts (Ql~ 2)' and the "on" res~ance of the ;~ISFET (~3) is ~ade sufflclently smaller than the "on" res~stances of the ~.ISF~Ts (Ql' Q2)' Owing to such a clrcult a~rar.gement, as shown ln an operating wavefor~ ~lagram of ~igure lC(b), when the cloc'~ pulse ~ ha~ reached a low level to turn the MIS~ET (Q3) "on", the dif~erence -(Y2 - Vl) between .he drain voltages (threshold voltages Vl, Y2) of both the ~1I3F~Ts ~ Q2) is provided ~rom the drain of the ~I~FET (~2) or the terminal of the capacltor (C) remote from the MISF_l (33).
~O The difference voltage output si~il2r to those Or the fore-golng circu$ts are obtalned ~y sampllng lt at the time t~).
Figure 12 shows a reference voltage generator devlce which utlli~es a~ N+-gate MOS Tl a3 well as a P~ -gate MOS
T2 and a capacitance C2 simllarly. A MOS F~T T8 is t~rned ~on~ by a clock ~1~ At thls tlme, a MOS FET Tg is ln the "off" state o~ing to a clock ~2. The potentlal of a node beco~e~ lower than that Or a node ~ by the threshold voltage Ythl of the MOS FET Tl, and the potent~al of a nod ~ beco~es lower than ~hat o~ the node ~ by the ~hreshold volta~e Vtr2 3~ of the M03 FET T2 Accordlngly, the dlfferenGe voltage o.
~ 61 -5~63 both the threshold voltages Vthl and Vth2 i3 charged acros-q the capacitance C2. Subsequently, the l~OS ~T T8 is turned "off" by ~1 and the ~.OS ~ET Tg is turned "on" by ~2 .hen, the difference voltage of the thre~hold voltages ls ~rovldeà
at the node ~ .
Flgu.e 13 shows an operatlonal ampllfier accordln~ to the princ~ple of this inventlon. Tl and T2 designate a differ ential pair constituting a dlfferentlal amplif~er clrcuit, and ~12 and T13 designate active loads of the dlfferential l~ amplifier. A transistor Tll forms a constant-current circult together with translstors T14 and T16. Translstors T15 and T16 cons~itute a level shift output bu~er circuit whose constant-current source load is ~he transistor T16.
Although the example o~ a circuit arrangement based on C-iiOS
is shown in the flgure, the circuit can of course be cons~ructed of single-channel MOS.
In this operational amplifler, the differential pair translstors Tl and T2 co~stitutlng the dlff~rential amplifier clrcuit are especlally endowed wit~ unequal threshold vol~a~es Ythl and Vth2 on the basls of the Fer~i level dif~erence o~
the sa~e electrodes stated before~ the dif~erence of the threshold voltages can be utllized or derl~ed as a reference voltage. This i3 an applicatlon of the operational a~plifier whlch has hitherto not been existent.
~l~ure 14 ~chematically depicts an ordlnary operational ampllfler by picking ~P only the difrerential portion tr.ereof.
It is here assumed that MO~ translstors Tl and T2 have un-e~ual thre~hold volta3es Vthl and Vth2 respectively and tha~
the other characteristlcs such as mutual conductances are 3~ equal. Slgn~ (-) and (+) appearln~ on the input side ~5~6~
sl~nify the invertlng and non-lnverting lnputs, respectively.
Letting V} denote an in?ut voltage of the translstor Tl and Y2 an input voltage of the tran~istor T2, Yl Ythl Y2 Yth2 that is, 1 V2 Vthl ~ ~th2 ,,,------ (29) The output levël changes wlth this lnpu~ voltage conditlon as t~e boundary.
The operatlonal amplifier ls endowed with an lnput ~O offset corresponding to the difference volt2ge of the thres hold voltages, Therefore, when elther OL the invertin3 input (-) and the non-inverting input (~) 1s grounded or connected to a re~erence potential of a power sup^ly, it can be opera~ed as a voltage comparator whose refere~ce voltage 15~ ls the o~fset volta~e. On the other hand, when the output is connected to the inverting lnput terminal (-) to construct a voltage follower clrcuit and the non-invertlng input ter~lnal (~) is grounded as shown ln Flgure 14, the difference of the threshold voltage~ i~ obtain~d at the output Gut. In this case, in order to ef~ect the operation of the operatlonal ampllfier, the transistor T2 needs to be of the depletion mode ~IOS ~ET. For example, in case of using the ?+-gate MOS for Tl and the N+-gate MOS for T2, they may be made the depletion type by subJecting the channel portlons of both a~ the MOSF~Ts to the ion lmplantation under the sa~e conditlons.
~ lgure 15 shows a devlce which can ar~ltrarily set a reference voltage by the use of the opera~ional amplifla~ 'n Figure 14. An output 1~ fed bsck to the lnvertlng lnpu~
through voltage divlder means A5 and R6. Thus, letting r ~sa~3 denotæ the voltage dlvision ratlo R6/R5+R6, the output voltage Y becomes:
Vo 5 ~hl~_~ ,t,h2 ...................... (3C) The volta~e divider mea~s R5 and R6 should de~irably be linear resistance$, but any reslstances may be adopted insofar as thelr cha.acteristics are su~flclently uniform to a permiss~le extent.
~ereas the circuits of ~igures 14 and 15 premise the /~ ~se o~ the depletion type MOS, circuits ln ?lgures 15 and 17 are made operable with enhancement type ~lOS. Cf course, the depletion type MOS may well ~e adopted.
t l`~ewise to the example of ~lgure 14, ~he example o~
Flgure 15 directly feeds an output bac~ to an lnverting 'n?ut ). Lettln~ VDD denote a supply voltage, the output VO
becomes:
Yo ~ ~DD ~ (Vthl - vth2) ............... .(31) Wlth the circults Or ~igures 14 and 15, at least one of the dlfferentlal palr transl~tors needs to be put into the de-ao pletion mode, which necessitates an increase in the number ~f manufacturing steps ln some cases. However, they can derive the dlfference voltage of the thre~hold voltages Yth with reference to the ground poten~lal.
Conver~el~, wlth the clrcuits of Figures 16 and 18, tne ~5 re~erence of the difference ~oltage to be obtained ls not the grou~d,potentlal. However, the conditlon of the operat~ng mode of the ~ET is not imposed.
'~hich circuit form 15 to be adopted may be decided by the merlt or demerlt to whlch more importance is attached.
~0 Llkewise to the example of Fi~ure 15, the example of ~ 3 Figure 17 feeds an output back ~o an lnvertlng lnput (-) through Yoltage divlder mean~ R7 and R8. The output beco~es;
Y -- Y
VO - YDD _ ~ thl_ _ th2 ........................ (32) ~igure 18 shows a voltage detector circuit wherein a reference voltage VR from a referer.ce voltaOe genera~or device ~VG according to this invention whi~h exploits the difference o~ the ~hre~hold ~ol~ages Vth i~ applied to one input of a con~ent'onal voltage comparator `iC and a voltago VD to be detected is applied to the other input, whereby the helght of the voltage to-be-detected V~ relatlve to the reference voltag~ VR can be discrlminatedO
3~n example ln Figure 19 is a vo~tage detector clrcult . wherein a reference volta~e VR fro~ a reference volta~e generator de~ice RYG which ut~lize~ the ~ifference of thres-hcld voltage~ Yth correspondlng to the Fer~i level differer.ce of gate electrodes in accordance with thl~ lnventlon is applied to one input of a voltage comparator VC and whereln a voltage obtalned by dlvidlng a voitage to be-detected V~
with voltage di~lder meanq R~ and Rlo ~s applled to the other lnput. Letting r denote the voltage div~s~on ratio, Vre~
denote the reference voltage and V~en~e the detectlon level:
Vsense ~ ref ,.,,~-. (33) The detection level V~en~e ca~ be arbitrarlly set through the voltage divlsion ratlo r.
An example ln ~lgur~ ~0 ~ ~ voltage detector clrcult whlcn uses the oper~tlonal ampllfle~ with the offset corres~
pondlng to the difference of the threshold voltages Y~ as described with reference to ~igure 1~ and ex~lo~ts the offset '~l'`~;
~ 5 -~ ~ ~ S ~6 3 voltage as a reference ~oltage as explained previously.
Rll and R12 lndica~e voltage dl~lder means as ln the exa~pl e of Flgure 19.
If the voltage to-be-detected YV ls a battery supply voltage ln the example cf ~lgure 18, 19 or 20, t~e volt~e detector circuit can be utilized as a battery chec~er in a 3ystem which uses a battery as a power sup?ly. A concre~e example in whlch the voltage detecto. clrcuit of Flgure 2C
ls applied to the battery checker of an electronlc t1~eplece O 13 shown ln Figure 54, and wlll be described in detail later.
~ / .
/
~, ~ ~ ~ 5 ~ 3 Flgure 21 shows ano~her embodiment of an operational amplifler circult which ls constructed by connectlng in the dlf~erential ~orm N-channel MOS FETs Ql and ~2 havlng unequal threshold ~oltages Vth on the basis of t~e differ-ence o~ ~he Fermi levels of gate electrodes in accordancewlth this inYen~ion. MOS ~ETs Q3 and Q4 operate as load FETs of the di~ferentlal pair MOS ~ETs Ql and Q2' ~nd a ~OS FET Q5 operates as a constant-current scurce of the differentlal pair MOS FETs Ql and Q2.
Flgure 22 shows a dlfferential amplifier circuit which has as its of~set ~oltage the dif~'erence of ~he threshold voltages V~h of MOS transistors Ql and Q2 accordlng to thls invention, Figure 23 show3 the draln current - ~ersus - gate ~oltage characterlstics of the MOS translstors Ql and Q2 ln Figure 2 In thls case, the mutual conductances o~ the MOS
transistors Ql and Q2 constitut~ng the differential pair are designed so as ~o become equal, As the current of a constant-current sQurce CS of the differentlal circul~ changes to IOr Iol and Iol', their points of in~ersections with ~he VGs ~ ~ S characteristic of the translstor ~1 vary to points 1, 1' and 1" and thelr poin~s o~ l~tersectlons with the VGs ~
25 characterlstlcs Or the translstor a2 Yary to points 2 2' and 2n. A~ ~lrst, voltageq YGl and VG2 ar pp to the gates of the respective transistors Ql and Q2 in order to brinB the dlf~erentiaI circuit into ~e 'oalanced state. Hereln, e~en when the curre~t of the cons~ant-30 current source CS has changed from Io to Iot or Iol' in i3 dependently of the tempera~ure, the dif~exence of the vol-tages VGl and VG2 which balance the differential circuit are held substantially constant. In actuality~ the difference volt~ge reflects the difference (Vthl - Vth2) of the threshold Yoltages of the ~ransistors Ql and Q2 as it 1~. Accordingly, the temperature characteristic of the differenCe (~hl ~ ~th2) f the threshold vol~ages of the transistors Ql and Q2 appears as lt is, as the ce (VGl -- YG2) of the voltages ~o be applied to ~he gates of the transistors Ql and 42 in order to pu~
these translstors lnto the bala~ced state.
When the P~-gate and N~-gate N-channel ~iOS transistors . previously descrlbed are respecti~ely used as the transis-tors Ql and Q2' a volta~e of approximately 1.1 V
corresponding to ~he band gap ls obtained. In the case of a silicon semiconductor, this difference voltage has a tempera~ure ~radient of -0.24 mV/C.
m e tempera~ure dependency of the d~fference ~oltage of ~he gate voltages can be nullified by making the values of the conductance-q o '~he transistors ~ aQd Q2 unequal.
It is supposed by way o~ example that ~he temperature depe~den~y of the co~stant-current source CS of the di~ferent~al circuit ha~ a positive grad~ent~ while ~he dlf~erence (V~hl - V~12) of the ~hreshold voltages Ql and Q2" exhlbits a temperature dependency of a negatiYe gradient. As lndlcated a~ Ql and Q~" in ~igure 23, the conductance of Q2" is made smaller than the conductance of Ql t whereby the gate ~0 Yoltage of the translstor Q2 under the balanced state ~5~63 ~arles as lndicated at 3, 3' and 3" in dependence on the temperature, and ~he temperature dependency of the dif~erence of the gate ~oltages of the transistors Ql and Q2" as based on the dlfference of the conductances of ~he transls~ors Ql and Q2" has a positive gradlen~.
By properly combining the magnitudes of the conductances, the to~al temperature dependency can be made zero or can be improved substantially.
When the temperature dependency o~ the cons~a~t-current source o~ the differential circult has a negatlYe gradie~t, the condu~tanee of ~he tr~nslstor Q2 ~ ls made greater than the conductance of the tr~nsistor Ql conver3ely to ~he above, whereby the temperature dependency can be lmproved to zero.
Under the balanced state, the following relations bold among~ the current Io Of the censtant-curren~ source, and the threshold ~oltages V~hl and Vth2, mutual conduc-~1 d ~2 and gate ~oltage~ VGl and VG2 of the respectiYe transi~tors Ql and Q2:
~ (VG~ ~ (VG2 - Vth2)2 , . . (34) VG,l ~ Ve}~, + 12 Io/~l VG2 Yth2 ~ ~ 2 Io/~2 ,..(36) VGl YG2 ~ (Vthl ~ Yth2~ + ~ ( ~ ~` 1 ) ...(37) In ~qUatiQn (37), when ~1> ~2~ ~ - ~ C , ~nd ~hen ~1 < ~2' ~ ~ ~? O> Therefore, the temperature gradient of the second term of E~uation (37) can become -~6 3 both po~itlve and negative.
Figures 24 and 25 show application circuits of voltage comparators each being another embodiment ~ich can reduce the temperature dependency on the basls of S the concept described abo~e, In ~igure 24~ ~iOS ~Ts Ql and Q2 whose threshold voltages Vth are unequal owin~ to bhe difference of t.~e F'erml levels of gate electrodes in accordance ~i~h this inventlon are operated as source follo~rers. ~he balanced state corresponds to the time when the differential input voltage o~ a ~olta&e comparator circuit or opera-tlonal ampllfier clrcu~t C~l Decomes O (~ero) volb, Under the balanced state, the follo~wing relatien~ hold among the threshold voltages V~l and Vth2, mutual conductances ~1 and ~2~ gate voltages VGl and VG2, source voltages Vl and V2 and drain currents Il and I2 of the respectlve MOS FETs Ql and Q2:
Il 3 ~ ~1 ~YGl - V~ Vl)2 2 ~~~ ~2 (VG2 Yth2 ~ V2) ,.... (38) Yl V2 ... (39) Accordingly, Y~l ' Vthl ~ Vl + ~ ... (40) YG2 Vth2 ~ Y2 ~ ~ ... ( ~) YG1 YG2 ~ (Vth1 - Vth2) * (~1/~1 -12 I;~/~2) ...(42) Thus, assuming that Il - I2 a I~ th~ tempera~re dependency of (VGl - VG2) can be made zero by ap?ro?riatel~f ~S~3 setting ~1 and ~2 in conformity with the temperature dependency of I and Ihe temperature dependency of (Vthl -Vth~) qulte similarly to t~e case of the differer~tlal circult.
~ur~her, in this example of the circult, assu~i~g that ~ 2 ~ ~, E~uatlon (42) becomes:
VGl ~ Vc 2 a Yth L ~ V I;h2 + ~ (~ r2 ) ( 43 ) ThereforR, e~n when the currents Il and I2 are set at une~ual values, the tempera~ure dependency o~ ~e nce (VGl - VG2) can be slmllarly made O (~ero) As an example of a constant-curre~t circuit, one as shown in Figure 26 is considered, Xere, when the conductances of FETs Q2 and Q3 are made 1 : n, a curren~
flowing ~hrough ~he ~ET Q3 can be made n.I relatiYe to a current.I flowing through FETs Ql and ~2.
AccordinglY, Il and I2 in Equation (43) can be readily realized by changing the ratio n in the above ` constant-current circuit.
Figure 27 shows an em~odlment of a specif~c form of a reference vol~age generator circuit based on the di~erentlal clrcult of ~lgure 22.
r 41~ Q2' Q3 and ~ enclosed with dotted lines in Flgure 27 con~tit~te a constant-current circuit similar to that in Figure 26, while transistors ~4, Q5, Q6' Q7 and Q3 constltute a difXe~en~ial clr¢uit slmilar to that in ~igure 22. ~ere, the transistor Q6 is a P~-gate ~-channel MOS transistor, and the translstor Q7 is an N~-gate N-channel MOS transistor.
The arrow symbols of the gates represents the N+-gate and ~ 71 -~ 5 ~ 3 the P+-gate dlscrimlnatingly, m e MOS transistors Q6 and ~ have their threshold voltages shifted by equal values by means of the ion implantation or the li~e, and ~he MOS transistor ~ is made a depletlon MOS transistor.
An outpu~ based on ~ransistors Q8 and Qg i~ negatively fed back to the gate o~ the transistor Q~. For an output ~olta~e, ~he o~fset ~oltage o~ the transistors Q6 and Q? can be used as a refere~ce ~ol-tage. Letting VO denote the output voltage and letting in Equatlon (37) V 3 V ~ VG2 = ~ Vth L - V~;~+ j . Vth2 t~lp ~ 6 and ~2 3 ~7, then:
' Vo 3 Vthnt' - Vthp+ ~
In th~s case~ (Vthl ~ Vth2) ls the difference between ~he threshold ~oltages of the P~-gate N-channel ~OS
translstor and the N~-gate N-channel MOS transistor and become substantially equal to the band gap voltage of 1.1 V~ The autput ~ol+aga VO has the form in which ~he correctio~ voltage of the second te.-m is ad~ed to the band gap vol~age.
Letting the mutual conduc~ance of the transistor Ql be ~1~ a~d supposing the drain ~Qltage of the transis-tor Q2 to be substantlally e~al to the threshold voltage Vthn thereof, o ~ ~l~(VDD Vthn)(VDD Vthp) ~ ~~~ (~DD ~ ~hp)2] ~--(45) In addi~ion,.
~ OP (~
~ .
~6 ~oN(tY/L~6~ oN~ Y/L)6 where ~ Op and ~BON denote the mutual conductances per unit area o~ the N-MOS and P-MOS translstors, respectively, Accordlngly, the o~tput voltage becomes:
Vo ~ V~hn+ - V~;hp+ ~ ~ D ~
. _, . .
~(.IY/L) -~I,Y/6 _ 7 -~ -~ L 6 ' (W/L)7 x ~(VDD Vthn) (YDD Ythp) ~ D~ Vt~P) ]
,.,(46) Dlfferentlating Equatlon (46) as to the temperature T, ~ ~ (Ythn~ ~ ~thP~
- ~,/ (W~L) ~ yl (~'r/L) 6 ~(W/L)l ~ (W~)6 (~!L)7 x ~ ~(YDD-Vthn)(VDD-Vthp) ~ ~ (~DD ~h~ ]
.. (47~ -(W/L)6 and (WjL)7 can be set so that a . o may be held.
Flgure 28 shows ~n embodiment of a reference voltage generator c~rcuit which is based on the princlple const-ructlon of Figure 24. A cirouit wi~hI~ dotted llnes in Figure 28 forms the comparator circuit ~ in Figure ~4.
rs Ql' Q2' Q4 and Q~ constltu-.e a constant-current circuit. Currents to ~low through transistors Q3 a~d Q5 can also be made uneq~al hy maklng the ~.
30 ratio~s of t~e conductances o~ the transi~tors Q4 and S~i3 Q6 different relative to the cond~ctance of the transistor Q2.
Here, the transistors Q3 and Q5 are an ~ -gate N-channel MOS transistor and a P~-gate N-channel MOS
transistor respectlvely.
As in the ~oregolng, the output voltage VO is nega-~i~el~ fed back to the gate of the translstor Q~ so as to form ~he voltaqe ~ollower, and the ground potential ls applied to the translstor Q5.
m e temperature dependency of the output vol~age can be made O (2ero) by making the conduc~ances oX the ~ransistors Q3 and Q5 or ~he conduc~nces o the transistors Q4 and Q6 unequal in a¢cordance with Equation (42) or (43), or by comblnlng bo~h these measures By way o~ example, it is supposed that the conduc tances of the trans~s~ors Q3 and ~5 are equal and ~, that the current to ~low through th~ transistor Ql is Io~
and that the ra~i~ of ~he conduc~ances of ~he transis~ors Q~ and Q4 is 1 : n, while the ratio of the conduc~ances of the transistors Q2 and Q6 ls 1 : n'. Thent the output ~0 voltage VO becomes:
YO ~ Vth~ V.~
By ad~us~ing the ~alues of n' and n, the temperature dependency o~ the output ~ol~age VO can be made subst~tlally zero. A further circu~t arrangement ~hich genera~es a re~er-ence voltage and which can reduce to zero or at least improve the temperatuxe dependency o~ the reference voltage~ is shown in Figure 25, in addition to the ~oregoing circuit arrangements.
~0 This circuit is operated with the sources of transistors.
_ .. . ....... ....... .. _ _ .. .. ..
Ql and ~2 grounded.
An example in Flgure 29 is a clrcult of a constant current whlch is determined by the difference of the threshold voltages of MOS FETs Tl and T2 in ac_ordance wlth this lnvention.
The MOS FETs Tl and T2 have e~ual mutual conductances ~, and their threshold voltages have values Vtnl aad Vth2 different from each ot~er owlng to the difference of the Fermi le~els of gate electrodes in accordance ~Jith this invention, I~ a res~stance R20 is sufficiently high as compared with t~e lmpedance o~ Tl~ the drain voltage (3 gate uol~age) ~1 ~ Tl becomes subst&nt~all~
equal to Vthl.
~nhen T2 is in ~he saturation region, a current I2 flowing through 22 is:
IOUT ~ ~~~ (V~hl ~ Vth2) ...(49) An example in ~lgure 30 is a constant-current circult employing a reference voltage ~enerator device RVG which generates a reference vol~age VRE~ Vthl - V~x~) decided by the dl~ference voltage o~ the threshold voltages of MOS F~Ts correspondlng to ~he difference of the Fermi leY~ls o~ the gate electrodes ~hereof in accordance wi~h this i~ventlon,and an ord~nary operatlonal ~mplifier VC. I~ the constant-current c~rcuit, a voltage dL~op IoUtR21 based o~ a curre~t I ~lowlng through a ~iOS FET
T22 is compared wi~h a reference voltage VRE~, and the gate voltage of Tl ls controlled so that both may become e~ual at all tlmes, ~0 IOUtR21 3 VREF-, IOut ~ ~ ~..(50) Here, the reference voltage may be obtained by endowing the operatlonal amplifler VC with an offset and grounding tlle non-inverting input ~+) of the opera-tional amplifier VC as` in the foregoing example of ~iO~ures
~lthough the present method of manufactu~e haY been explalned as to the case of the sllicon gate P-channel MOSr; Ts, qulte the ~ame applles to the case of P-channel l~'OSF~T~ in a ~llicon gate C~IOSIC.
Now, circuits accordlng to e~bodlments o~ thls lnven~lon for deriving the dlfference of the threshold voltaæes Vth of the ~IOS translstors wlll be explaine&.
Although the clrcults described below can become ex-pedient~ for taklng out the dlfferences of the Fer~l level~
~Efn ~ Efp), (Ern - El) and (El - E~p), they are further appllcable as reference voltage generator de~ices whlch. in ~f general, utllize as a reference volta~e a voltage based on the dlfference of the threshold voltages Vth of FETs havlng unequal threshold voltage val~es.
Flgure 6(b) shows a clrcult whlch generates ~oltage~
corre~pondlng to thre~hold voltages of MOS transl3tor Tran~lstor~ Tl and T2 construct the so-called MOS.dlode~
ln ~hich dralns and gates are connected n common.
Io de~lgnates a constant-current source, and Tl and T2 lndicate MOS~Ts which have unequal thre3hold voltages ~I hl and Vth2 as indicated ln ~lgure 6~a) and substantlally equal mutual conduc~ance~ ~. Lettlng the drain volta3e~ of the respective tran~istors be ~1 and V2, Io ~ l/2 ~ (Yl ~ Vthl) 1/2 ~ (V2 Vth2) ........... (21) Therefore, 1~Yl ~ Vth~, ~ 12 Io/~
2 Vth2 + ~2 Io/~ .O........ (22) By takln5 the difference of the drain volt2ges, the dif,erence of the threshold voltage~ can be derived.
As the constant-current sources, sufflclently hlgh I5~ re31~tances may be used~ I~ their characterlstic3 are uniform, dif~usion resistanc~,polycrystalline Si resistances, resistances formed by ion implan~ation, or high resistances formed of MOS transistors can be used.
'~hen, ln this clrcuit, the N+ gate P~¢hannel MOS and the P~ gate P-channel MOS previou ly explained wlth reference to Flgures 58 and 59 respectlvely are u~ed as the tr~r.~l~tors Tl and T2, ~hat difference (~fn ~ ~p) of the ~er~i levels of the N-type semiconductor and the P-type Aemlconductor which is a value substantially equal to the difference as of tne thre-~hold vol~ages can be derived.
Besice3 by maklng the com~csitions of the gate electrode~
different, it is poqs~ble to e~dow the unequal threshold volta~es by, for èxample, implantlnO lons lnto the channels, - 57 ~
~S~3 `:
alterl~ the thicknesses of a doped gate oxlde or gate lnsulatin5 fil~s, etc. When quch a measure 1~ applied to ` the clrcult of Flgure 6(b), the difference of threshold voltages corre~ponding to the implanted quantltle~ of the lons or the dlfference of threshold voltages correspondin, to the quantlties of an lmpurity wlth whlch the gate insulat-ln~ films are doped or corre3pond!n2 to the thicknes~es of the gate lns~atlng fil.~s can be simllarly derived ~5 .he re~erence voltage, ~or example, the ion impl~ntatlon ls ~uch hl~her in the preclsion of the lmpuri~y concentratlon than the conventlonal dlffuslon because the quantity of lmplantation can be ~onltored in the for~ of current. ~13ure 7 illustrates thls situation~
_ven if, lettlng Tl denote the charzcteristlcs of ~OS trans~stors before the lmplantation of lons, they have been lndiYidually dispersed during manufacture and the threshold val~e~ are lndlvldually ~hif~ed by ~Yth on account of the lon lmplanta-tion, the ma~nitude aYth belng the difference o~ both the thre~hold voltage~ is determined by the quantlty of the lon ao implantation and is therefore dispersed to an extremely small extent. It cah accordingly be similarly used as a reference voltaqe with little dispersions of manufacture. More specifically, letting Vthl indicate the threshold voltage of the MOS transistor Tl which is not subjected to the ion ~S implantation, likewise to Equation (15):
COX COX ..~ ... (23) Lettin~ ~QB indlc~te the lncre~ent o~ fixed changes in ~he substrate due ~o the ion implantation, the thre~hold ~oltage Yth2 of the MOS transistor T2 subJected to the ~on lmplantatlon ~, ~5~63 becomes:
V~h2 ~MS 2 ~F COX COX ....... (24) Accordlngly, Vthl - Yth2 - B ,,,,, . . ( 25 ) The temperature variatlon of thls dlfference voltage between the thre-qhold vol~ages ls extremely small because QB 15 almost invariable agaln~t temperature chan~e~.
Addltlonal sreat advantages are that the reference Yoltage can be freely ~e~ by the quan~i~f of ion implantation and that the deYlce can be easlly produced even by a single-channel ~IOS manu~acturin3 proces~.
Fl~ure.~ 8 and 9,show example~ o~ clrcuits wherein an N~-~ate ~T Tl and a P~-sate FET T2 having une~ual threshold voltages as ln the ca~e of Flgures 6~a) and 6(b) are us~d, and ~he ~ET Tl ls connected ln the ~IOS dlode forQ and i~
connected in serleq with the FET T2, to derive the dlfference~ of the thre-~hold volta~es. It is ~up~o~ed thzt the F~T Tl ha~ a ~hreshold voltage V~hl, whlle the F~T T2 haq a threshold voltage Yth2.
Under the condîtions in which a resistance ~1 is su~iciently great as compared wi~h ~he impeda~e oE T
and that a resis~ance R2 is suf~iciently grea~ as compared with ~he impedance o~ T2, Yl V2 ~ Vthl .,~.~..................... ~25) Yl , Vt~l2 ,,,~,.Ø. (27) Therefore, Y2 Vthl Y~h2 ....................... (28) Flgure ll(a) ~how~ a device wh~reln volta~es correspond ~ng ~o the thre~hold voltages of a~ M~-gate ~'OS Tl and a P+-gate MOS T2 are applied to both ~erminals of a ca?acitor ~ - 59 -~5~3 , .
Cl connected to the ~.OS ~ransis~ors, and a voltage held in the capacitor is taken out as a dlfference voltage.
Flgure ll(b) depict~ the operat~ng timlngs. I~OS ?ET~ T5 and T6 are turned "on" by a clork pulse ~1~ to charge the difference voltage of the thre~hold voltages Ythl and Y~h2 of the ~.OS FET Tl and T2 ln a capacitance Cl.
After turning the MOS ~Ts T5 and T6 "off" by the pulse ~1~ a MOS FET T3 is turned nonll ~y a clock ~2 so as to 2round a node ~ of Cl. Since, at thl3 time, the di~ference ~O ~oltage of the threshold volta~e~ ls retained ln C1, the difference potential appears at a node ~ of the ca~acltance Cl as lt i~. In the case of a use for voltage detector circuit to be stated later, the potential of the node ~ at thls t'me can be employed as a reference voltago as i. ls. In or~er to permlt the use in a more ~eneral formJ howe~er, transmlssion ~ates ~6 and T7 are turned "on" by a clock ~3 wlth~n a perlod of t1me in which the high level si~nal of the clock ~2 13 entering, the potential i3 held in a capacitance C2 connected to the non-inverting input (~) of an operational am~lifier 5, ao and the potentlal is recleYed by the so-called voltage foliower ln which lOO ~ of an output is negative~y fed back to the lnverting input (-) of the operation21 amplifler 5. Then, as the output of the Yoltage follower, the dlff2ren^e of the ~ threshold ~oltage3 of Tl and T2 is obtalned a~ a reference a~ voltage when the internal impedance is su~ficiently low.
~lOure lO(a) is a circult dlagram ~howing an embodlment of a dynamlc type dlYference voltage output ~lrc~it which explolts ~he difference of th~ threshold volta3es of an 3 ~ N+-ga~e N-channel MOS Ql and a P~gate N-channel ~OS ~2 ~S~3 In this circult, the gate~ and dralns of the MISF~Ts (Ql' Q2) are lnterconnected, and they are connected to a bias power supply -VDD throu~h load resistors (Rl, R2). A capacitor (C) is interposed between the gate and drain terminals, and the difference component between the threshold voltage~ of the MIS~ETs (Ql' Q2) ls stored 'n the capacltor so as to provide an output. More specifically, a P-channel MISFET
, -~ hich is drlven by a clock pulse (~) i3 incorporated between the gate and source of tne MISFET (~1) of the s~aller 1 thre~hol~ voltage. ~he re~pectlve load re~iYtance~ of the tlIS?~Ts (Ql~ 2)' and the "on" res~ance of the ;~ISFET (~3) is ~ade sufflclently smaller than the "on" res~stances of the ~.ISF~Ts (Ql' Q2)' Owing to such a clrcult a~rar.gement, as shown ln an operating wavefor~ ~lagram of ~igure lC(b), when the cloc'~ pulse ~ ha~ reached a low level to turn the MIS~ET (Q3) "on", the dif~erence -(Y2 - Vl) between .he drain voltages (threshold voltages Vl, Y2) of both the ~1I3F~Ts ~ Q2) is provided ~rom the drain of the ~I~FET (~2) or the terminal of the capacltor (C) remote from the MISF_l (33).
~O The difference voltage output si~il2r to those Or the fore-golng circu$ts are obtalned ~y sampllng lt at the time t~).
Figure 12 shows a reference voltage generator devlce which utlli~es a~ N+-gate MOS Tl a3 well as a P~ -gate MOS
T2 and a capacitance C2 simllarly. A MOS F~T T8 is t~rned ~on~ by a clock ~1~ At thls tlme, a MOS FET Tg is ln the "off" state o~ing to a clock ~2. The potentlal of a node beco~e~ lower than that Or a node ~ by the threshold voltage Ythl of the MOS FET Tl, and the potent~al of a nod ~ beco~es lower than ~hat o~ the node ~ by the ~hreshold volta~e Vtr2 3~ of the M03 FET T2 Accordlngly, the dlfferenGe voltage o.
~ 61 -5~63 both the threshold voltages Vthl and Vth2 i3 charged acros-q the capacitance C2. Subsequently, the l~OS ~T T8 is turned "off" by ~1 and the ~.OS ~ET Tg is turned "on" by ~2 .hen, the difference voltage of the thre~hold voltages ls ~rovldeà
at the node ~ .
Flgu.e 13 shows an operatlonal ampllfier accordln~ to the princ~ple of this inventlon. Tl and T2 designate a differ ential pair constituting a dlfferentlal amplif~er clrcuit, and ~12 and T13 designate active loads of the dlfferential l~ amplifier. A transistor Tll forms a constant-current circult together with translstors T14 and T16. Translstors T15 and T16 cons~itute a level shift output bu~er circuit whose constant-current source load is ~he transistor T16.
Although the example o~ a circuit arrangement based on C-iiOS
is shown in the flgure, the circuit can of course be cons~ructed of single-channel MOS.
In this operational amplifler, the differential pair translstors Tl and T2 co~stitutlng the dlff~rential amplifier clrcuit are especlally endowed wit~ unequal threshold vol~a~es Ythl and Vth2 on the basls of the Fer~i level dif~erence o~
the sa~e electrodes stated before~ the dif~erence of the threshold voltages can be utllized or derl~ed as a reference voltage. This i3 an applicatlon of the operational a~plifier whlch has hitherto not been existent.
~l~ure 14 ~chematically depicts an ordlnary operational ampllfler by picking ~P only the difrerential portion tr.ereof.
It is here assumed that MO~ translstors Tl and T2 have un-e~ual thre~hold volta3es Vthl and Vth2 respectively and tha~
the other characteristlcs such as mutual conductances are 3~ equal. Slgn~ (-) and (+) appearln~ on the input side ~5~6~
sl~nify the invertlng and non-lnverting lnputs, respectively.
Letting V} denote an in?ut voltage of the translstor Tl and Y2 an input voltage of the tran~istor T2, Yl Ythl Y2 Yth2 that is, 1 V2 Vthl ~ ~th2 ,,,------ (29) The output levël changes wlth this lnpu~ voltage conditlon as t~e boundary.
The operatlonal amplifier ls endowed with an lnput ~O offset corresponding to the difference volt2ge of the thres hold voltages, Therefore, when elther OL the invertin3 input (-) and the non-inverting input (~) 1s grounded or connected to a re~erence potential of a power sup^ly, it can be opera~ed as a voltage comparator whose refere~ce voltage 15~ ls the o~fset volta~e. On the other hand, when the output is connected to the inverting lnput terminal (-) to construct a voltage follower clrcuit and the non-invertlng input ter~lnal (~) is grounded as shown ln Flgure 14, the difference of the threshold voltage~ i~ obtain~d at the output Gut. In this case, in order to ef~ect the operation of the operatlonal ampllfier, the transistor T2 needs to be of the depletion mode ~IOS ~ET. For example, in case of using the ?+-gate MOS for Tl and the N+-gate MOS for T2, they may be made the depletion type by subJecting the channel portlons of both a~ the MOSF~Ts to the ion lmplantation under the sa~e conditlons.
~ lgure 15 shows a devlce which can ar~ltrarily set a reference voltage by the use of the opera~ional amplifla~ 'n Figure 14. An output 1~ fed bsck to the lnvertlng lnpu~
through voltage divlder means A5 and R6. Thus, letting r ~sa~3 denotæ the voltage dlvision ratlo R6/R5+R6, the output voltage Y becomes:
Vo 5 ~hl~_~ ,t,h2 ...................... (3C) The volta~e divider mea~s R5 and R6 should de~irably be linear resistance$, but any reslstances may be adopted insofar as thelr cha.acteristics are su~flclently uniform to a permiss~le extent.
~ereas the circuits of ~igures 14 and 15 premise the /~ ~se o~ the depletion type MOS, circuits ln ?lgures 15 and 17 are made operable with enhancement type ~lOS. Cf course, the depletion type MOS may well ~e adopted.
t l`~ewise to the example of ~lgure 14, ~he example o~
Flgure 15 directly feeds an output bac~ to an lnverting 'n?ut ). Lettln~ VDD denote a supply voltage, the output VO
becomes:
Yo ~ ~DD ~ (Vthl - vth2) ............... .(31) Wlth the circults Or ~igures 14 and 15, at least one of the dlfferentlal palr transl~tors needs to be put into the de-ao pletion mode, which necessitates an increase in the number ~f manufacturing steps ln some cases. However, they can derive the dlfference voltage of the thre~hold voltages Yth with reference to the ground poten~lal.
Conver~el~, wlth the clrcuits of Figures 16 and 18, tne ~5 re~erence of the difference ~oltage to be obtained ls not the grou~d,potentlal. However, the conditlon of the operat~ng mode of the ~ET is not imposed.
'~hich circuit form 15 to be adopted may be decided by the merlt or demerlt to whlch more importance is attached.
~0 Llkewise to the example of Fi~ure 15, the example of ~ 3 Figure 17 feeds an output back ~o an lnvertlng lnput (-) through Yoltage divlder mean~ R7 and R8. The output beco~es;
Y -- Y
VO - YDD _ ~ thl_ _ th2 ........................ (32) ~igure 18 shows a voltage detector circuit wherein a reference voltage VR from a referer.ce voltaOe genera~or device ~VG according to this invention whi~h exploits the difference o~ the ~hre~hold ~ol~ages Vth i~ applied to one input of a con~ent'onal voltage comparator `iC and a voltago VD to be detected is applied to the other input, whereby the helght of the voltage to-be-detected V~ relatlve to the reference voltag~ VR can be discrlminatedO
3~n example ln Figure 19 is a vo~tage detector clrcult . wherein a reference volta~e VR fro~ a reference volta~e generator de~ice RYG which ut~lize~ the ~ifference of thres-hcld voltage~ Yth correspondlng to the Fer~i level differer.ce of gate electrodes in accordance with thl~ lnventlon is applied to one input of a voltage comparator VC and whereln a voltage obtalned by dlvidlng a voitage to be-detected V~
with voltage di~lder meanq R~ and Rlo ~s applled to the other lnput. Letting r denote the voltage div~s~on ratio, Vre~
denote the reference voltage and V~en~e the detectlon level:
Vsense ~ ref ,.,,~-. (33) The detection level V~en~e ca~ be arbitrarlly set through the voltage divlsion ratlo r.
An example ln ~lgur~ ~0 ~ ~ voltage detector clrcult whlcn uses the oper~tlonal ampllfle~ with the offset corres~
pondlng to the difference of the threshold voltages Y~ as described with reference to ~igure 1~ and ex~lo~ts the offset '~l'`~;
~ 5 -~ ~ ~ S ~6 3 voltage as a reference ~oltage as explained previously.
Rll and R12 lndica~e voltage dl~lder means as ln the exa~pl e of Flgure 19.
If the voltage to-be-detected YV ls a battery supply voltage ln the example cf ~lgure 18, 19 or 20, t~e volt~e detector circuit can be utilized as a battery chec~er in a 3ystem which uses a battery as a power sup?ly. A concre~e example in whlch the voltage detecto. clrcuit of Flgure 2C
ls applied to the battery checker of an electronlc t1~eplece O 13 shown ln Figure 54, and wlll be described in detail later.
~ / .
/
~, ~ ~ ~ 5 ~ 3 Flgure 21 shows ano~her embodiment of an operational amplifler circult which ls constructed by connectlng in the dlf~erential ~orm N-channel MOS FETs Ql and ~2 havlng unequal threshold ~oltages Vth on the basis of t~e differ-ence o~ ~he Fermi levels of gate electrodes in accordancewlth this inYen~ion. MOS ~ETs Q3 and Q4 operate as load FETs of the di~ferentlal pair MOS ~ETs Ql and Q2' ~nd a ~OS FET Q5 operates as a constant-current scurce of the differentlal pair MOS FETs Ql and Q2.
Flgure 22 shows a dlfferential amplifier circuit which has as its of~set ~oltage the dif~'erence of ~he threshold voltages V~h of MOS transistors Ql and Q2 accordlng to thls invention, Figure 23 show3 the draln current - ~ersus - gate ~oltage characterlstics of the MOS translstors Ql and Q2 ln Figure 2 In thls case, the mutual conductances o~ the MOS
transistors Ql and Q2 constitut~ng the differential pair are designed so as ~o become equal, As the current of a constant-current sQurce CS of the differentlal circul~ changes to IOr Iol and Iol', their points of in~ersections with ~he VGs ~ ~ S characteristic of the translstor ~1 vary to points 1, 1' and 1" and thelr poin~s o~ l~tersectlons with the VGs ~
25 characterlstlcs Or the translstor a2 Yary to points 2 2' and 2n. A~ ~lrst, voltageq YGl and VG2 ar pp to the gates of the respective transistors Ql and Q2 in order to brinB the dlf~erentiaI circuit into ~e 'oalanced state. Hereln, e~en when the curre~t of the cons~ant-30 current source CS has changed from Io to Iot or Iol' in i3 dependently of the tempera~ure, the dif~exence of the vol-tages VGl and VG2 which balance the differential circuit are held substantially constant. In actuality~ the difference volt~ge reflects the difference (Vthl - Vth2) of the threshold Yoltages of the ~ransistors Ql and Q2 as it 1~. Accordingly, the temperature characteristic of the differenCe (~hl ~ ~th2) f the threshold vol~ages of the transistors Ql and Q2 appears as lt is, as the ce (VGl -- YG2) of the voltages ~o be applied to ~he gates of the transistors Ql and 42 in order to pu~
these translstors lnto the bala~ced state.
When the P~-gate and N~-gate N-channel ~iOS transistors . previously descrlbed are respecti~ely used as the transis-tors Ql and Q2' a volta~e of approximately 1.1 V
corresponding to ~he band gap ls obtained. In the case of a silicon semiconductor, this difference voltage has a tempera~ure ~radient of -0.24 mV/C.
m e tempera~ure dependency of the d~fference ~oltage of ~he gate voltages can be nullified by making the values of the conductance-q o '~he transistors ~ aQd Q2 unequal.
It is supposed by way o~ example that ~he temperature depe~den~y of the co~stant-current source CS of the di~ferent~al circuit ha~ a positive grad~ent~ while ~he dlf~erence (V~hl - V~12) of the ~hreshold voltages Ql and Q2" exhlbits a temperature dependency of a negatiYe gradient. As lndlcated a~ Ql and Q~" in ~igure 23, the conductance of Q2" is made smaller than the conductance of Ql t whereby the gate ~0 Yoltage of the translstor Q2 under the balanced state ~5~63 ~arles as lndicated at 3, 3' and 3" in dependence on the temperature, and ~he temperature dependency of the dif~erence of the gate ~oltages of the transistors Ql and Q2" as based on the dlfference of the conductances of ~he transls~ors Ql and Q2" has a positive gradlen~.
By properly combining the magnitudes of the conductances, the to~al temperature dependency can be made zero or can be improved substantially.
When the temperature dependency o~ the cons~a~t-current source o~ the differential circult has a negatlYe gradie~t, the condu~tanee of ~he tr~nslstor Q2 ~ ls made greater than the conductance of the tr~nsistor Ql conver3ely to ~he above, whereby the temperature dependency can be lmproved to zero.
Under the balanced state, the following relations bold among~ the current Io Of the censtant-curren~ source, and the threshold ~oltages V~hl and Vth2, mutual conduc-~1 d ~2 and gate ~oltage~ VGl and VG2 of the respectiYe transi~tors Ql and Q2:
~ (VG~ ~ (VG2 - Vth2)2 , . . (34) VG,l ~ Ve}~, + 12 Io/~l VG2 Yth2 ~ ~ 2 Io/~2 ,..(36) VGl YG2 ~ (Vthl ~ Yth2~ + ~ ( ~ ~` 1 ) ...(37) In ~qUatiQn (37), when ~1> ~2~ ~ - ~ C , ~nd ~hen ~1 < ~2' ~ ~ ~? O> Therefore, the temperature gradient of the second term of E~uation (37) can become -~6 3 both po~itlve and negative.
Figures 24 and 25 show application circuits of voltage comparators each being another embodiment ~ich can reduce the temperature dependency on the basls of S the concept described abo~e, In ~igure 24~ ~iOS ~Ts Ql and Q2 whose threshold voltages Vth are unequal owin~ to bhe difference of t.~e F'erml levels of gate electrodes in accordance ~i~h this inventlon are operated as source follo~rers. ~he balanced state corresponds to the time when the differential input voltage o~ a ~olta&e comparator circuit or opera-tlonal ampllfier clrcu~t C~l Decomes O (~ero) volb, Under the balanced state, the follo~wing relatien~ hold among the threshold voltages V~l and Vth2, mutual conductances ~1 and ~2~ gate voltages VGl and VG2, source voltages Vl and V2 and drain currents Il and I2 of the respectlve MOS FETs Ql and Q2:
Il 3 ~ ~1 ~YGl - V~ Vl)2 2 ~~~ ~2 (VG2 Yth2 ~ V2) ,.... (38) Yl V2 ... (39) Accordingly, Y~l ' Vthl ~ Vl + ~ ... (40) YG2 Vth2 ~ Y2 ~ ~ ... ( ~) YG1 YG2 ~ (Vth1 - Vth2) * (~1/~1 -12 I;~/~2) ...(42) Thus, assuming that Il - I2 a I~ th~ tempera~re dependency of (VGl - VG2) can be made zero by ap?ro?riatel~f ~S~3 setting ~1 and ~2 in conformity with the temperature dependency of I and Ihe temperature dependency of (Vthl -Vth~) qulte similarly to t~e case of the differer~tlal circult.
~ur~her, in this example of the circult, assu~i~g that ~ 2 ~ ~, E~uatlon (42) becomes:
VGl ~ Vc 2 a Yth L ~ V I;h2 + ~ (~ r2 ) ( 43 ) ThereforR, e~n when the currents Il and I2 are set at une~ual values, the tempera~ure dependency o~ ~e nce (VGl - VG2) can be slmllarly made O (~ero) As an example of a constant-curre~t circuit, one as shown in Figure 26 is considered, Xere, when the conductances of FETs Q2 and Q3 are made 1 : n, a curren~
flowing ~hrough ~he ~ET Q3 can be made n.I relatiYe to a current.I flowing through FETs Ql and ~2.
AccordinglY, Il and I2 in Equation (43) can be readily realized by changing the ratio n in the above ` constant-current circuit.
Figure 27 shows an em~odlment of a specif~c form of a reference vol~age generator circuit based on the di~erentlal clrcult of ~lgure 22.
r 41~ Q2' Q3 and ~ enclosed with dotted lines in Flgure 27 con~tit~te a constant-current circuit similar to that in Figure 26, while transistors ~4, Q5, Q6' Q7 and Q3 constltute a difXe~en~ial clr¢uit slmilar to that in ~igure 22. ~ere, the transistor Q6 is a P~-gate ~-channel MOS transistor, and the translstor Q7 is an N~-gate N-channel MOS transistor.
The arrow symbols of the gates represents the N+-gate and ~ 71 -~ 5 ~ 3 the P+-gate dlscrimlnatingly, m e MOS transistors Q6 and ~ have their threshold voltages shifted by equal values by means of the ion implantation or the li~e, and ~he MOS transistor ~ is made a depletlon MOS transistor.
An outpu~ based on ~ransistors Q8 and Qg i~ negatively fed back to the gate o~ the transistor Q~. For an output ~olta~e, ~he o~fset ~oltage o~ the transistors Q6 and Q? can be used as a refere~ce ~ol-tage. Letting VO denote the output voltage and letting in Equatlon (37) V 3 V ~ VG2 = ~ Vth L - V~;~+ j . Vth2 t~lp ~ 6 and ~2 3 ~7, then:
' Vo 3 Vthnt' - Vthp+ ~
In th~s case~ (Vthl ~ Vth2) ls the difference between ~he threshold ~oltages of the P~-gate N-channel ~OS
translstor and the N~-gate N-channel MOS transistor and become substantially equal to the band gap voltage of 1.1 V~ The autput ~ol+aga VO has the form in which ~he correctio~ voltage of the second te.-m is ad~ed to the band gap vol~age.
Letting the mutual conduc~ance of the transistor Ql be ~1~ a~d supposing the drain ~Qltage of the transis-tor Q2 to be substantlally e~al to the threshold voltage Vthn thereof, o ~ ~l~(VDD Vthn)(VDD Vthp) ~ ~~~ (~DD ~ ~hp)2] ~--(45) In addi~ion,.
~ OP (~
~ .
~6 ~oN(tY/L~6~ oN~ Y/L)6 where ~ Op and ~BON denote the mutual conductances per unit area o~ the N-MOS and P-MOS translstors, respectively, Accordlngly, the o~tput voltage becomes:
Vo ~ V~hn+ - V~;hp+ ~ ~ D ~
. _, . .
~(.IY/L) -~I,Y/6 _ 7 -~ -~ L 6 ' (W/L)7 x ~(VDD Vthn) (YDD Ythp) ~ D~ Vt~P) ]
,.,(46) Dlfferentlating Equatlon (46) as to the temperature T, ~ ~ (Ythn~ ~ ~thP~
- ~,/ (W~L) ~ yl (~'r/L) 6 ~(W/L)l ~ (W~)6 (~!L)7 x ~ ~(YDD-Vthn)(VDD-Vthp) ~ ~ (~DD ~h~ ]
.. (47~ -(W/L)6 and (WjL)7 can be set so that a . o may be held.
Flgure 28 shows ~n embodiment of a reference voltage generator c~rcuit which is based on the princlple const-ructlon of Figure 24. A cirouit wi~hI~ dotted llnes in Figure 28 forms the comparator circuit ~ in Figure ~4.
rs Ql' Q2' Q4 and Q~ constltu-.e a constant-current circuit. Currents to ~low through transistors Q3 a~d Q5 can also be made uneq~al hy maklng the ~.
30 ratio~s of t~e conductances o~ the transi~tors Q4 and S~i3 Q6 different relative to the cond~ctance of the transistor Q2.
Here, the transistors Q3 and Q5 are an ~ -gate N-channel MOS transistor and a P~-gate N-channel MOS
transistor respectlvely.
As in the ~oregolng, the output voltage VO is nega-~i~el~ fed back to the gate of the translstor Q~ so as to form ~he voltaqe ~ollower, and the ground potential ls applied to the translstor Q5.
m e temperature dependency of the output vol~age can be made O (2ero) by making the conduc~ances oX the ~ransistors Q3 and Q5 or ~he conduc~nces o the transistors Q4 and Q6 unequal in a¢cordance with Equation (42) or (43), or by comblnlng bo~h these measures By way o~ example, it is supposed that the conduc tances of the trans~s~ors Q3 and ~5 are equal and ~, that the current to ~low through th~ transistor Ql is Io~
and that the ra~i~ of ~he conduc~ances of ~he transis~ors Q~ and Q4 is 1 : n, while the ratio of the conduc~ances of the transistors Q2 and Q6 ls 1 : n'. Thent the output ~0 voltage VO becomes:
YO ~ Vth~ V.~
By ad~us~ing the ~alues of n' and n, the temperature dependency o~ the output ~ol~age VO can be made subst~tlally zero. A further circu~t arrangement ~hich genera~es a re~er-ence voltage and which can reduce to zero or at least improve the temperatuxe dependency o~ the reference voltage~ is shown in Figure 25, in addition to the ~oregoing circuit arrangements.
~0 This circuit is operated with the sources of transistors.
_ .. . ....... ....... .. _ _ .. .. ..
Ql and ~2 grounded.
An example in Flgure 29 is a clrcult of a constant current whlch is determined by the difference of the threshold voltages of MOS FETs Tl and T2 in ac_ordance wlth this lnvention.
The MOS FETs Tl and T2 have e~ual mutual conductances ~, and their threshold voltages have values Vtnl aad Vth2 different from each ot~er owlng to the difference of the Fermi le~els of gate electrodes in accordance ~Jith this invention, I~ a res~stance R20 is sufficiently high as compared with t~e lmpedance o~ Tl~ the drain voltage (3 gate uol~age) ~1 ~ Tl becomes subst&nt~all~
equal to Vthl.
~nhen T2 is in ~he saturation region, a current I2 flowing through 22 is:
IOUT ~ ~~~ (V~hl ~ Vth2) ...(49) An example in ~lgure 30 is a constant-current circult employing a reference voltage ~enerator device RVG which generates a reference vol~age VRE~ Vthl - V~x~) decided by the dl~ference voltage o~ the threshold voltages of MOS F~Ts correspondlng to ~he difference of the Fermi leY~ls o~ the gate electrodes ~hereof in accordance wi~h this i~ventlon,and an ord~nary operatlonal ~mplifier VC. I~ the constant-current c~rcuit, a voltage dL~op IoUtR21 based o~ a curre~t I ~lowlng through a ~iOS FET
T22 is compared wi~h a reference voltage VRE~, and the gate voltage of Tl ls controlled so that both may become e~ual at all tlmes, ~0 IOUtR21 3 VREF-, IOut ~ ~ ~..(50) Here, the reference voltage may be obtained by endowing the operatlonal amplifler VC with an offset and grounding tlle non-inverting input ~+) of the opera-tional amplifier VC as` in the foregoing example of ~iO~ures
13 and 14.
An example in Flgure 31 is a constant-current circult wherein the so-called current mlrror circuit in ~/hlch ~~ ~ranslstors T31 and T33 have ~he same characteri~ticsO
An example in ~gure 32 is an ap~llcation ~herein a re~erence- voltage VREF which is decided by ~he dif~erence voltage of the threshold voltages of M0~ F~Ts corresponding to the dlf~erence o~ the Fermi levels of ~he gate electrodes of the ~SOS FETs in accordance wlth t~ls inventlon is explolted for ~ ~ta~ili2ed power supply clrcu~t, A
reference voltage generator devlce RVG i5 constructed by any of the above-stated several methods acco~dlng to the principle of thi~ ~nvention. A dlvided ~oltage of a stabillzed output ow~ng to volta~e d~vlder means ~13 ~nd R14 and.a reference ~oltage are comparedJ ~nd the gate voltage o~ a controlllng MOS FET T20 is controlled so as to bring ~hem into agreement, thereby to st~bilize the ~utpu~ voltage VOut. Any operational amplifler may be used as lor.g a~ lts characteristic~ are allowableO
In theexample of Flgure 33? the MOS transistor used for ~20 in the example of Fi~ure 32 is replaced with a ~0 bipolar transistor TRl.
A~ example in ~igure ~4 uses the operational amplifler VC as show~ in the exampla of ~lgures 13 and 14, ~rhich has the offset voltage based on the dlfference voltage of the threshold vol~age~ Yth o~ MOS FETs and whose non-inver~ing input t~) is grounded. Tzl may be a MOS tran-sistor, a bipolar transistor or a ~unction field-effect ~ransistor, ~ Flgure 35(a) sho.ws a Yoltage regula~r according to thls invention ~loh is a fur~her lmpro~ement on '~he stabillzed po~er supply oircuits illustrated in ~igul~es 32, 33 and 34, and Figure 3S(b) is a characteristlc diagram thereof.
e ¢ircult arrangement in Flgure 35(a) has ~he construction of a comparing voltage regulator. It differq f~om a conventional voltage comparator in that the lnput characterist~cs of an operational amplifier YC being a voltag~ comparator are asymmetric at ~he lnput ~ermi~als of an non-in~ertlng lnput (+) and an lnvertlng input (-).
That is, this voltage comparator does not balance t~hen the voltage l~evels o~t the non lnverting lnput ~) and ~he in~ertlng lnput t-) are equal to each other, and it balances when a predetermined hlgh iniU~ Yoltage (in the absolute value) i8 applled on the in~erting input (~).
In o-ther w~rds, in thls voltage comparator, ~he lnpu~
levels of the ~on-i~ert~ng input ~3 and the invertlng lnput (-) have an o~fset wi~h respect to the kalance p~
On ~he o ~er hand, accordlng to a con~entional voltage regulator, in case where a~ input ~oltage Vin ls hlgh, an output ~oltage VOu~ depend upon a reerence .
~ ~ ~ 5 ~ 3 voltage Vre~ generated ~rom the reference voltage gene-rator RVC and the di~erence of VOUt - Vi is ~ade large, whereas in c~se where the input voltage Vin is low, VOUt depends solely upon Vi and the dlfference of ¦Yin ~ VOUtl is made s~all. Accordlng to this inventlon, the changlng polnt P between bo~ ~he cases is set at a point o~ Yin ~ Vl wi~h respect to the ~nput voltage Vin (V~ indicates ~he lowest operating voltage of a regulator load L).
Accordlng to the voltage re~ulator o ~his inven-tlon thus constructed, when the input ~oltage Vin is higher than the lowest operati~g voltage Vl~ the laad L
ls operated by ~he output voltage l~ou~ which is higher than the lowest opera~lng ~oltage Vl but lower than the input roltage Vint and hence, ~he power dlss~pation is reduced wh~le ensurlng proper operation. When the input voltage Yi~ i~ low~ ~he load L is operated by the output volta~e which is substantially e~ual to the ~nput Yoltage Vin or somewha~ smaller ~han itJ and hence, a voltage near the lowest operating ~oltage Vl of ~he load L ~o.r the lnput voltage Vin is supplied. S~nce the output voltage VOUt is reduced to a voltage sui~ed to ~he load L for the high lnput voltage V~ hls voltage regula~or can e~dow the load L.wi~h a lou power dissipation and a wide range of input v~ltages Vin.
Such an e~ect of ~hi5 i~vention will be described ~n de~ail with reference tG the g~aph of Flglre 35(b) 1~ comparison with the prior-art v~ltage somparing regu-lator having no offset~
In the figure, the abscissa represents ~ ~ ~ S ~ 3 the lnput voltage Vin,while the ordinate represents the output VOUt and the re~erence voltage Vref. 3traight line ~h indicates VOUt equal to Vin, in other words, a vlrtual curve in the case where the load L ls operated directly by the ~nput voltage Vin without employing ~he voltage generator.
Curve c indicates a reference voltage Vre~l generated from any of the reference vol~a~e generator devices in various forms. Depending on the type thereof, the reference voltage generator circuit device RVG utilizes various parameters o~ semiconductor devioes such as the threshold voltage Vth of a MOSFET, the ~utual conductanoe qm, the forward voltage V~ or backward Zener voltage Vz of a PN-~unction, .' and the current ga~n h~e of a bipolar transistor. There-1~ fore, .the reference ~oltage Vre~l depends upon ~he supplyvoltage Vin according to the vol~age dependency of the parameter ~ Yre~l Y f ~Vi~)].
When the ~eference voltage Vrefl is used as ~he reference voltage of the vol~age comparator circui~ YC and where the comparator circuit VC 1s not endowed w~th the offset as previously sta~ed, ~he outpu~
vol~age Vout becomes e~ual to the reference voltage Vrefl ~nd agrees wi~h the cur~e c, Since the reference volta~e ~refl does not become hlgher than the input voltage Yin, ~he output ~oltage You~ becomes lower than the input voltage Yin in any range, As a result, the lnput voltage ~in at the time when ~he output ~oltage YoUt becomes e~ual to the lowest operating ~oltage Vl of the load (~oin~ R) becomes V2 (V2 ~ Vl) Accordingly, the usable range of input voltages Vin as ~iewed from the load L
~ - 79 ~
5r~
suffers a loss o~ a ~ol~age component corresponding to 2 - Vl I -In order to make this loss small, ln the ~oltage regulator of Figure ~5(a) according to ~his in~ention the operational amplifier VC maklnæ up the voltage compara~or balances when the in~ertlng input (-) has become hlgher than ~he non-in~erting ~npu~ (+) by the offset voltage ~JOlf.
, In considera~ion o~ ~he of~set vol~age ~tJoff of the operational amplifier ~C~ a reference voltage Vref2 (curve d) which is ~maller than the virtual ~eference voltage Vrefl and whlch has a similar characteristlc is employe~ as an actual reference Yol~age Vref, m e ~alues o~ Vref2 and ~Vof~ are set so that a substanti~l co~ari-tage (Vref2 + ~Vo~f~ at an input voltage V3 ln the normal operation may ~ecome e~ual to the virtual reference ~olt~ge Vre~ , namely~ ~hat it may agree with a desired operating point ~.
With such a construction, the volta~e comparator vC
ormed into the voltage follower balances under the condi-tlon o~ VOu~.~ Vref2 + ~Vof~. Since ~nput voltages Vln satisfying the balance condltlon are only Vin ~ Yre~2 ~off' When the inpu~ voltaye Vin is smaller ~han ~ref2 + QVoff)~ ~he oUtput voltage VOUt atso becomes smaller than itt sO that the voltage co~para~v~r VC func~
tions to raise the output voltage VOUt. This feedbac~ controlr how~ver, is limited when ~le eu~put ~oltage VOUt has become equal to the lnput ~-ol~age Vin.
Accor~lngly, with the ln~lexlon poin~ (P) a~ Yin ~ Vref2 ~ AVo~f, the output voltage VOUt is reduced - 80 ~
~ 3 (limited) to Vre~2 ~ ~Voff (curve bl) wh voltag~ Vin is higher than the inflexlon point P, and it is made substantially equal ~o the input voltage V
(curve a2) when Vin l-~ lower than the inflexion point.
If ~he inflexlon point P is the same as or higher than the lowest operating voltage Vl tpoi~t Q) ~th respect to the input ~ol~age V~n (on ~he abscissa), the foregoing locs can be avoided.
This is because the curve bl has a point of intersec-tion ~ith ~he straigh~ llne al owing to ~Vof~.
when the operational amplifier does no~ have the of~se t voltage ~ltoff and ~here ther~ is no point of ~ntersection with the stralght llne al as in the curve d, such a~
ef~ect is not achleved, Al~hough a MOS FET TC ~n Figure 35(a) functlons as a source fo}lower, it is a depletlon mode N channel FET, so that lt makes VoUt a Yln posslble when Vin ~ V
L~Voff ~nd that its ~hreshold ~oltage V~h has no loss, Accordingly, thls ls effectlve when the input ~oltage Vin is sm~ll, Thls, however~. does no~ deny the use of a source follower FE~ Or ~he enhancement mode. The enhancement mode FET i~s very effectiYe when the input voltage is great and the Vth lo~s i~ not a serlou3 problem and when the adoption of a depletion mode FET manufacturing process is di~ficult. In ~ls case, curve a~ (VOUt =
Yin) ~rhi^h determlnes lower output ~oltage~ VOUt (below the changing point P) merely shifts dow~wards by V~h ~VOu~ - Vln ~ Vth)~ and it is slmilarly possible to brlng ~o forth the effect as previously stated on the output -~ 3 ~oltage VOut, In the figure, the N-channel F~T can be replaced wlth a P-channel FET, In th~s case~ ~he ?-cnannel ~ET
functions t~th the source grounded, and the lo s of Vth above described is not involved.
Whe~her the source grounding or ~he source ~ollo~er is adopted as the contro~ling FET does not produce an esse~tlal dl~erence. However, ln case of the source gro~nding, no special consideration for the loss of the threshold voltage Vth, ~s is required for the depletion mode F~T, is necessary. In case of ~he source follower, when the operation o~ the ~ol~age comparison needs to ~e cycllc~lly sampled (for example, w~en the comparat4r is sub~ected to the clock drive in order to render ~he power dissipation low), thi~ F~T is con~enient as it function~ as a ~oltage fo Uower. This is because the output voltage ls determined by the gate voltage if ~he mu~
tual conduc~ance g~ of the ~ET is su~ficiently high.
It is also possible to use a bipolar translstor as the controll~ng transistor. ..-I~ is not necessarily denled ~hat the offset ~Voff becomes a ~unction o~ the input ~ol~age Vin. In settinC
~he ln~lexion poin~ P9 howeverp it is ~esirable that ~off 1~ constan~ wlth respect to Vi~
If a reference voltage which has a fluctuating factor similar to that of the load L is used as ~te reference Yoltage Vref~, outpu~ voltages VOu cor~espond-ing to the characteristlc o~ ~he load L can be ob'~ai~ed, which is also convenient. I~, in ~hat case, Vre~2 ls set at the lowest ~oltage at wh~ch ~le load L can cperate ~ 82 -5 ~ 3 ~n ad~ance, ~Vof~ can be exploited as means of a certain margin, l~hile a construc~ion for bestowing +ihe offset ~Voff and an application circuit explolt the difference of the threshold ~oltages of two MOS FETs according to the pr~nciple of this invention to be described later, another method for endowing the output voltage VOUt with the ipflexion point will be explained here wlth reference to ~he circuit diagram o~ Fi~ure 36~a) and the ~raph of Figure 36tb).
In ~he followin~ description ~nd the ~ra~h of Figure 36tb), all the voltage values shall be absolu~e Yalues, In Figure 36(a), Q107 designates a co~trolling transistor ~hi~h is made o~ an ~-channel depletion mode ~E~ N_cha~nel FETs Qlol -and Q102' Q104 and Q106 construct current mirror circuits. A dra~n current approxlmately equal to the dra~n current f Q
flows through a diode-connected P-channel FET Q104 and a diode;connected N-channel FET Qlos~ The source~
drain ~oltage drops VDs.of the diode-connected P-cha~nel 104 ~ channel FE~ Q105 become approx~mately equal to respecti~e threshold voltages V~hp and Vthn owl~g ~o the high ~mpedance loads ~102 and Q106- Acco g ~, voltages Vthp and (Vout ~ Vthn) are respectively applied to the non-in~ertlng input (~) and the invert.Lng input t-) of an-operat~onal amplif~er VC constructln~ a vo'~a~e comparator (cur~es d and b in Figure ~6(b)~.
Supposing a case where the operational ampli~ier vc has no offset, it balances when bo~h ~e ~nputs of the f~3 non-inYerting input (~) and the lnvertlng inpu~ (-) are e~ual. Accord~lgly, the e~uilibrium condition is (VOu~ -thn) Ythp, that is, VOut = Vthp + Vthn ~mhe outpu~
voltage VOUt is llmited to (V~hp + V~n) w~en Vin ~ Vthp Vthn, and lt becomes substantially equaf to Vin when ~ln ~ Vthp + Vthn. Accordlngly/ in~case where the load L
is constructed of a complementary MOS lntegrated clrcuit (CMOSIC), the operating lower-limit ~olt~ge of the ~OS
ci.c-~ usually becomes (Vthp ~ Vthn) and the output ~ol~age VOUt can compensate for it.
Al~hough the threshold Yoltage to be deri~ed by the dlode-connected IIIOS Q104 and 4105 is inherent threshold voltage, it ls not equal thereto and follows up the draln current of the circuit. O~ course, i~ is favorable to maXe the outpu~ voltage VOUt of the equilibrium poin~ somewhat greater than the inherent (Vthp ~ ~thn)- To that end, ~he mu~ual conduc~ance of the T Q103 may be made small in advance so as to reduce the current to flow through each MOS diode Q104 or Q105' T~e approximate threshold vol ~ e to be derived by the MOS diode premlses the ~low of ~he drain current.
Therè~ore, the clrc~it must be con3tructed so that ~he curre~ts may ~low through both ~he dlodes even when the input ~oltage Vln becomes low.
~he reference v~ltage generator d~vlce according ~o this ~nYention can generate the ~l~f~rence voltage o~
the thre~hold voltages of MOS as the reference voltage, and can therefore be constructed.o~ MISFETs. Accordingly, it can be extensi~ely utilized as various constant-voltage ~.4 5~ ~ ~
sources in monollthic integrated circuits for an electronic desk top calculator, an electronic timepiece etc. made up of MISFETs. As lllustrated by way of exam-ple ln ~igure 37, a li~etlme detector circuit for a battery can be ob ~ ned ~n such a way that the output of the reference voltage generator de~ice (N~-gate N-channel MOS Ql9 P~-gate N-channel ~OS Q2' resis~or Rl) as shown ~n the foregoing em~odiment is applied to one i~put of a voltage comparator circuit (7) as a reference voltage and that a ~oltage ob ~ ned by di~iding a ~Oattery voltage (VDD) by mea~s of divider resistors (Rlo, Rll) is applied to the other input.
In this case, since the battery voltage does no~
lower suddenly, 1~ is desirable to drive the constant-~oltage generator circuit, the voltage dlYider clrcuitand the Yoltage compara~or circuit wi~h clock pulses, thereby to achieve the reduction of current consumption.
Likewise, when the constant-voltage output is not required at all times, the constant-voltage generator circult may be clock-driven as stated ~bove. ...
m e circuit for obtainlng the difference of the threshold volta~es of the MISFETs (Ql' Q2) ls not restrlcted to the construction o~ the above embod1me~', but lt ca~ be modified in various ways and any specific cir-cuit arrangement may be used~
Figure 38 shows another embodiment in whlch thlsinven~lo~ i~ applied to a battery checker.
Ql' Q2' ~ and ~ constitute a constant-current ~ 5~ 4~ Q6 and Q7 constltu~e a d~f~erential circuit. Qll and Qlo serve for the clocX drive to the : - 85 -~ 3 end of the reduct~on of power dls~ipation.
Rl and R2 constitute a battery ~oltage divider circult for setting the detection level of a batter-~voltage. Gl and G2 func~ion to latch an output owing to Q8 and Qg.
Q4 and Q6 are an N~ gate P-channel .~IOS and a ~+-ga~e N-channel MOS, respectively, By ~e lon implantation ot~
e~ual quantities, Q6 is adapted to operate in the deple-tlon mode~
The embod~ment shown in ~igure 38 ~s 'he battery checker for a ti~epiece. When the detection level is set between 1.3 V and 1,5 V, a cur.ent flowing through Q~ has positive gradlent for ~le temperature, and ~he difference (_ band gap ~oltage 3 1 . 1 V) of ~he threshold voltages of Q~ and ~ has a negative gradlent for the temperature. Therefore, ~he dimensional ratio of ~he MOSFETs is set so that ~he conduct~nce of Q~ may become smaller than the conductance of Q4~
Figure 39 -qhows a hlghpreclsion reference voltage generator circult o~ the voltage follower type ~tilizlng an operational ampli~ler. N-channel I~IOS FETs of the P+-gate and N+-gate are used for`Q4 and Q5, respecti~el~.
Furt;her, tlle conduc~ces o~ the FETs are o~a~e dif~eren~
to pro~uce an o~:~set ~roltage. By adJus~ing a resistor 25 Rl outside an IC, a con~tant. current to flow through a constant-c~ent source Q~; ls ad~usted, thereby to ad~us~
t:he o~:~set~roltage, Thus, ~e ~ine a~,ustment of a re~erence ~ol~age ~s made pos~ible, On the other h~d, as a Schm~tt trfgger circuit 30 compo~ed o~ ~lISFETs, a ci~cuit a~ shown in Flgtlre 40(a~
-- ~6 --i3 which has reduced the number of constituent elements has been proposed by one of the inventors.
The circuit shown in Figure 40(a) is such that two inverters are connected in cascade and that a MISFET
(T3) forming a positive feedback circuit is disposed between the input and output of the inverter on the output side. With this circuit, the width of a hysteresis curve (the difference of two logic threshold values VTLl and VTL2) deviates on account of deviations in a supply voltage (VDD), the threshold voltages (Vth) o~
MISFETS, etc. Therefore, when the circuit is applied to an oscillator whose output oscillates-within the voltage width, the frequency deviates disadvantageously.
This invention employs MISFETS formed by a method wherein the threshold voltage of one (T2) of MISF~TS
constituting the first~stage inverter in Figure 40(a) is made higher than that of the other MISFET having the same conductivity type channel by a voltage component based on the difference of Fermi levels. In this way, it is ~0 intended that the width of the hysteresis curve of the Schmitt trigger circuit (the difference of two logic threshold voltages) assumes a fixed voltage (a voltage substantially equal to the Fermi level difference) fluctuating little against the supply voltage, the manu-facturing deviations of the MISFETs, temperature changes, etc.
`In the following, this invention will be described 5~i3 in connection with a ~referred e~o~.iment. Referring to Figure 40(a), the Schmltt ~rlgger circui~ ls constructed of an in~erter 1 to which an inpu~ signal (Vi) is applied, an inverter 2 which receives an output of ~he inverter 1 as its lnput and which forms an output signal (VO) and a MISFET.(T3) whlch ls interpo~ed be~ween an lnput termlnal and a ground termlnal o~ the ~n~erter 2 and which l~;con~rolled ~y the ou~put slgnal~(VO);
T.he MTSFET (T3') aots as p~sltiYe feedback means of ~he output slde inverter 2. The operation of positively feeding the input signal of ~he inver~er 2 to the outpu~ slgnal thereo~ is inseparable from the operatlon of ~he inverter 1 ~orming the input signal. The circui~
operation is more easily understood whe~ expla~ed ln rela~ion with the input side lnverter lr as in the following.
When the input s-l ~ al tVl) ls at a high level (ground le~el~, the o~ù ~ t oS.the input side ln~er~er 1 becomes a low le~e ~ se~the N-cha~nel MlSFET.tTl) 20 is ~on~ and the P~cha~nel MIS~ET (T2~ is "offn~ The N-channel MISFE~ ~T4) of the output side ln~erter 2 rece~Ying this output of the input side inve~ter 1 tur~s lloff" and the P-channel MISFET (T5) turn~ "on", so ~hat the output o~ the output qlde lnverter 2 become~
~he high level~(&round level). For thls reason, the P-channel MISFET (~).falls ~nto the "off" state, ~ nen, under ~hls condlt~on, the input s~gnal ~
intends to change to the low level, the output o~ the in~erter 1 forms an output signal which is dependent upon the le~el ~ the input signal ~Vi~ and ~ich ~s deter-- 8~ -mlned by the impedance ratio of the ~ISF2Ts (Tl, T2), because ~he MISFET T3 is "o~f". The input level of the output slde ln~erter 2 is changed from the low level to the hlgh le~el.
Accordlngly, wheri the outpul; of ~e output s~de lnver-ter 2 is changed rom the high level to the lo~ level .
and this output signal (VO) has exceeded the threshold vo~tage of the`~IS~ET (T3), the MISFET (T3) starts the "on" operation. Owl~lg to the "on" operat'on of the MISFET (T3), ~he output level of the inpu~ side inYerter l is decided by the impedance ratio between the MISF~T
(Tl) and the parallel MISFETs (T~, T3), and it is shifted onto a hlgher le~el side. In other words, upon the "on" operatlon of the MI3~T (T3) ~hlch .ls controlled by the output of the ~utpu~ side ~nverter 2, the posi-tl~e feedback in which ~he ~nput level of the output side in~erter 2 ~s ohanged into the h~gh level side is applied to the input o~ ~he output side ln~erter 2.
Then, the-outpùt s12nal (VO) changes abruptly. Accord-~o ingly, the loglc threshold value (V~L2) in Figure 40~b) is determlned by the thre hold ~olta~es Vthl and V~h2 and mutual conduotances ~l and ~2 ~ the MISFETs (Tl, T2) in Flgure 40(a), That is, YD~ Vthl ~ ~ th2 VTH2 ~ ~ .,.(51) , On t'he other hand, when the input slgnal ~Vi) is at the low le~el, the N-channel MISFET (Tl) of the ln~ut ~ ~ ~ 5 ~ 3 side lnverter (1) ~s "off" and the P-channel MI3FET (T2) ls "on", tha N-channel MIS~3T (T4) of the output slde lnverter Z ~s "on" in the P-channel MISFET (T5) is "off", and the P-channel MISFE~ (T3) ls "on" owlng to the low level of the ~utput signal (VO), so that the output signal of the lnpu~ slde lnYerter 1 is determined by the lmpedance ratlo between the MISFET (Tl) and the parAllel MISFETs (T2, ~3)-Accordingly, in the course ln whlch the lnput signal (V~) changes fro~ the low level to the h~gh level, unlessthe ~input sign~l (Yi) ~ecomes a leY~l hlgher than the loglc threshold voltage (VT~2) in the precedlng operation, the outpu~ slgnal of the lnput side inverter 1 does no~ change to the low level. However9 once thi5 out~ut (the lnput sl~nal for the output side lnverter 2) has begun to change towards the low }evel and to change the outpu~ o~ the output side inverter 2 onto the hlgh level slde, the impedance of ~he MISFET tT~) changes to lncrease. There~ore, the posit~e feedback in which ~0 the change of the output o~ the input slde lnv~ter 1, namely, the lnpu~ ~lgnal of the output side lnverter 2 is promotèd is applied, and the output signal (VO) changes abruptly, ~ere, when ~he P-channel ~ISF~T (T2) has lts gate elec~rode ~orme~ o~ a semiconductor oî
25 ~e opposlte conducti~rity type (N-type) to the conductlvlty type (P-tgpe) of the gate of - the con~rentf onal P-channel MISFET (T3)~ or o~med of an intrinslc {i-type) semlcon-ductor, it ba~ a ~shold ~ro}tage whlch is higher ~an the threshold Yoiiage YTH of the ordinflry MISFET (~r3) by 30 a ~oltage corre pondlng to the dif~erence o~ Fer~ levels e.g. to the dif~erenee of the lntrlnslc level and the Fermi level, respectively.
Accord.~ngly, the logic threshold ~ol~tage (VTLl) in Figure 40(b) ls approx~mately expressed as follows:
VDD ~ Vthl + ~ Vth3 VTLl ' ~ ...(52) ~ ~1 ~2 ~ ~3 i~ he}d by makin~ ~he sl2es of the 1~I3~ET (Tl) and the MISFET (T2) equal~ Therefore, ~he d'L~erence ~YTL2 - YTLl) of ~he two 1O81c threshold values beco~es:
VTI~2 ~ V~ (Vl;h2 Vth3) 1+~
\1 ~1 Accordingly, the dif~erence (VTL2 ~ VTLl) .~ the logic threshold ~alues in Figure 40~b) as~umes a fixed voltage w~ich is proportional to the dlfference (Vth2 -Vth3) of the threshold voltages of ~he MISFET.2 and the MI~FET 3, that is, the difference of the Fermi levels of the gate electrodes of these MISFETs 2 and 3.
An example for-der~vlng the volta~e correspondlng to the dirferen~e of the ~erm~ levels is to utllize ~he difference of the threshold voltages Vth of two kIOSFETs having ~emlcondue~or gate e}e~trodes which ha~e different ~on~uct~vity types and which are formed on gate Sl~j3 lnsulating films ~ormed on an identical semiconduc ~r substrate by an lden~ical process Hereunder, a specific example w~ll be explained, Figure 59 previously referred to represents the conceptual sectional structure of ~he raspec~ive ~ETs, and the stru~ture can be fabrlcated by the MOS manufac~uring process lllustrated i~ Figures 73~a) - 73(f) Hereunder, - for t~e sake of brevity, ~he MOS tra~slstor whose ga~e electrode ls made of a P+-type semlconductor shall be called the "?+ gate ~OS", and the MOS transistor whose ~ate electrode 1~ made of an N~-~ype semi~onductor sh~ll be called the "N~ gate MOS".
~ he dIfference tYthP~ ~ VthN~) ~ the threshold voltages of the P4 gate MOS and the N~ gate MOS becomes 1~ the differen~e o~ the ~erml potentlals of sem~conductors making the gate electrode~ as seen from Equatlon (16).
While ~he above descrlption has been msde by takln~
the P+-channel ~IOS transistor as an example, gulte the same applies to the case of the N+~channel ~iOS transis~or.
Besides, qulte ~he same applles to the i-type gate MOS
~hose gate electrode ls made of an lntrlnsic semiconductor, Figure 41 shows a Schmltt tr~gger clrcult according to another embodlment o~ ~his in~ention. The point of differe~ce from the embodlment o~ Figure 40(a) is ~hat an input lnverter 11 lncludes a P~-gate P-channel depletion ~ype MOS translstor Tll for a load, a P~gate P-channel ez~n~ement type MOS transistor Tl~ or drlve and an N+-gate P-channel enhancement type MOS trans~stor T13 for feedbac~, and that an output inYerter 12 includes a P+-gate P-channel depletlon type MOS tr2nsistor T14 ~or ~ 3 a load and a P~-gate P-channel enhancement type MOS transis-tor T15 ~or drive. It is identlcal that the difference of loglc threshold ~alues becomes a constant voltage propor-tional ~o the difference of the ~ermi levels of the gate electrodes of the MIS~ET 12 and MISFET 13.
Now, an osc~llator wlll be descrlb d as a~ example of appllca~lon o~ ~he Schmltt ~rlgger cLrcuit of thls entlon.
~ gure 42 is a c~rcuit diagram of an oscilla~or ~o which the Schmltt trl~ger circult of this in~ention ; is applled. A part enclosed with do~ted lines in Figure 42 ls the 3chmitt trlgger clrcuitO An outpu~ o~ the Schmitt trigger circuit (STC) becomes an input of an inverter 3;, an output o~ which becomes an inpu~ of the Schmitt trigger ¢lrcult tSTC).
Upon closure o a supply ~oltage, the leYel of a point (d) proceeds towards ~he Ie~el (-~DD) gradually.
When lt has exce~ded ~he threshold voltage (VTL~) of the Schmitt trlgger clrcuit (STC), the potential of a point (f) changes ~o the ground voltage, an~ the potential o~
a polnt (g) chsnges to ~he supply ~oltages (-VDD). Then, a~ the point (g) is the 1nput of the lnverter (3), a MISFET tT4) turns "on"J and the po~entl~l of the polnt (d) pr~eeds towards the ground voltage lmmedlatelyO
25 When the level of the point (d) ha~ become ~elow the logic threshold Yoltage ~VTLl) o~ the Schmitt trigger clrcult (STC), the ?ote~tial of the point (f) changes to the ground vol~age, and the voltage of the point (g) changes to the supply ~oltage (-VDD). Therefore~ ~he MISFET (2 30 of the succeeding 'ln~erter (3) tuxns "off", and the .
~ 6 3 level of the point (d) ls charged accordlng to a tlme constant CR which is determined by a resistor (R) ar.d a capacitor (C) connected to the point (d). When ~he po~ential of ~he poi~t (d) gradually approaches the supply voltage (-~DD~ and has exceeded the threshold voltage (VTL2) o~ the Schmitt trigger circuit (STC), '~he potential of ~he poi~t (~) changes to the ground potential, and the potential of the point (g) changes to the supply ~oltage (-~DD)~ Thereafter, ~he in~ersiorls are simll~ly repeated to cause oscillat~on. Since the potential of the point (d) reciprocates betweer, the ~o logic threshold ~oltages (VT$l, VTL2) o~ the Schmltt trigger circul~ (STC), the oscillation frequency of the oscillator is determined by the speed at whl~h charges are stored in~o or dlscharged ~rom the capacitor ~C) by ~he reslstor (R) or ~he MISFET
(T4). Assumlng now that ~he resistance (R~ is suf~iclently greater than the lmpedan¢e of the MISFET (T4)9 the oscil-lation ~requency of the oscillator circult is determined by only R and C~ a~d ~he oscillation ~f a ~re~uency which ls stable agal~st f~uctuations in t~e su~ply voltage, temperature changes, manufacturing deviations, etc, When the resistor (R) i~ mounted outside the inte-grated clrcuit, only one pin suffices for the integrated clrcuit of the oscillator circuit, and the stable oscil-latlo~ ls realizable under such a condltion.
The resistor (R) may be any of a dlffuslon resistor,a resistor owi~g to a MISFET, etc, Howe~er, when a reslstor of sufficle~tly small devla~on ls formed in ~n integràted circuit, the oscllla~or oircuit ca~ be entirel~
contained therei~.
g ~ _ 1 ~ ~ 5~ ~ ~
Flgure 43 ls a circu~t diagram show~ng an example of an oscilla~or circuit utlllzing the Schml~t trigger clrcuit (STC) as shown in Figure 41 in which the wldth of hysteresis is coRstant according to thls invention.
A third lnverter 3 is conne~ted to the input of the . Schmitt trigger circult ~STC), a fourth inverter 4 is connected to ~he output of the Schmitt trlgger circuit (S~C),. and a resls~or (R) ~nd a coupling capacltor (C) for determinin~ the oscillatlon ~requency are connected ~o ~he inpu~ of the thlrd in~erter 3.
Control of Thre~shold V ltage The threshold ~oltages (Vth) of MOSFETs being discrete elements in a MOS lntegrated circult lorm an ~' lmportant parameter whiGh determlnes the characteristics f the LSI. The threshold voltage Yth undergoes a great deviatlon due ~o the manufacturi~g pr~cess and a grea~
change dependlng upon the temperature, and the control of Vth is a dlfficulty in the manufacture of the MOS LSI.
In thls ~nventlon, as ~hown by way of example in ~igure SO, a bla~ voltage VBB is applled to a siIicon substrate of a MOS memory IC to redu~e parasitic capaci-tance In order to obta~n the bias vol~age VBB, a substrata bia~ generator clrcult SBGC is employed. me substrate blas generator clrcult SBGC has an arrangement 25 whlch is lllustrated ln Flgure 47, In ~his lnvention, ~e comparator employing the difference o~ the work functions of the gate electrodes of MIS FET~ as previ~usly s~ated i9 used ln the substrate blas genera~or circult S~GC so as to co~trol V~ into a constant voltage.
~ 95 -~5~3 Yth c~ange~ in dependence on the substrate bias V~B, and ls expressed by the followlng equation:
Vth ~ V~ho ~ ~ (2 0F ~ ~ VBB I ~) where VthO denotes V~h when the substrate bias ~oltage VBB - O V, K denotes the substrate effeet constant, and 0F
denotes the Fermi level. m erefore, Vth is controllable by varylng the substrate blas VBB. ~ substrate blas voltage generatlng circuit SBGC shown ln Figure 47 has a ~th sense portion 471, a comparator 472, an oscil-latlon clrcuit 473 and a waveform shaping por~io~ 474.
m e osc~llstion clrcuit portion 473 may be replaced with another oscillatlon ~ircuit. The wave~orm shaping por~ion 474 is composed of two MOS diodes Ql and Q2 and a capa-cltor Cl, and it ~u~ctions to drawlng out charges of VBB
to the earth poi~ by a pumplng ac~lon, Owing to the pumping action, YBB is ~rawn towards a nega~ive voltage.
age VBBM of IVBBI is determined by a point at wh~ch the drawlng-out vol~age owlng to ~he pumplng act-lo~ and the substrate leakage current are stabilized.
As long as the os~illatlon clrcuit ls operatin~ VB~ i5 held at the stable point VBBM. After stop of the oscll-latlonl howeYer, the charges o~ the substrate leaXs due to ~he substra~e leakage current and YBB approaches the ground level. ~hen ~BB ha~ become close to the ground level, Vth lowers..
The comparator portlon 472 in Figure 47 exploits the dlfference of the Fermi levels of the ~ate electrodes, and an example ln the N-channel process ~s show~ in Flgure 21, m e comparator portion 472 employs an intr~hsic silicon gate MOS as ~ ln Flgure 21, and an N
- 96 ~
~ ~ ~ 5~ ~
gate MOS as Q2. These are depletion type MOS. Therefore, ~his comparator e~fects ~he in~ersion when a voitage of 3 0.55 V has been put lnto an in~erting input (-).
The Vth sense por~lon 471 in Figure 47 is composed of a resistance and a dlode-connected ~iOSFET ~ ere, ~he reslstance may be either a polyc~ystalline silicon dlffused layer reslstance or a MOS resistance, and the resls~ance v~lue ls set so that an output may become 0,55 V when Y~h ~ Q3 has become 0.55 V. Now, when the substrate bias vol~age YBB ls close to the grou~d level and Vth OL ~3 is below 0,55 V, the (-) input voltage of the comparator portion becomes below 0.55 Y, the output of the comparator becomes "1" and the oscillation circult continues to operate. '~hen the substra~e blas Yoltage VBB approaches VBBM and Vth rises and exceeds 0.5? V, the comparator output becomes "O", ~he oscillation ceases and ~he substrate blas ~oltage VBB becomes close to ~he ground level due to the leakage. That ls, since a ~eedback loop is ~ormed, Y~h is controlled ~o th~ s~able point by this substra~e bias generator clrcult SBGC, The voltage O,55 V ob~ained in the comparator portion 472 is 1/2 of the energy gap, which ch~nges lit~le against temperature changes, manufac-turing dispersions and supply voltage fluo~uations, l~erefore, it becomes possible to control Vt;h at a very high preclslon~ and a MOSLSI whlch is wlde in the tem~e~a-~ure margln, the ~anufa~turlng process margin and the power supply margin ls ob~alned, ~s will be stated later, also tn point of the process, the lntrln~ic silicon gate MOS Ql f the comparator portlon 472 can be obtained.
by quite an identical process to that ~or obtaining a ~S~3 . .
. .
. .
high resistance load R in a memory cell shown in Figure 51, so ~hat the control of V~h can be readily realized wlth the prlor-art process.
:` Level Shift Cir.puit In case w~ere a 5 V power supply is employed as a power source ln a MOSLSI and where Slgnal3 from a TTL
logic circuit are employed as lnputs, ~he outputs of the TTt- logic circuit be¢ome 2.0 V as a high level and 0.8 Y
as a low le~el, In conYerting the TTL sig~als in~4 the ~!OS
levels, it has heretofore been carried out to ~ke ~he ratios of inverters in an input portion and to convert them into tbe MOS le~els. Howe~er, there has been the probl~
that the inpu~ level margin becomes small on account of the disper~ion o~ Vth and tem~erature changes.
Flgure 45 shows a TTL-~ MOS slgnal lèvel con~erter clrcuit wbich employs ~he reference ~oltage Yre~ generated from the refere~ce Yoltage generator clrcuit utilizing the di~erence of the Fermi le~els of the gate electrodes as pre~ously described. The slgnal level converter circult in Figure 45 i preferably applied to ~he address buffer clrcults XAB and YAB o~ the MOS memory shown ~n Figure 50. A~ the ref.e~e~ce Yol~age Vref, ~he reference ~oltage of 1.4 Y i~ genera~ed by the foregoing reference voltage generator circult o~ ~igure 15. A differential ampllfier employ~ng MOSFETs in Figure 44 ls employed as an ampllfier (~P) ~n Flgure 45, and an lnput buffer in which the log~c ~hreshold volta~e of ~n input ~s 1.4 Y
equal to ~he reference voltage Vr~f i~ prepared. Wl~h ~he present method, the TTL - ~M~S sign21 le~el converter circuit is obtained.
Alternatively, a signal level conver~er circuit w~hich has the logic threshold voltage of 1.4 Y can be obtalned by employing the circuit shown in F~gure 13 as the ampll~ier (A~) in Flgure 45. The inphase lnput (+) ~ is grounded as shown in Figure 14, and an address signal Ao - A4 ls applied to the antiphase input (-~0 As the translstor~ Tl and T2 depletion type MOS ~s are used. By making the threshold voltages Vt~l and V~h2 of the respective FETs unequal, ~e operational.
amplifler is endowed with an i~put offset vol~age of 1.4 ~.
A clrcult in Figure 46 intends to al~ays hold the logic threshold voltages of loglcal clrcuits such as inverter cons~ant against changes in the service supply 1~ voltage, the threshold voltages of ~IOS trans~stors, tem-peratures,.etc.
An inverter 1 composed of Q2 and Q3 and an inverter 2 composed of Q5 and Q6 are especially pro~ided wi~h ~IOS
FET~ Ql and Q4 for controlling logic thresholds, respec-tively.
A logic threshold detector circuit 3 ~ich is composedof a con~rolling MOSFET Q~ and an lnrerter tQ8, Qg) with its lnput and output coupled i~ constructed so as to be simllar to the i~verters 1 and 2 s~ated above tthe patter~ size ratios of MOSFETs are equal)~ ~rln2 to the coupling of the input and output of the inverter (Q8~ Q9)~
Just the logic threshold voltage is obtalned, CMPl lndicates the comparator circ~ preY' ou~ly ~tated with reference to Figures13 and 14 which has ~he ~o reference Ycltage Vref as the o~Lset o~ the dlf~erentlal ...
;363 circuit. The comparator clrcult CMPl compares the logic threshold an~ the reference voltage possessed therein, and control3 the gate Yoltage of the controlling MOSF~T
Q7 so that the dif~erence of both the voltages may become substantlally O (zero).
More speclfically, i~ the logic l~hreshold ~ the reference ~oltage (Vref), the output of ~MPl becomes a hi~h level, and the equivalent resistance of Q? lncreases and this t~ansistor functlons in the d~rectlon of lowering ~he logic threshold, In case where the logic threshold ~ the reference ~oltage (Vref) t` the converse ls true.
Both the voltages fall lnto the e~llibrlum state when they are e~ual.
~ The gate voltages o~ the controlling ~OSFETs Ql and Q4 ar,e common wlth the gate voltage of the controlling MOSFET Q7, and the former transistors and the latter ~ransi~tor a~e in the similar relatlQnship. Thus, ~he loglc thresholds o~ the in~erters 1 and 2 become e~ual to the re~erence ~oltage, and ~ery stable in~erter charac-teristlcs are exhiblted.
As stated at the beglnning, this is not restr~cted o~ly to the inv~rters, but is sim~larly applicable ~o the o~her logical circuit~ such as NAMD and NOR.
mis ls readily applicable to the case of in~erters and the like logic~l circuitQ of ordlnary single-channel types, not the CMO~ construction, These clrcults are useful as input in'erface circuits which can dlgitally process slgnals rellably especially when the ranges Qf input le~els and logic amplitudes are narrow.
" j - 100 -~5~3 :
.
There wlll now be explained specific examples in ~hich the reference voltage generator means accordlng to this invention ls applied to a status setting circult (an auto-clear circult) for electronic devices.
Flgure 48 i~ a circuit diagram showlng an example of a sta~us setting circuit, ~h~ch is a fllp-flop circult constructed of two in~er~ers each including ~wo MOS~ETs.
Referring to t~e ~igure, in case where potentials at polnts a and b are O (zero), both the MOSFETs Tl and T3 falls into the "ON" state upon closure of a power supply (-VDD) because they are N-channel MOSFETs, Simultaneously with the closure of the supply voltage, the polnts a and b change towards the supply ~oltage (-VDD). At ~his tlme;
the Fermi levels of the gate semiconductors of the N-channel MOSFETs Tl and T3 differ from each other, and ~he ~hreshold ~oltage Vth3 of the MOSFET T3 ls a~out three time~ gre~ter than that Vthl of ~he ~O~FET Tl (example:
Vthl ~ 0.45 V, V~h3 Y 1.25 Y). m erefore, in the course of the fall of the supply vol~age, the MOSFET T3 turns "OFF" previously, Since ~he MOSFET Tl continues to be ln the "ON" stste~ the points b a~d a are respectively stabi~
lized at -VDD and the ground potential.
In case where, wlth the power supply (-YDD) disconnec-~ed, the pol~t a i9 at O V and charge3 remain at about 1 V
at the point b, T3 ls in the "OFF" s~ate till VDD , Yth~
ln the course of the fall of the supply ~oltage, and the MOSFET Tl ialls lnto the '10N" state at ~V~D ~ Vthl-Therefor~, even when the polnt a has been O Y and ~he point b has been about 1 V (or up to VthN o~ T3) ln the inltial state, the point b becomes VD~ and the point a ~ ~ ~95~ ~ 3 becomes O V in the stable state. Further, slnce all the FETs are constructed o~ E(enhancement)-IIOS~ETs in the present circuit, the current consumption in t~e stable state is almost æero.
Fl~ure 49 is a c~rcuit diagram which shows ~n example of a status setting circuit having heretofore been proposed. Referring to ~he ~lgure, the threshold vol~age Vth of MOSFETs T2 and T4 are equal to each other, a~d an N-channel D (depletion) MOSFET Tl ls inserted in order to increase the stabillty of a latch circui~. Owlng ~o t~e D-MOSFET, upon closure of the power supply (-V~D), the point a falls simultaneously with ~ha power supply without fail, and the point b does not tu~n "ON" unless the supply ~oltage falls to Vth of the MOSFET T4, so that the point a and the point b become -VDD and O V ~n the stable state respecti~ely. Slnce, however, the r-MOS~ET ls lnserted between the point a and -VDD in the present cir-cuit, ~he P-~IOSFET T3 turn~ "ON" when the s~ate in whlch the point b is -VDD and the polnt a ls O V (R23ET) is sub-sequently established from some reason, and a ~.~. path due to ~ a~d T3 arises to result in a high current consumption. In contrast, with the 3tatus setting clrcult of this invention as shown in Flgure ~8, the status settlng can be reliably done and the current consumption is ~ery low as described above, a~d hence, effective status setting means can be proYided.
Nowt ~n embodiment in ~hich thls lnvention is applied to a semiconductor random access memory (~I) will be descr~bed.
In general, in a storage de~ice constructed of S~63 a static RAM, the voltage control of lowerlng a supply voltage is carried out in order to reduce power dlssipa-tion at the time when the storage device is not used tstand-b~ status) Thls is called ~he data retent~on ~ode.
S In thls case, a slgnal voltage is lowered simultane-ously with the supply voltage~ In this regard, s~noe a power supply llne has a greater time constant ~han a signal line, the sig~al ~oltage lowers to a predetermined ~alue faster, Usualiy, ln a semiconductor RAM, a read control slgnal is set at a supply vol~age leYel, a write control signal at a reference voltage level, and a chlp select signal at a reference potential le~el.
In the data retention mode, therefore, the level of the control slgnal lowers faster than the supply volt~ge, so that the read control si~nal becomes ~he wrlte control signal le~el lns~antaneously and that ~he chlp select si~nal ls formed. For thls reason, the write operatlon is ef~ected instantaneo~sly, and the information of a blt selected at that time ls destroyed.
In order to solve thls problem, in a RAM construc~ed of field-effect transistor of a single cha~nel, it ls considered to dispose a tlme constant circuit for making the tlme cons~ant o~ the signal llne greater ~ti~h thls measure, however, an external clrcult is requlred, and the control signals are ad~ersely affected.
In a ~-MOS (complementary MOS) lntegrated cireui~, a p-n-p-n element is prone to be formed on accoun~ of the structure thereof. Therefore, ~rhen the slgnal ~ol~age is made hlgher than the supply voltage~ such a p-n p-n element operate~ and a great current flows between the supply voltage and the re~erence po 4ential . ~or th~s reason, a tlme constant circuit wi~h which the sign~l vol~uQge and ~he supply voltage lower at the same time must be selected ~or the C-MOS memory.
These fact3 are serious problems in the design and manufacture of storage devices on ~he side of the user of memory chips.
In ~his regard, lt ls deslrable that a circuit for sensing the lowering of the supply voltage is contained ln the same chip as that of the R~l. Howe~er, MOS~ETs on the semlconductor ch~p have ~he tempera~ure dependency of threshold voltages V~h, manufacturing de~atio~s, etc., and lt has been di~icult to obtain a detection voltage necessary for ~he senslng at hig~ precislon.
Hereunder, this inYention will be concretely descrlbed along an embodiment Figure 52 ls a block dlagram of a statlc type semi-conductor memory lntegrated clrcult device showing an embodiment o~ this in~ention.
In the figure, 1 designates a memory matri~ (64 x 64 bits) circuit which is constructed of static memory cell~.
2 designa~es an X-decoder circuit. It discerns an informatlon pattern assigned by a row selec~ signal (Ao - A4) and applled through a buffer clrcu~t BC, to assign a row-(X~ line of 1/64.
3 indicates a Y-decoder and input/output circuit.
This circult 3 discerns an information pat~ern assigned by a column select slgn 1 (A5 - ~ ) and appl~ed through a buffer circuit BY, to asslgn a column (Y) llne of 1/64.
~5~3 It also gi~es the assigned column line of ~he memory matrlx an input data applied through gates t~a~ It also provides an output data from the assigned column line to ter~'nals (1/01 - 1/04) ~hrough gates RB.
4 indicates an input data control circuit, which gives the input/output circuit the input data to-~e-written, (1/0~ 0~) lnd1cate irput/output t~rminals.
(~) denotes a chlp sele¢t signal, which indicates the selection of th~s chip by the "0" level i.e. reference potential level.
(WE) denotes a write/read con~rol signal. It si~nifies the write operatton when ~t is at ~he "0" level i,e. Lhe reference potential level, while lt sl~nifles the read ' operation when it is at the "1" level i,e. supply voltage level.
5,6 designate gate circuits which are alternately controlled by the control signals, That is, only when (~) is "0", the gate circuits are controlled by either "0" or "1" of (WE), to execu~e ~he write or read operation, 7 designates a voltage detector circuit. It detects the data retention de on the basis of the fact that the supply ~oltage has become below a predeterm1ned voltage, and lt controls the gate circuit 5 so as to 2S 1 nh~ bit the (W~) at that time. Thus, the malf~nction as previously described is prevented, An example of the concrete arrangement of the voltage detector circult 7 is shown in Figure 53(a).
Resistors (Rl? ~2) connected in serles constitute a circuit ~or dl~ding a supply vol~age tVcc). The vol~age ~1~5~3 .
divider clrcult applies a divided voltage (a) to the gate of an N-channel MISFET (Q2). The supply voltage (VcC) is applied to the gate of æn ~-channel MIS~ET (Q4).
A ~IISFET (Q5) has its gate supplied wlth a suita'ole bias voltage from (d), and constructs a constant-curren~
source. It constitutes an opera~ional ampl~fler, together wlth load MISFETs (Ql) and (Q3) and the two differential inout MISF~Ts (Q2) and (Q4).
The dif.~erenti~l lnput MIS~ETs ~Q2) and (~4) are f~rmed on, for example, N-type silicon laye~s of equal conductivities, and the respecti~e gate electrode~ arP
made of di,ferent materials so that the threshold ~rolea~es may become 2?nequal. The gate electrodes of the two MISFETs (Q2) and tQ4) are made o~, for example, silicon, and their condu`ctlvlty types are made ~ifferent. The MISFET (Q2~ has the N-~ype silicon gate, whereas the ~SFET (Q4) has the P-type silicon gate. As a result, the threshold ~oltage (Vth4) of the MISFET (Q4~ becomes greater than ~he threshold voltage (Vth2) of the '`IISFET
(Q2) by the dif~erence of the Fermi levels of the P-type and N-type silicon gates.
Accordingly, ~he operational amplifier has an of.set voltage e~u~ to the difference of the threshold voltages.
Under the state under which the supply voltage Vcc is comp~ratively great in ~he clrcuit o~ Figure 53~a), ~he MISFET (Q4~ ls in the "on" state and ((;~2) ls in ~he "off" s~ate, ar~ the pote~tial of a point c is at ~he low le~el. D~e to the lowering of the supply volt2ge YCC . the poten~ial of the point (a) changes as indicated by a curve a in Flgure 53(b). '~hen, due to the loweri~g ..
~ 3 of the supply voltage Vcc, the potential dlfference b~t~reen the s~pply voltage Vcc and the potentlal of the point a has become smaller than the offset vol~age, the MISFET (Q4) falls lnto ~he "off" state &n~ (Q2) ~alls into the "on" state. In consequence, the potentlals of the points D and c in the clrcuit of ~iO~ure 53(a) change as indicated by curves b and c in Figure 53(b), respectively. That is, the potential of the point c becomes the high level when the supply voltage Vcc has lo~ered to a predetermined value.
As described above, '~he detection level of the clrcuit of Figure 53(a) is determined ~y ~he offset voltage owing to the MISFETs (Q2) and (~4) and the divided voltage owing to the reslstors Rl and R2, I~ is ~ot affected by the threshold voltages of t~he respect~ ~re ~SFETs, The offset voltage is at a comparatlvely high preci-~ion becauqe lt ls declded by the dlfference of the Fer~l levels of the gate electrode~ of the ~wo MISFETs (Q2) and tQ4) as stated previou~ly, Since, in a semiconductor integrated clrcuit9 the relative values of the reslst~ces of resistor elements are at a comparatively high precision, the ~oltage dl~islon ratio owing to the reslstors (21) and ~R2) ls at a comparatlvely high precision.
As a result, the detection level of the circuit of ~igure 53(a) can be set comparatl~ely accuratel-;.
In Figure 53(b), a waveform (d') lndicates the output of ~he gate circuit (5) during the data reten'ion m~de durlng which the gate clrc~-t (5) is not controll2d by the detection outDut, ~ ~ ~ 5~ 3 In the data retention mode, the input control signals (~) and (~E) lower ~aster than the supply voltage (Vcc) o~ the gate c~lrcuit (5). Therefore, when the dlfference of both the voltages has become above the logic threshold, the output waveform td') as stated above is generated.
This forms the cause of the malfunction explained before.
According to the circuit of ~he present embodiment, however, the control signal (c) is applied to the input of the gate circult (5)~ so tnat the waveform (d') is inhibited ~rom being pro~ided. Thus, the erroneous wri~e ln the data retention mode can be prevented, and data stored in the matrix memory are not destroyed.
In accordance with the embodiment set forth above, the erroneous write in the data retent$on mode can be perfectly prevented. Moreover, the detector circuit can be constructed with the slmple clrcuit arrangement a~d can be contalned in the memory chip, It is therefore unnecessary to care for the prevention of malfunctions on the side of the user of the semiconductor memory device.
For example, the gate circult which is controlled by the voltage detection output may obtain the chip select signal. All the memory cell select signa~s may b~e lnhibited so as to select no memory cell.
~his is because the erroneous wrlte can be preYented when one of conditions necessary for the executlon of the write operation is inhibited.
The voltage divider c~rcult which constitutes thQ
voltage detector clrcuit in the prevlous embodlment may utllize resis~ance by means of MISFETs inste2d o~
the resistor elements. Deslrably, the resistance of this - 1~8 -~5~,3 voltage di~ider clrcuit is made a large value ln order to make the power dissipation low, The twc MISFETs of the foregoing embodiment which have sllicon gate electrodes of conductlvity types opposi~e to each o~her are fabricated within a silicon monolithic semiconductor lntegrated circuit chip. Since these FETs are manufactured under substantially the same condi~lons except the conductivity ~ypes of the gate elèctrodes, the dlfference of the threshold voltages Y~
of both ~he FETs becomes approximately equal to the d~-ference o~ the Fermi levels of P-type silicon and N-type silico~. The P-type and N-type gate elec~rodes are doped with re~pecti~e impurities to the vicinities of the satura-tion densities, and the difference becomes approximately equal to the energy gap Eg of slllcon (about 1.1 V), which is util~zed as a reference voltage source.
The reference voltage generator device based on such a construction is low in the temperature dependency and small in the manu~acturing deviations~
The voltage detector circult 7 can be modi~ied varlously, That is, the re~erence voltage sources which exploit ~he dlf~erence o~ the Fermi le~els of semiconductors forming ~he gate elec~rodes of tw~ MOS FETs as shown in Figure 6(b), Flgure 8, Figure 9, Figure lO(a), ~igure ll(a), Flgure 12, Figure 13, Figure 14, Figure 15, Flgure 16 and F~gure 17 are ef~ecti~e as ~he reference volta&e source for the voltage detector ~ircult of ~his invention, To this end, there can be employed two FETs which have semiconductor gate electrodes of different conductlvlty ~5~3 -types as already explained with reference to ~lgure 59, for example, a MOS transistor with its gate electrode made of a P -type semlconduc~or or a P+-gate MOS translstor and a MOS transistor with its gate electrode made of an N~-type semiconductor or an IY+-gate MOS translstor. As already described with reference to ~igures 73(a) to 73(f), the above two FETs can be manufactured without the change or addltion of any step by the con~entional CMOS manufacturing process, In case of employlng ~he conventional CMOS ma~ufac-turing process, the self-alignment structure as shown in Figures 65(a) and 65(b) and Flgures 66(a) and 66(b) is obtained as stated below~ 3ince the MOS translstors are of the P-channel in this case, a P-type lmpur~ty is diffused into bo~h end parts of a gate electrode ad~olning the source.and draln in both the P~-gate MOS and ~he N~-gate MOS. In a central part of. the gate electrode, a P-type impurity ls diffused ~or the P~-gate MOS, and an N-type impurity is diffused for the N~-gate MOS, Between the cen~ral region and both the end par~s ad~oin-lng the source. and drain9 regions i in whlch no i~purlty is diffused are disposed. mus, lt ls considered that the difference of the P~-gate MOS and the N~-gate MOS is only the conductivity type (P or N) of ~he semlconductor form~ng 25 the central reglo~ of the gate.
~ urther, in order to reduce to the utmost the devia-tion (difference) of the effecti~e channel leng~hs of the MOS transistors attributed to the fact that the regions of the ga~es which are formed for the self-al~gnment a~d in 30 which t'le P-type imp~ity is dlffused shlft onto elther ~5~6~
the left or right side (source side or drain side) during manu~aoture on account of the error of the mask alignment, the columns of the source regions and the d~aln regions are alternately arranged, and the left hal~ and the right hal~ are put into a line symmetry ~rith respect to the channel direction as a whole. ~ccordlngly, even when the misregistration of ~le mask alignmen~ with respect to ~le char~lel direction (lQf~ward or rightward shifting) changes the effective channel len~ths of the FETs ~n ~h@ respective columns, the average effectlve channel lengths of the P~-gate MOS and the N~-gate ~ICS
in the respectlve columns connected in par211el have the s~ifting canceled as a whole and become substantially . constant, Besides by ma~ing the compositions of the gate elec-trodes different, unequal threshold voltages are realized by the ion implan~ation into channels as described with reference to Figure 7, by utilizing a doped gate oxide, by changing the thickness of gate insulatlng film~, etc, An example in Figure 54 is the example in whlch ~he battery checker of the ex2mple of Figure 20 ls applied to an electronic timepiece.
Tl~ T2~ T41 T49 and R41 and R42 constitute a clrcuit which checks the ~ol~age level of a mercury battery El having a nominal voltage o~ 1.5 V. A translstor pair (Tl, T2) in a differential portion is constructed of a P+ gate N-ch~nnel ~OS Tl and an N~ gate ~-channel ~IOâ
T2 t~e channel portions of which are sub;ect~d '~ ion implantatio~ so that the threshold voltages of both the transistors may lie within loO V to 1~5 V beinO the ~ .
~ 6 3 operating power supply range of the electro~ic timepiece.
The di~ference of the threshold voltages to serve as a reference voltage ls about 1.1 V in case of a silicon semiconductor. In order to set at about 1.4 V a level for de~ecting that the vol~age of the battery El has lowered, an ad~ustment is made by the resis~ance ratlo of the resistance means R41 and R42.
In order to make the current consump~lon negl ~ible in practical use, the battery checker is lntermi~ten ~y operated by a clock si~nal ~ whlch is ob~ained from a frequency divider circuit ~D and a timi~ circuit ~'.
An output of the battery checker is statically held by-a latch which is composed of NAND gates ~JA
and NA2 ~he timlng circuit TM is controlled by a logic leYel of an output from ~he latch circuit, whereby a dr~vlng output of a motor is changed and the ~ethod of mo~ing hand o~ the timepiece is changed so as to indica~e the lowering of the battery vol~age. The lowering of the battery voltage can also be lndlcated without chang-ing ~he movements of the hand and by, for exampl~, fl~cker-ing an electrooptic device such as a llquid crystal and light emi~ting diode.
Xn the figure, OSC indicates a crystal oscillator circuit which is constructed of a CTfilOS inverter and which al~o includes components outslde the IC, a crystal Xt and capacitances CG and CD. WS ~ndicates a waveform shaping circuit which converts the oscilla~,~on outpu~
from a slnusoldal wave into a rectangular Yra~,e. C~l indicates an excitatlon coil of a step ~otor for driv~ng the second hand. BFl and 3F2 indicate bu~ers ~trhich are ~ ~ ~ 5 ~ ~
cons~ructed of CMOS inverters and ~ich serve to drive the exclta~lon coil ~ while inverting the polaritles every second, All the circults withln the IC are operated by the mercury battery ~1 f the no~inal 1,5 V. ~l is the tlming pulse generator circult which revei~es a plurallty of frequency dlvision outputs of different frequencies from the frequency divider clrcuit ~D and the control output of the latch composed o~ MAl and NA2 and which generates pulses having any desired period a~d pulse width. The IC is of a monolithic ai semiconductor chip for a hand type electron~c wrist watch which is fabricated by the Si gate CMOS process alread~J e,Yplained ' with reference to Figures 73(a) - ?3 (f).
Figure 55 shows an example of the co3struction of a circult system for an electronic wrist watch con-taining a battery checker thereln. In this example, the conductances of FETs Q4 and Q5 of a differential circuit are made unequal as in Figure 39, and the detectlon level can be finely ad~usted by means o~ an adjusting reslstor R~ outside the IC.
Owing to the resls~or R~, de~iations ln the ma~u-facture can be per~ectly avoided in use, Now, an example in whlch the ~oltage regulator as shown in Figure 36(a) is applied to an electronlc tlme-piece wlll be explained with reference to Flgure 56, In Figure 56, OSC designates a crys~al osclllator, WS a waveform shapi~g circuit which converts a sinusoidal wa~e oscillation output into a rectangular wa~e, F~ a frequency di~ider circult, IM a tlmlng pulse generator ~ 3 circuit which prepares pulse~ of predetermined period and width from frequency division outputs, LF a level shift clrcuit which converts a signal of low level into a signal of high le~el, BC a bat~e~y lifetime detector, VC a voltage comparator, VR a vol~age re~ulator ~ch uses the voltage comparator VC, H a hold circuit, DT
an oscillation state detector, and ~M &n excl~a~ion coil of a step motor for driving a second hand.
The detector DT detects it through the f equency dl~ider FD and the timing circuit TM that the oscillator OSC has oscillated, In case of the oscillatio~, it actuates the volta~e regulator V~ to drop t~e operating voltage VOp of ~he oscillator OSC as well as .~S, FD, ~l etc. into a value below the battery voita~e (-1.5 ~).
The moment a battery E is turned "o~", ~he lnput node of an inverter I7 becomes the earth potential (logic "O") owing to a dlscharging resistor ~104~ so that an N-channel FET Q201 is brought i~to the "0~"
state and that the output o~ the regulator is made -1 5 V being the battery voltage. At this time, a ~T
Q203 is also turned "ONn, and the gate node of a ~ET Q202 is charged. This is to the end of pre~iously making the negative ~eedback loop of the regulator active lest ~he regulator ou~put should drop ~he moment the FET Q201 is subse~uently switched "OFF".
Wher the oscillator has started operatlng, the other logical circults are already in the operative s~ate, so that a pulse ~ ls supplied from the timing circult TM to the detector DT. ~ e~clusive OR circui~
EXl detects the issue of the pulse P'B One lnput thereo ~5~3 rece~ves the pulse ~B delayed by inverters I4 and I5 and an integration circuit C10l and Rlo~ ~itn respect to the other. Upon the issue of the pulse ~, accord-ingly, a pulse of a width corresponding to the delay time is provided at the output of ~le gate EXl, This pulse is lntegrated by a rectif~er circuit made up of a F~T
Q225' an inverter I6 and a capacitor C102? and turns "OFF" the N-channel FETs Q201 and Q203 P
a snort time from the beginning of the issue f ~B~
mus, the reO~ula~or VR generates a predetermined voltage (less than 1.5 V) at the source electrode o, the con-trolling P-channel FET Q202 by the nega~ive feedback cor.trol loop, ~nd it contributes to reduce the power dissipation ,~ of the electronic timepieceO
Hereunder, the opera~ion of the regula~or, especially the ~oltage comparator VC will be explalned, Slnce this comparator VC ef~ects an operation ~imilar to that of the comparator CP described with reference to the principle dia~ram of ~igure 35(a) and the characterlstic dlaOram of Figure 35(b), only a brlef explanation ~11 be given.
Regard~ng P-channel r~lOSF~Ts Q206 and Q207' in order to obtain the offset voltage Voff, the gate of Q206 is made the P-type as ln Ql of FiO~ure 60 and FiO~ures 67(a) and 67(b), and the gate of Q207 is made the i-type (intrinsic semloonductor) as in Q2 of FiO~ure 60 ~Lnd Figures 68(a) and 68(b). Accordingly, the threshold ~oltage Vth f Q207 becomes higher than ~hat ~ Q206 by abou~ 0~ V, wnich serves as the aforeclted offset voltage Voff.
On the other hand, sinoe both an N-channel ~ET Q2~8 and a P-channel FET Q209 are dlode-connected, the sum of 5~3 both the threshold voltages Yth i-e- (V~hp209 + Vthn208) is applied to ~he gate of Q207 being the non-inverting input (+) of the comparator VC, and the sum serves as the voltage Vre~2 as indicated ln the curve d in Figure 35(b).
On the other hand, the gate of the ~ET Q206 being the lnvertlng input (-) of the comparator is connected to the source of ~he controlling P-channel FET Q202 of the source follower type Accordingly, the output voltage VOUt of ~he voltage regulator VR which is generated at ~he source of the con-trolling FET Q202 under the control actlon of this control-ling FET Q202 driven by the comparator VC becomes VOUt _ thp209 Vthn208 + ~Voff (in case where Vin 2 Vthp ~
~ Vthn ~ ~Voff)~ When the input voltage Vin is low, the output voltage becomes VOUt - Vin as in the foregoing.
Of course, the output voltage VOUt of ~he voltage regu-lator VR is utilized as the operating voltage VOp of the oscillator OSG as well as WS, FDI ~M, etc.
Ir, order to render the power dlss~pation low, thls comparator has the opera~lng time llmited by a timing slgnal ~A owing to ~he on-o~f operatlon of the driven ~ET
Q211 f cour~e, the same applies to the c~rcult for ob~ainlng the reference ~oltage Vref2 To this end, a oapacitor C104 lq connected to ~he gate of Q207 and a 2S capacitance C105 is connected to the gate of Q202 so as to hold the voltage of the reference voltage~rref2 and to hold the gate Yoltage of Q202' respecti~ely. These capaci-~a~ces C104 and C105 are added sepa~ately from parasitic capacitances such as ga~e capacl~anceq A capacltor C103 serves to prevent any oscillation which is attributed to a phase rotation caused by the cascade connectlon of sev-eral ~ETs in the feedback loop.
Since ~he battery checker BC has a construction slmllar to that in Figure 54, the explanation is omltted.
At the output stage of the IC, drlvers I2 and I3 for the exc~tation coil directly use the battery of 1.5 V as the power supply in order to make the driving capabillty high Flgure 57 shows an example in which the voltage regulator VR and ~he battery chec~er BC according ~o this inventlon are applied to a digital display electronic tlmepiece.
In the figure, parts OSC, '~tS and r~D use an adJusted voltage lo~ter than 1.5 V as a power supply as in the ex~mple of Figure 56, and also loglcal clrcuits within an IC such as decoder DC and time correction circuit TC
u~e the lower voltage as a power supply.
DB designates a voltage doubler circult whlch boosts the voltage of 1.5 V to 3.0 V, which is used as a driYe vol~age for a li~uid crystal display DP (a driY.er ~s not shown). Each of LSl and LS2 indica~es a level shift circuit, which converts a low $1g~al level into a high one D,C.-wise and supplies lt to circuits of high supply vol~ages, It ls effective for rendering the power dissipatlon low and the expanslon of a service power supply range that, as thus far described, the low opera~ing power supply is used for the ordinary lo~lcal circuits within the IC which operate at low operating ~oltages, while the high operating power supply i~ used for the display - 117 ~
driver etc. at the lnput/output lnterface of the IC
whlch require high operating voltages.
: - 118 -
An example in Flgure 31 is a constant-current circult wherein the so-called current mlrror circuit in ~/hlch ~~ ~ranslstors T31 and T33 have ~he same characteri~ticsO
An example in ~gure 32 is an ap~llcation ~herein a re~erence- voltage VREF which is decided by ~he dif~erence voltage of the threshold voltages of M0~ F~Ts corresponding to the dlf~erence o~ the Fermi levels of ~he gate electrodes of the ~SOS FETs in accordance wlth t~ls inventlon is explolted for ~ ~ta~ili2ed power supply clrcu~t, A
reference voltage generator devlce RVG i5 constructed by any of the above-stated several methods acco~dlng to the principle of thi~ ~nvention. A dlvided ~oltage of a stabillzed output ow~ng to volta~e d~vlder means ~13 ~nd R14 and.a reference ~oltage are comparedJ ~nd the gate voltage o~ a controlllng MOS FET T20 is controlled so as to bring ~hem into agreement, thereby to st~bilize the ~utpu~ voltage VOut. Any operational amplifler may be used as lor.g a~ lts characteristic~ are allowableO
In theexample of Flgure 33? the MOS transistor used for ~20 in the example of Fi~ure 32 is replaced with a ~0 bipolar transistor TRl.
A~ example in ~igure ~4 uses the operational amplifler VC as show~ in the exampla of ~lgures 13 and 14, ~rhich has the offset voltage based on the dlfference voltage of the threshold vol~age~ Yth o~ MOS FETs and whose non-inver~ing input t~) is grounded. Tzl may be a MOS tran-sistor, a bipolar transistor or a ~unction field-effect ~ransistor, ~ Flgure 35(a) sho.ws a Yoltage regula~r according to thls invention ~loh is a fur~her lmpro~ement on '~he stabillzed po~er supply oircuits illustrated in ~igul~es 32, 33 and 34, and Figure 3S(b) is a characteristlc diagram thereof.
e ¢ircult arrangement in Flgure 35(a) has ~he construction of a comparing voltage regulator. It differq f~om a conventional voltage comparator in that the lnput characterist~cs of an operational amplifier YC being a voltag~ comparator are asymmetric at ~he lnput ~ermi~als of an non-in~ertlng lnput (+) and an lnvertlng input (-).
That is, this voltage comparator does not balance t~hen the voltage l~evels o~t the non lnverting lnput ~) and ~he in~ertlng lnput t-) are equal to each other, and it balances when a predetermined hlgh iniU~ Yoltage (in the absolute value) i8 applled on the in~erting input (~).
In o-ther w~rds, in thls voltage comparator, ~he lnpu~
levels of the ~on-i~ert~ng input ~3 and the invertlng lnput (-) have an o~fset wi~h respect to the kalance p~
On ~he o ~er hand, accordlng to a con~entional voltage regulator, in case where a~ input ~oltage Vin ls hlgh, an output ~oltage VOu~ depend upon a reerence .
~ ~ ~ 5 ~ 3 voltage Vre~ generated ~rom the reference voltage gene-rator RVC and the di~erence of VOUt - Vi is ~ade large, whereas in c~se where the input voltage Vin is low, VOUt depends solely upon Vi and the dlfference of ¦Yin ~ VOUtl is made s~all. Accordlng to this inventlon, the changlng polnt P between bo~ ~he cases is set at a point o~ Yin ~ Vl wi~h respect to the ~nput voltage Vin (V~ indicates ~he lowest operating voltage of a regulator load L).
Accordlng to the voltage re~ulator o ~his inven-tlon thus constructed, when the input ~oltage Vin is higher than the lowest operati~g voltage Vl~ the laad L
ls operated by ~he output voltage l~ou~ which is higher than the lowest opera~lng ~oltage Vl but lower than the input roltage Vint and hence, ~he power dlss~pation is reduced wh~le ensurlng proper operation. When the input voltage Yi~ i~ low~ ~he load L is operated by the output volta~e which is substantially e~ual to the ~nput Yoltage Vin or somewha~ smaller ~han itJ and hence, a voltage near the lowest operating ~oltage Vl of ~he load L ~o.r the lnput voltage Vin is supplied. S~nce the output voltage VOUt is reduced to a voltage sui~ed to ~he load L for the high lnput voltage V~ hls voltage regula~or can e~dow the load L.wi~h a lou power dissipation and a wide range of input v~ltages Vin.
Such an e~ect of ~hi5 i~vention will be described ~n de~ail with reference tG the g~aph of Flglre 35(b) 1~ comparison with the prior-art v~ltage somparing regu-lator having no offset~
In the figure, the abscissa represents ~ ~ ~ S ~ 3 the lnput voltage Vin,while the ordinate represents the output VOUt and the re~erence voltage Vref. 3traight line ~h indicates VOUt equal to Vin, in other words, a vlrtual curve in the case where the load L ls operated directly by the ~nput voltage Vin without employing ~he voltage generator.
Curve c indicates a reference voltage Vre~l generated from any of the reference vol~a~e generator devices in various forms. Depending on the type thereof, the reference voltage generator circuit device RVG utilizes various parameters o~ semiconductor devioes such as the threshold voltage Vth of a MOSFET, the ~utual conductanoe qm, the forward voltage V~ or backward Zener voltage Vz of a PN-~unction, .' and the current ga~n h~e of a bipolar transistor. There-1~ fore, .the reference ~oltage Vre~l depends upon ~he supplyvoltage Vin according to the vol~age dependency of the parameter ~ Yre~l Y f ~Vi~)].
When the ~eference voltage Vrefl is used as ~he reference voltage of the vol~age comparator circui~ YC and where the comparator circuit VC 1s not endowed w~th the offset as previously sta~ed, ~he outpu~
vol~age Vout becomes e~ual to the reference voltage Vrefl ~nd agrees wi~h the cur~e c, Since the reference volta~e ~refl does not become hlgher than the input voltage Yin, ~he output ~oltage You~ becomes lower than the input voltage Yin in any range, As a result, the lnput voltage ~in at the time when ~he output ~oltage YoUt becomes e~ual to the lowest operating ~oltage Vl of the load (~oin~ R) becomes V2 (V2 ~ Vl) Accordingly, the usable range of input voltages Vin as ~iewed from the load L
~ - 79 ~
5r~
suffers a loss o~ a ~ol~age component corresponding to 2 - Vl I -In order to make this loss small, ln the ~oltage regulator of Figure ~5(a) according to ~his in~ention the operational amplifier VC maklnæ up the voltage compara~or balances when the in~ertlng input (-) has become hlgher than ~he non-in~erting ~npu~ (+) by the offset voltage ~JOlf.
, In considera~ion o~ ~he of~set vol~age ~tJoff of the operational amplifier ~C~ a reference voltage Vref2 (curve d) which is ~maller than the virtual ~eference voltage Vrefl and whlch has a similar characteristlc is employe~ as an actual reference Yol~age Vref, m e ~alues o~ Vref2 and ~Vof~ are set so that a substanti~l co~ari-tage (Vref2 + ~Vo~f~ at an input voltage V3 ln the normal operation may ~ecome e~ual to the virtual reference ~olt~ge Vre~ , namely~ ~hat it may agree with a desired operating point ~.
With such a construction, the volta~e comparator vC
ormed into the voltage follower balances under the condi-tlon o~ VOu~.~ Vref2 + ~Vof~. Since ~nput voltages Vln satisfying the balance condltlon are only Vin ~ Yre~2 ~off' When the inpu~ voltaye Vin is smaller ~han ~ref2 + QVoff)~ ~he oUtput voltage VOUt atso becomes smaller than itt sO that the voltage co~para~v~r VC func~
tions to raise the output voltage VOUt. This feedbac~ controlr how~ver, is limited when ~le eu~put ~oltage VOUt has become equal to the lnput ~-ol~age Vin.
Accor~lngly, with the ln~lexlon poin~ (P) a~ Yin ~ Vref2 ~ AVo~f, the output voltage VOUt is reduced - 80 ~
~ 3 (limited) to Vre~2 ~ ~Voff (curve bl) wh voltag~ Vin is higher than the inflexlon point P, and it is made substantially equal ~o the input voltage V
(curve a2) when Vin l-~ lower than the inflexion point.
If ~he inflexlon point P is the same as or higher than the lowest operating voltage Vl tpoi~t Q) ~th respect to the input ~ol~age V~n (on ~he abscissa), the foregoing locs can be avoided.
This is because the curve bl has a point of intersec-tion ~ith ~he straigh~ llne al owing to ~Vof~.
when the operational amplifier does no~ have the of~se t voltage ~ltoff and ~here ther~ is no point of ~ntersection with the stralght llne al as in the curve d, such a~
ef~ect is not achleved, Al~hough a MOS FET TC ~n Figure 35(a) functlons as a source fo}lower, it is a depletlon mode N channel FET, so that lt makes VoUt a Yln posslble when Vin ~ V
L~Voff ~nd that its ~hreshold ~oltage V~h has no loss, Accordingly, thls ls effectlve when the input ~oltage Vin is sm~ll, Thls, however~. does no~ deny the use of a source follower FE~ Or ~he enhancement mode. The enhancement mode FET i~s very effectiYe when the input voltage is great and the Vth lo~s i~ not a serlou3 problem and when the adoption of a depletion mode FET manufacturing process is di~ficult. In ~ls case, curve a~ (VOUt =
Yin) ~rhi^h determlnes lower output ~oltage~ VOUt (below the changing point P) merely shifts dow~wards by V~h ~VOu~ - Vln ~ Vth)~ and it is slmilarly possible to brlng ~o forth the effect as previously stated on the output -~ 3 ~oltage VOut, In the figure, the N-channel F~T can be replaced wlth a P-channel FET, In th~s case~ ~he ?-cnannel ~ET
functions t~th the source grounded, and the lo s of Vth above described is not involved.
Whe~her the source grounding or ~he source ~ollo~er is adopted as the contro~ling FET does not produce an esse~tlal dl~erence. However, ln case of the source gro~nding, no special consideration for the loss of the threshold voltage Vth, ~s is required for the depletion mode F~T, is necessary. In case of ~he source follower, when the operation o~ the ~ol~age comparison needs to ~e cycllc~lly sampled (for example, w~en the comparat4r is sub~ected to the clock drive in order to render ~he power dissipation low), thi~ F~T is con~enient as it function~ as a ~oltage fo Uower. This is because the output voltage ls determined by the gate voltage if ~he mu~
tual conduc~ance g~ of the ~ET is su~ficiently high.
It is also possible to use a bipolar translstor as the controll~ng transistor. ..-I~ is not necessarily denled ~hat the offset ~Voff becomes a ~unction o~ the input ~ol~age Vin. In settinC
~he ln~lexion poin~ P9 howeverp it is ~esirable that ~off 1~ constan~ wlth respect to Vi~
If a reference voltage which has a fluctuating factor similar to that of the load L is used as ~te reference Yoltage Vref~, outpu~ voltages VOu cor~espond-ing to the characteristlc o~ ~he load L can be ob'~ai~ed, which is also convenient. I~, in ~hat case, Vre~2 ls set at the lowest ~oltage at wh~ch ~le load L can cperate ~ 82 -5 ~ 3 ~n ad~ance, ~Vof~ can be exploited as means of a certain margin, l~hile a construc~ion for bestowing +ihe offset ~Voff and an application circuit explolt the difference of the threshold ~oltages of two MOS FETs according to the pr~nciple of this invention to be described later, another method for endowing the output voltage VOUt with the ipflexion point will be explained here wlth reference to ~he circuit diagram o~ Fi~ure 36~a) and the ~raph of Figure 36tb).
In ~he followin~ description ~nd the ~ra~h of Figure 36tb), all the voltage values shall be absolu~e Yalues, In Figure 36(a), Q107 designates a co~trolling transistor ~hi~h is made o~ an ~-channel depletion mode ~E~ N_cha~nel FETs Qlol -and Q102' Q104 and Q106 construct current mirror circuits. A dra~n current approxlmately equal to the dra~n current f Q
flows through a diode-connected P-channel FET Q104 and a diode;connected N-channel FET Qlos~ The source~
drain ~oltage drops VDs.of the diode-connected P-cha~nel 104 ~ channel FE~ Q105 become approx~mately equal to respecti~e threshold voltages V~hp and Vthn owl~g ~o the high ~mpedance loads ~102 and Q106- Acco g ~, voltages Vthp and (Vout ~ Vthn) are respectively applied to the non-in~ertlng input (~) and the invert.Lng input t-) of an-operat~onal amplif~er VC constructln~ a vo'~a~e comparator (cur~es d and b in Figure ~6(b)~.
Supposing a case where the operational ampli~ier vc has no offset, it balances when bo~h ~e ~nputs of the f~3 non-inYerting input (~) and the lnvertlng inpu~ (-) are e~ual. Accord~lgly, the e~uilibrium condition is (VOu~ -thn) Ythp, that is, VOut = Vthp + Vthn ~mhe outpu~
voltage VOUt is llmited to (V~hp + V~n) w~en Vin ~ Vthp Vthn, and lt becomes substantially equaf to Vin when ~ln ~ Vthp + Vthn. Accordlngly/ in~case where the load L
is constructed of a complementary MOS lntegrated clrcuit (CMOSIC), the operating lower-limit ~olt~ge of the ~OS
ci.c-~ usually becomes (Vthp ~ Vthn) and the output ~ol~age VOUt can compensate for it.
Al~hough the threshold Yoltage to be deri~ed by the dlode-connected IIIOS Q104 and 4105 is inherent threshold voltage, it ls not equal thereto and follows up the draln current of the circuit. O~ course, i~ is favorable to maXe the outpu~ voltage VOUt of the equilibrium poin~ somewhat greater than the inherent (Vthp ~ ~thn)- To that end, ~he mu~ual conduc~ance of the T Q103 may be made small in advance so as to reduce the current to flow through each MOS diode Q104 or Q105' T~e approximate threshold vol ~ e to be derived by the MOS diode premlses the ~low of ~he drain current.
Therè~ore, the clrc~it must be con3tructed so that ~he curre~ts may ~low through both ~he dlodes even when the input ~oltage Vln becomes low.
~he reference v~ltage generator d~vlce according ~o this ~nYention can generate the ~l~f~rence voltage o~
the thre~hold voltages of MOS as the reference voltage, and can therefore be constructed.o~ MISFETs. Accordingly, it can be extensi~ely utilized as various constant-voltage ~.4 5~ ~ ~
sources in monollthic integrated circuits for an electronic desk top calculator, an electronic timepiece etc. made up of MISFETs. As lllustrated by way of exam-ple ln ~igure 37, a li~etlme detector circuit for a battery can be ob ~ ned ~n such a way that the output of the reference voltage generator de~ice (N~-gate N-channel MOS Ql9 P~-gate N-channel ~OS Q2' resis~or Rl) as shown ~n the foregoing em~odiment is applied to one i~put of a voltage comparator circuit (7) as a reference voltage and that a ~oltage ob ~ ned by di~iding a ~Oattery voltage (VDD) by mea~s of divider resistors (Rlo, Rll) is applied to the other input.
In this case, since the battery voltage does no~
lower suddenly, 1~ is desirable to drive the constant-~oltage generator circuit, the voltage dlYider clrcuitand the Yoltage compara~or circuit wi~h clock pulses, thereby to achieve the reduction of current consumption.
Likewise, when the constant-voltage output is not required at all times, the constant-voltage generator circult may be clock-driven as stated ~bove. ...
m e circuit for obtainlng the difference of the threshold volta~es of the MISFETs (Ql' Q2) ls not restrlcted to the construction o~ the above embod1me~', but lt ca~ be modified in various ways and any specific cir-cuit arrangement may be used~
Figure 38 shows another embodiment in whlch thlsinven~lo~ i~ applied to a battery checker.
Ql' Q2' ~ and ~ constitute a constant-current ~ 5~ 4~ Q6 and Q7 constltu~e a d~f~erential circuit. Qll and Qlo serve for the clocX drive to the : - 85 -~ 3 end of the reduct~on of power dls~ipation.
Rl and R2 constitute a battery ~oltage divider circult for setting the detection level of a batter-~voltage. Gl and G2 func~ion to latch an output owing to Q8 and Qg.
Q4 and Q6 are an N~ gate P-channel .~IOS and a ~+-ga~e N-channel MOS, respectively, By ~e lon implantation ot~
e~ual quantities, Q6 is adapted to operate in the deple-tlon mode~
The embod~ment shown in ~igure 38 ~s 'he battery checker for a ti~epiece. When the detection level is set between 1.3 V and 1,5 V, a cur.ent flowing through Q~ has positive gradlent for ~le temperature, and ~he difference (_ band gap ~oltage 3 1 . 1 V) of ~he threshold voltages of Q~ and ~ has a negative gradlent for the temperature. Therefore, ~he dimensional ratio of ~he MOSFETs is set so that ~he conduct~nce of Q~ may become smaller than the conductance of Q4~
Figure 39 -qhows a hlghpreclsion reference voltage generator circult o~ the voltage follower type ~tilizlng an operational ampli~ler. N-channel I~IOS FETs of the P+-gate and N+-gate are used for`Q4 and Q5, respecti~el~.
Furt;her, tlle conduc~ces o~ the FETs are o~a~e dif~eren~
to pro~uce an o~:~set ~roltage. By adJus~ing a resistor 25 Rl outside an IC, a con~tant. current to flow through a constant-c~ent source Q~; ls ad~usted, thereby to ad~us~
t:he o~:~set~roltage, Thus, ~e ~ine a~,ustment of a re~erence ~ol~age ~s made pos~ible, On the other h~d, as a Schm~tt trfgger circuit 30 compo~ed o~ ~lISFETs, a ci~cuit a~ shown in Flgtlre 40(a~
-- ~6 --i3 which has reduced the number of constituent elements has been proposed by one of the inventors.
The circuit shown in Figure 40(a) is such that two inverters are connected in cascade and that a MISFET
(T3) forming a positive feedback circuit is disposed between the input and output of the inverter on the output side. With this circuit, the width of a hysteresis curve (the difference of two logic threshold values VTLl and VTL2) deviates on account of deviations in a supply voltage (VDD), the threshold voltages (Vth) o~
MISFETS, etc. Therefore, when the circuit is applied to an oscillator whose output oscillates-within the voltage width, the frequency deviates disadvantageously.
This invention employs MISFETS formed by a method wherein the threshold voltage of one (T2) of MISF~TS
constituting the first~stage inverter in Figure 40(a) is made higher than that of the other MISFET having the same conductivity type channel by a voltage component based on the difference of Fermi levels. In this way, it is ~0 intended that the width of the hysteresis curve of the Schmitt trigger circuit (the difference of two logic threshold voltages) assumes a fixed voltage (a voltage substantially equal to the Fermi level difference) fluctuating little against the supply voltage, the manu-facturing deviations of the MISFETs, temperature changes, etc.
`In the following, this invention will be described 5~i3 in connection with a ~referred e~o~.iment. Referring to Figure 40(a), the Schmltt ~rlgger circui~ ls constructed of an in~erter 1 to which an inpu~ signal (Vi) is applied, an inverter 2 which receives an output of ~he inverter 1 as its lnput and which forms an output signal (VO) and a MISFET.(T3) whlch ls interpo~ed be~ween an lnput termlnal and a ground termlnal o~ the ~n~erter 2 and which l~;con~rolled ~y the ou~put slgnal~(VO);
T.he MTSFET (T3') aots as p~sltiYe feedback means of ~he output slde inverter 2. The operation of positively feeding the input signal of ~he inver~er 2 to the outpu~ slgnal thereo~ is inseparable from the operatlon of ~he inverter 1 ~orming the input signal. The circui~
operation is more easily understood whe~ expla~ed ln rela~ion with the input side lnverter lr as in the following.
When the input s-l ~ al tVl) ls at a high level (ground le~el~, the o~ù ~ t oS.the input side ln~er~er 1 becomes a low le~e ~ se~the N-cha~nel MlSFET.tTl) 20 is ~on~ and the P~cha~nel MIS~ET (T2~ is "offn~ The N-channel MISFE~ ~T4) of the output side ln~erter 2 rece~Ying this output of the input side inve~ter 1 tur~s lloff" and the P-channel MISFET (T5) turn~ "on", so ~hat the output o~ the output qlde lnverter 2 become~
~he high level~(&round level). For thls reason, the P-channel MISFET (~).falls ~nto the "off" state, ~ nen, under ~hls condlt~on, the input s~gnal ~
intends to change to the low level, the output o~ the in~erter 1 forms an output signal which is dependent upon the le~el ~ the input signal ~Vi~ and ~ich ~s deter-- 8~ -mlned by the impedance ratio of the ~ISF2Ts (Tl, T2), because ~he MISFET T3 is "o~f". The input level of the output slde ln~erter 2 is changed from the low level to the hlgh le~el.
Accordlngly, wheri the outpul; of ~e output s~de lnver-ter 2 is changed rom the high level to the lo~ level .
and this output signal (VO) has exceeded the threshold vo~tage of the`~IS~ET (T3), the MISFET (T3) starts the "on" operation. Owl~lg to the "on" operat'on of the MISFET (T3), ~he output level of the inpu~ side inYerter l is decided by the impedance ratio between the MISF~T
(Tl) and the parallel MISFETs (T~, T3), and it is shifted onto a hlgher le~el side. In other words, upon the "on" operatlon of the MI3~T (T3) ~hlch .ls controlled by the output of the ~utpu~ side ~nverter 2, the posi-tl~e feedback in which ~he ~nput level of the output side in~erter 2 ~s ohanged into the h~gh level side is applied to the input o~ ~he output side ln~erter 2.
Then, the-outpùt s12nal (VO) changes abruptly. Accord-~o ingly, the loglc threshold value (V~L2) in Figure 40~b) is determlned by the thre hold ~olta~es Vthl and V~h2 and mutual conduotances ~l and ~2 ~ the MISFETs (Tl, T2) in Flgure 40(a), That is, YD~ Vthl ~ ~ th2 VTH2 ~ ~ .,.(51) , On t'he other hand, when the input slgnal ~Vi) is at the low le~el, the N-channel MISFET (Tl) of the ln~ut ~ ~ ~ 5 ~ 3 side lnverter (1) ~s "off" and the P-channel MI3FET (T2) ls "on", tha N-channel MIS~3T (T4) of the output slde lnverter Z ~s "on" in the P-channel MISFET (T5) is "off", and the P-channel MISFE~ (T3) ls "on" owlng to the low level of the ~utput signal (VO), so that the output signal of the lnpu~ slde lnYerter 1 is determined by the lmpedance ratlo between the MISFET (Tl) and the parAllel MISFETs (T2, ~3)-Accordingly, in the course ln whlch the lnput signal (V~) changes fro~ the low level to the h~gh level, unlessthe ~input sign~l (Yi) ~ecomes a leY~l hlgher than the loglc threshold voltage (VT~2) in the precedlng operation, the outpu~ slgnal of the lnput side inverter 1 does no~ change to the low level. However9 once thi5 out~ut (the lnput sl~nal for the output side lnverter 2) has begun to change towards the low }evel and to change the outpu~ o~ the output side inverter 2 onto the hlgh level slde, the impedance of ~he MISFET tT~) changes to lncrease. There~ore, the posit~e feedback in which ~0 the change of the output o~ the input slde lnv~ter 1, namely, the lnpu~ ~lgnal of the output side lnverter 2 is promotèd is applied, and the output signal (VO) changes abruptly, ~ere, when ~he P-channel ~ISF~T (T2) has lts gate elec~rode ~orme~ o~ a semiconductor oî
25 ~e opposlte conducti~rity type (N-type) to the conductlvlty type (P-tgpe) of the gate of - the con~rentf onal P-channel MISFET (T3)~ or o~med of an intrinslc {i-type) semlcon-ductor, it ba~ a ~shold ~ro}tage whlch is higher ~an the threshold Yoiiage YTH of the ordinflry MISFET (~r3) by 30 a ~oltage corre pondlng to the dif~erence o~ Fer~ levels e.g. to the dif~erenee of the lntrlnslc level and the Fermi level, respectively.
Accord.~ngly, the logic threshold ~ol~tage (VTLl) in Figure 40(b) ls approx~mately expressed as follows:
VDD ~ Vthl + ~ Vth3 VTLl ' ~ ...(52) ~ ~1 ~2 ~ ~3 i~ he}d by makin~ ~he sl2es of the 1~I3~ET (Tl) and the MISFET (T2) equal~ Therefore, ~he d'L~erence ~YTL2 - YTLl) of ~he two 1O81c threshold values beco~es:
VTI~2 ~ V~ (Vl;h2 Vth3) 1+~
\1 ~1 Accordingly, the dif~erence (VTL2 ~ VTLl) .~ the logic threshold ~alues in Figure 40~b) as~umes a fixed voltage w~ich is proportional to the dlfference (Vth2 -Vth3) of the threshold voltages of ~he MISFET.2 and the MI~FET 3, that is, the difference of the Fermi levels of the gate electrodes of these MISFETs 2 and 3.
An example for-der~vlng the volta~e correspondlng to the dirferen~e of the ~erm~ levels is to utllize ~he difference of the threshold voltages Vth of two kIOSFETs having ~emlcondue~or gate e}e~trodes which ha~e different ~on~uct~vity types and which are formed on gate Sl~j3 lnsulating films ~ormed on an identical semiconduc ~r substrate by an lden~ical process Hereunder, a specific example w~ll be explained, Figure 59 previously referred to represents the conceptual sectional structure of ~he raspec~ive ~ETs, and the stru~ture can be fabrlcated by the MOS manufac~uring process lllustrated i~ Figures 73~a) - 73(f) Hereunder, - for t~e sake of brevity, ~he MOS tra~slstor whose ga~e electrode ls made of a P+-type semlconductor shall be called the "?+ gate ~OS", and the MOS transistor whose ~ate electrode 1~ made of an N~-~ype semi~onductor sh~ll be called the "N~ gate MOS".
~ he dIfference tYthP~ ~ VthN~) ~ the threshold voltages of the P4 gate MOS and the N~ gate MOS becomes 1~ the differen~e o~ the ~erml potentlals of sem~conductors making the gate electrode~ as seen from Equatlon (16).
While ~he above descrlption has been msde by takln~
the P+-channel ~IOS transistor as an example, gulte the same applies to the case of the N+~channel ~iOS transis~or.
Besides, qulte ~he same applles to the i-type gate MOS
~hose gate electrode ls made of an lntrlnsic semiconductor, Figure 41 shows a Schmltt tr~gger clrcult according to another embodlment o~ ~his in~ention. The point of differe~ce from the embodlment o~ Figure 40(a) is ~hat an input lnverter 11 lncludes a P~-gate P-channel depletion ~ype MOS translstor Tll for a load, a P~gate P-channel ez~n~ement type MOS transistor Tl~ or drlve and an N+-gate P-channel enhancement type MOS trans~stor T13 for feedbac~, and that an output inYerter 12 includes a P+-gate P-channel depletlon type MOS tr2nsistor T14 ~or ~ 3 a load and a P~-gate P-channel enhancement type MOS transis-tor T15 ~or drive. It is identlcal that the difference of loglc threshold ~alues becomes a constant voltage propor-tional ~o the difference of the ~ermi levels of the gate electrodes of the MIS~ET 12 and MISFET 13.
Now, an osc~llator wlll be descrlb d as a~ example of appllca~lon o~ ~he Schmltt ~rlgger cLrcuit of thls entlon.
~ gure 42 is a c~rcuit diagram of an oscilla~or ~o which the Schmltt trl~ger circult of this in~ention ; is applled. A part enclosed with do~ted lines in Figure 42 ls the 3chmitt trlgger clrcuitO An outpu~ o~ the Schmitt trigger circuit (STC) becomes an input of an inverter 3;, an output o~ which becomes an inpu~ of the Schmitt trigger ¢lrcult tSTC).
Upon closure o a supply ~oltage, the leYel of a point (d) proceeds towards ~he Ie~el (-~DD) gradually.
When lt has exce~ded ~he threshold voltage (VTL~) of the Schmitt trlgger clrcuit (STC), the potential of a point (f) changes ~o the ground voltage, an~ the potential o~
a polnt (g) chsnges to ~he supply ~oltages (-VDD). Then, a~ the point (g) is the 1nput of the lnverter (3), a MISFET tT4) turns "on"J and the po~entl~l of the polnt (d) pr~eeds towards the ground voltage lmmedlatelyO
25 When the level of the point (d) ha~ become ~elow the logic threshold Yoltage ~VTLl) o~ the Schmitt trigger clrcult (STC), the ?ote~tial of the point (f) changes to the ground vol~age, and the voltage of the point (g) changes to the supply ~oltage (-VDD). Therefore~ ~he MISFET (2 30 of the succeeding 'ln~erter (3) tuxns "off", and the .
~ 6 3 level of the point (d) ls charged accordlng to a tlme constant CR which is determined by a resistor (R) ar.d a capacitor (C) connected to the point (d). When ~he po~ential of ~he poi~t (d) gradually approaches the supply voltage (-~DD~ and has exceeded the threshold voltage (VTL2) o~ the Schmitt trigger circuit (STC), '~he potential of ~he poi~t (~) changes to the ground potential, and the potential of the point (g) changes to the supply ~oltage (-~DD)~ Thereafter, ~he in~ersiorls are simll~ly repeated to cause oscillat~on. Since the potential of the point (d) reciprocates betweer, the ~o logic threshold ~oltages (VT$l, VTL2) o~ the Schmltt trigger circul~ (STC), the oscillation frequency of the oscillator is determined by the speed at whl~h charges are stored in~o or dlscharged ~rom the capacitor ~C) by ~he reslstor (R) or ~he MISFET
(T4). Assumlng now that ~he resistance (R~ is suf~iclently greater than the lmpedan¢e of the MISFET (T4)9 the oscil-lation ~requency of the oscillator circult is determined by only R and C~ a~d ~he oscillation ~f a ~re~uency which ls stable agal~st f~uctuations in t~e su~ply voltage, temperature changes, manufacturing deviations, etc, When the resistor (R) i~ mounted outside the inte-grated clrcuit, only one pin suffices for the integrated clrcuit of the oscillator circuit, and the stable oscil-latlo~ ls realizable under such a condltion.
The resistor (R) may be any of a dlffuslon resistor,a resistor owi~g to a MISFET, etc, Howe~er, when a reslstor of sufficle~tly small devla~on ls formed in ~n integràted circuit, the oscllla~or oircuit ca~ be entirel~
contained therei~.
g ~ _ 1 ~ ~ 5~ ~ ~
Flgure 43 ls a circu~t diagram show~ng an example of an oscilla~or circuit utlllzing the Schml~t trigger clrcuit (STC) as shown in Figure 41 in which the wldth of hysteresis is coRstant according to thls invention.
A third lnverter 3 is conne~ted to the input of the . Schmitt trigger circult ~STC), a fourth inverter 4 is connected to ~he output of the Schmitt trlgger circuit (S~C),. and a resls~or (R) ~nd a coupling capacltor (C) for determinin~ the oscillatlon ~requency are connected ~o ~he inpu~ of the thlrd in~erter 3.
Control of Thre~shold V ltage The threshold ~oltages (Vth) of MOSFETs being discrete elements in a MOS lntegrated circult lorm an ~' lmportant parameter whiGh determlnes the characteristics f the LSI. The threshold voltage Yth undergoes a great deviatlon due ~o the manufacturi~g pr~cess and a grea~
change dependlng upon the temperature, and the control of Vth is a dlfficulty in the manufacture of the MOS LSI.
In thls ~nventlon, as ~hown by way of example in ~igure SO, a bla~ voltage VBB is applled to a siIicon substrate of a MOS memory IC to redu~e parasitic capaci-tance In order to obta~n the bias vol~age VBB, a substrata bia~ generator clrcult SBGC is employed. me substrate blas generator clrcult SBGC has an arrangement 25 whlch is lllustrated ln Flgure 47, In ~his lnvention, ~e comparator employing the difference o~ the work functions of the gate electrodes of MIS FET~ as previ~usly s~ated i9 used ln the substrate blas genera~or circult S~GC so as to co~trol V~ into a constant voltage.
~ 95 -~5~3 Yth c~ange~ in dependence on the substrate bias V~B, and ls expressed by the followlng equation:
Vth ~ V~ho ~ ~ (2 0F ~ ~ VBB I ~) where VthO denotes V~h when the substrate bias ~oltage VBB - O V, K denotes the substrate effeet constant, and 0F
denotes the Fermi level. m erefore, Vth is controllable by varylng the substrate blas VBB. ~ substrate blas voltage generatlng circuit SBGC shown ln Figure 47 has a ~th sense portion 471, a comparator 472, an oscil-latlon clrcuit 473 and a waveform shaping por~io~ 474.
m e osc~llstion clrcuit portion 473 may be replaced with another oscillatlon ~ircuit. The wave~orm shaping por~ion 474 is composed of two MOS diodes Ql and Q2 and a capa-cltor Cl, and it ~u~ctions to drawlng out charges of VBB
to the earth poi~ by a pumplng ac~lon, Owing to the pumping action, YBB is ~rawn towards a nega~ive voltage.
age VBBM of IVBBI is determined by a point at wh~ch the drawlng-out vol~age owlng to ~he pumplng act-lo~ and the substrate leakage current are stabilized.
As long as the os~illatlon clrcuit ls operatin~ VB~ i5 held at the stable point VBBM. After stop of the oscll-latlonl howeYer, the charges o~ the substrate leaXs due to ~he substra~e leakage current and YBB approaches the ground level. ~hen ~BB ha~ become close to the ground level, Vth lowers..
The comparator portlon 472 in Figure 47 exploits the dlfference of the Fermi levels of the ~ate electrodes, and an example ln the N-channel process ~s show~ in Flgure 21, m e comparator portion 472 employs an intr~hsic silicon gate MOS as ~ ln Flgure 21, and an N
- 96 ~
~ ~ ~ 5~ ~
gate MOS as Q2. These are depletion type MOS. Therefore, ~his comparator e~fects ~he in~ersion when a voitage of 3 0.55 V has been put lnto an in~erting input (-).
The Vth sense por~lon 471 in Figure 47 is composed of a resistance and a dlode-connected ~iOSFET ~ ere, ~he reslstance may be either a polyc~ystalline silicon dlffused layer reslstance or a MOS resistance, and the resls~ance v~lue ls set so that an output may become 0,55 V when Y~h ~ Q3 has become 0.55 V. Now, when the substrate bias vol~age YBB ls close to the grou~d level and Vth OL ~3 is below 0,55 V, the (-) input voltage of the comparator portion becomes below 0.55 Y, the output of the comparator becomes "1" and the oscillation circult continues to operate. '~hen the substra~e blas Yoltage VBB approaches VBBM and Vth rises and exceeds 0.5? V, the comparator output becomes "O", ~he oscillation ceases and ~he substrate blas ~oltage VBB becomes close to ~he ground level due to the leakage. That ls, since a ~eedback loop is ~ormed, Y~h is controlled ~o th~ s~able point by this substra~e bias generator clrcult SBGC, The voltage O,55 V ob~ained in the comparator portion 472 is 1/2 of the energy gap, which ch~nges lit~le against temperature changes, manufac-turing dispersions and supply voltage fluo~uations, l~erefore, it becomes possible to control Vt;h at a very high preclslon~ and a MOSLSI whlch is wlde in the tem~e~a-~ure margln, the ~anufa~turlng process margin and the power supply margin ls ob~alned, ~s will be stated later, also tn point of the process, the lntrln~ic silicon gate MOS Ql f the comparator portlon 472 can be obtained.
by quite an identical process to that ~or obtaining a ~S~3 . .
. .
. .
high resistance load R in a memory cell shown in Figure 51, so ~hat the control of V~h can be readily realized wlth the prlor-art process.
:` Level Shift Cir.puit In case w~ere a 5 V power supply is employed as a power source ln a MOSLSI and where Slgnal3 from a TTL
logic circuit are employed as lnputs, ~he outputs of the TTt- logic circuit be¢ome 2.0 V as a high level and 0.8 Y
as a low le~el, In conYerting the TTL sig~als in~4 the ~!OS
levels, it has heretofore been carried out to ~ke ~he ratios of inverters in an input portion and to convert them into tbe MOS le~els. Howe~er, there has been the probl~
that the inpu~ level margin becomes small on account of the disper~ion o~ Vth and tem~erature changes.
Flgure 45 shows a TTL-~ MOS slgnal lèvel con~erter clrcuit wbich employs ~he reference ~oltage Yre~ generated from the refere~ce Yoltage generator clrcuit utilizing the di~erence of the Fermi le~els of the gate electrodes as pre~ously described. The slgnal level converter circult in Figure 45 i preferably applied to ~he address buffer clrcults XAB and YAB o~ the MOS memory shown ~n Figure 50. A~ the ref.e~e~ce Yol~age Vref, ~he reference ~oltage of 1.4 Y i~ genera~ed by the foregoing reference voltage generator circult o~ ~igure 15. A differential ampllfier employ~ng MOSFETs in Figure 44 ls employed as an ampllfier (~P) ~n Flgure 45, and an lnput buffer in which the log~c ~hreshold volta~e of ~n input ~s 1.4 Y
equal to ~he reference voltage Vr~f i~ prepared. Wl~h ~he present method, the TTL - ~M~S sign21 le~el converter circuit is obtained.
Alternatively, a signal level conver~er circuit w~hich has the logic threshold voltage of 1.4 Y can be obtalned by employing the circuit shown in F~gure 13 as the ampll~ier (A~) in Flgure 45. The inphase lnput (+) ~ is grounded as shown in Figure 14, and an address signal Ao - A4 ls applied to the antiphase input (-~0 As the translstor~ Tl and T2 depletion type MOS ~s are used. By making the threshold voltages Vt~l and V~h2 of the respective FETs unequal, ~e operational.
amplifler is endowed with an i~put offset vol~age of 1.4 ~.
A clrcult in Figure 46 intends to al~ays hold the logic threshold voltages of loglcal clrcuits such as inverter cons~ant against changes in the service supply 1~ voltage, the threshold voltages of ~IOS trans~stors, tem-peratures,.etc.
An inverter 1 composed of Q2 and Q3 and an inverter 2 composed of Q5 and Q6 are especially pro~ided wi~h ~IOS
FET~ Ql and Q4 for controlling logic thresholds, respec-tively.
A logic threshold detector circuit 3 ~ich is composedof a con~rolling MOSFET Q~ and an lnrerter tQ8, Qg) with its lnput and output coupled i~ constructed so as to be simllar to the i~verters 1 and 2 s~ated above tthe patter~ size ratios of MOSFETs are equal)~ ~rln2 to the coupling of the input and output of the inverter (Q8~ Q9)~
Just the logic threshold voltage is obtalned, CMPl lndicates the comparator circ~ preY' ou~ly ~tated with reference to Figures13 and 14 which has ~he ~o reference Ycltage Vref as the o~Lset o~ the dlf~erentlal ...
;363 circuit. The comparator clrcult CMPl compares the logic threshold an~ the reference voltage possessed therein, and control3 the gate Yoltage of the controlling MOSF~T
Q7 so that the dif~erence of both the voltages may become substantlally O (zero).
More speclfically, i~ the logic l~hreshold ~ the reference ~oltage (Vref), the output of ~MPl becomes a hi~h level, and the equivalent resistance of Q? lncreases and this t~ansistor functlons in the d~rectlon of lowering ~he logic threshold, In case where the logic threshold ~ the reference ~oltage (Vref) t` the converse ls true.
Both the voltages fall lnto the e~llibrlum state when they are e~ual.
~ The gate voltages o~ the controlling ~OSFETs Ql and Q4 ar,e common wlth the gate voltage of the controlling MOSFET Q7, and the former transistors and the latter ~ransi~tor a~e in the similar relatlQnship. Thus, ~he loglc thresholds o~ the in~erters 1 and 2 become e~ual to the re~erence ~oltage, and ~ery stable in~erter charac-teristlcs are exhiblted.
As stated at the beglnning, this is not restr~cted o~ly to the inv~rters, but is sim~larly applicable ~o the o~her logical circuit~ such as NAMD and NOR.
mis ls readily applicable to the case of in~erters and the like logic~l circuitQ of ordlnary single-channel types, not the CMO~ construction, These clrcults are useful as input in'erface circuits which can dlgitally process slgnals rellably especially when the ranges Qf input le~els and logic amplitudes are narrow.
" j - 100 -~5~3 :
.
There wlll now be explained specific examples in ~hich the reference voltage generator means accordlng to this invention ls applied to a status setting circult (an auto-clear circult) for electronic devices.
Flgure 48 i~ a circuit diagram showlng an example of a sta~us setting circuit, ~h~ch is a fllp-flop circult constructed of two in~er~ers each including ~wo MOS~ETs.
Referring to t~e ~igure, in case where potentials at polnts a and b are O (zero), both the MOSFETs Tl and T3 falls into the "ON" state upon closure of a power supply (-VDD) because they are N-channel MOSFETs, Simultaneously with the closure of the supply voltage, the polnts a and b change towards the supply ~oltage (-VDD). At ~his tlme;
the Fermi levels of the gate semiconductors of the N-channel MOSFETs Tl and T3 differ from each other, and ~he ~hreshold ~oltage Vth3 of the MOSFET T3 ls a~out three time~ gre~ter than that Vthl of ~he ~O~FET Tl (example:
Vthl ~ 0.45 V, V~h3 Y 1.25 Y). m erefore, in the course of the fall of the supply vol~age, the MOSFET T3 turns "OFF" previously, Since ~he MOSFET Tl continues to be ln the "ON" stste~ the points b a~d a are respectively stabi~
lized at -VDD and the ground potential.
In case where, wlth the power supply (-YDD) disconnec-~ed, the pol~t a i9 at O V and charge3 remain at about 1 V
at the point b, T3 ls in the "OFF" s~ate till VDD , Yth~
ln the course of the fall of the supply ~oltage, and the MOSFET Tl ialls lnto the '10N" state at ~V~D ~ Vthl-Therefor~, even when the polnt a has been O Y and ~he point b has been about 1 V (or up to VthN o~ T3) ln the inltial state, the point b becomes VD~ and the point a ~ ~ ~95~ ~ 3 becomes O V in the stable state. Further, slnce all the FETs are constructed o~ E(enhancement)-IIOS~ETs in the present circuit, the current consumption in t~e stable state is almost æero.
Fl~ure 49 is a c~rcuit diagram which shows ~n example of a status setting circuit having heretofore been proposed. Referring to ~he ~lgure, the threshold vol~age Vth of MOSFETs T2 and T4 are equal to each other, a~d an N-channel D (depletion) MOSFET Tl ls inserted in order to increase the stabillty of a latch circui~. Owlng ~o t~e D-MOSFET, upon closure of the power supply (-V~D), the point a falls simultaneously with ~ha power supply without fail, and the point b does not tu~n "ON" unless the supply ~oltage falls to Vth of the MOSFET T4, so that the point a and the point b become -VDD and O V ~n the stable state respecti~ely. Slnce, however, the r-MOS~ET ls lnserted between the point a and -VDD in the present cir-cuit, ~he P-~IOSFET T3 turn~ "ON" when the s~ate in whlch the point b is -VDD and the polnt a ls O V (R23ET) is sub-sequently established from some reason, and a ~.~. path due to ~ a~d T3 arises to result in a high current consumption. In contrast, with the 3tatus setting clrcult of this invention as shown in Flgure ~8, the status settlng can be reliably done and the current consumption is ~ery low as described above, a~d hence, effective status setting means can be proYided.
Nowt ~n embodiment in ~hich thls lnvention is applied to a semiconductor random access memory (~I) will be descr~bed.
In general, in a storage de~ice constructed of S~63 a static RAM, the voltage control of lowerlng a supply voltage is carried out in order to reduce power dlssipa-tion at the time when the storage device is not used tstand-b~ status) Thls is called ~he data retent~on ~ode.
S In thls case, a slgnal voltage is lowered simultane-ously with the supply voltage~ In this regard, s~noe a power supply llne has a greater time constant ~han a signal line, the sig~al ~oltage lowers to a predetermined ~alue faster, Usualiy, ln a semiconductor RAM, a read control slgnal is set at a supply vol~age leYel, a write control signal at a reference voltage level, and a chlp select signal at a reference potential le~el.
In the data retention mode, therefore, the level of the control slgnal lowers faster than the supply volt~ge, so that the read control si~nal becomes ~he wrlte control signal le~el lns~antaneously and that ~he chlp select si~nal ls formed. For thls reason, the write operatlon is ef~ected instantaneo~sly, and the information of a blt selected at that time ls destroyed.
In order to solve thls problem, in a RAM construc~ed of field-effect transistor of a single cha~nel, it ls considered to dispose a tlme constant circuit for making the tlme cons~ant o~ the signal llne greater ~ti~h thls measure, however, an external clrcult is requlred, and the control signals are ad~ersely affected.
In a ~-MOS (complementary MOS) lntegrated cireui~, a p-n-p-n element is prone to be formed on accoun~ of the structure thereof. Therefore, ~rhen the slgnal ~ol~age is made hlgher than the supply voltage~ such a p-n p-n element operate~ and a great current flows between the supply voltage and the re~erence po 4ential . ~or th~s reason, a tlme constant circuit wi~h which the sign~l vol~uQge and ~he supply voltage lower at the same time must be selected ~or the C-MOS memory.
These fact3 are serious problems in the design and manufacture of storage devices on ~he side of the user of memory chips.
In ~his regard, lt ls deslrable that a circuit for sensing the lowering of the supply voltage is contained ln the same chip as that of the R~l. Howe~er, MOS~ETs on the semlconductor ch~p have ~he tempera~ure dependency of threshold voltages V~h, manufacturing de~atio~s, etc., and lt has been di~icult to obtain a detection voltage necessary for ~he senslng at hig~ precislon.
Hereunder, this inYention will be concretely descrlbed along an embodiment Figure 52 ls a block dlagram of a statlc type semi-conductor memory lntegrated clrcult device showing an embodiment o~ this in~ention.
In the figure, 1 designates a memory matri~ (64 x 64 bits) circuit which is constructed of static memory cell~.
2 designa~es an X-decoder circuit. It discerns an informatlon pattern assigned by a row selec~ signal (Ao - A4) and applled through a buffer clrcu~t BC, to assign a row-(X~ line of 1/64.
3 indicates a Y-decoder and input/output circuit.
This circult 3 discerns an information pat~ern assigned by a column select slgn 1 (A5 - ~ ) and appl~ed through a buffer circuit BY, to asslgn a column (Y) llne of 1/64.
~5~3 It also gi~es the assigned column line of ~he memory matrlx an input data applied through gates t~a~ It also provides an output data from the assigned column line to ter~'nals (1/01 - 1/04) ~hrough gates RB.
4 indicates an input data control circuit, which gives the input/output circuit the input data to-~e-written, (1/0~ 0~) lnd1cate irput/output t~rminals.
(~) denotes a chlp sele¢t signal, which indicates the selection of th~s chip by the "0" level i.e. reference potential level.
(WE) denotes a write/read con~rol signal. It si~nifies the write operatton when ~t is at ~he "0" level i,e. Lhe reference potential level, while lt sl~nifles the read ' operation when it is at the "1" level i,e. supply voltage level.
5,6 designate gate circuits which are alternately controlled by the control signals, That is, only when (~) is "0", the gate circuits are controlled by either "0" or "1" of (WE), to execu~e ~he write or read operation, 7 designates a voltage detector circuit. It detects the data retention de on the basis of the fact that the supply ~oltage has become below a predeterm1ned voltage, and lt controls the gate circuit 5 so as to 2S 1 nh~ bit the (W~) at that time. Thus, the malf~nction as previously described is prevented, An example of the concrete arrangement of the voltage detector circult 7 is shown in Figure 53(a).
Resistors (Rl? ~2) connected in serles constitute a circuit ~or dl~ding a supply vol~age tVcc). The vol~age ~1~5~3 .
divider clrcult applies a divided voltage (a) to the gate of an N-channel MISFET (Q2). The supply voltage (VcC) is applied to the gate of æn ~-channel MIS~ET (Q4).
A ~IISFET (Q5) has its gate supplied wlth a suita'ole bias voltage from (d), and constructs a constant-curren~
source. It constitutes an opera~ional ampl~fler, together wlth load MISFETs (Ql) and (Q3) and the two differential inout MISF~Ts (Q2) and (Q4).
The dif.~erenti~l lnput MIS~ETs ~Q2) and (~4) are f~rmed on, for example, N-type silicon laye~s of equal conductivities, and the respecti~e gate electrode~ arP
made of di,ferent materials so that the threshold ~rolea~es may become 2?nequal. The gate electrodes of the two MISFETs (Q2) and tQ4) are made o~, for example, silicon, and their condu`ctlvlty types are made ~ifferent. The MISFET (Q2~ has the N-~ype silicon gate, whereas the ~SFET (Q4) has the P-type silicon gate. As a result, the threshold ~oltage (Vth4) of the MISFET (Q4~ becomes greater than ~he threshold voltage (Vth2) of the '`IISFET
(Q2) by the dif~erence of the Fermi levels of the P-type and N-type silicon gates.
Accordingly, ~he operational amplifier has an of.set voltage e~u~ to the difference of the threshold voltages.
Under the state under which the supply voltage Vcc is comp~ratively great in ~he clrcuit o~ Figure 53~a), ~he MISFET (Q4~ ls in the "on" state and ((;~2) ls in ~he "off" s~ate, ar~ the pote~tial of a point c is at ~he low le~el. D~e to the lowering of the supply volt2ge YCC . the poten~ial of the point (a) changes as indicated by a curve a in Flgure 53(b). '~hen, due to the loweri~g ..
~ 3 of the supply voltage Vcc, the potential dlfference b~t~reen the s~pply voltage Vcc and the potentlal of the point a has become smaller than the offset vol~age, the MISFET (Q4) falls lnto ~he "off" state &n~ (Q2) ~alls into the "on" state. In consequence, the potentlals of the points D and c in the clrcuit of ~iO~ure 53(a) change as indicated by curves b and c in Figure 53(b), respectively. That is, the potential of the point c becomes the high level when the supply voltage Vcc has lo~ered to a predetermined value.
As described above, '~he detection level of the clrcuit of Figure 53(a) is determined ~y ~he offset voltage owing to the MISFETs (Q2) and (~4) and the divided voltage owing to the reslstors Rl and R2, I~ is ~ot affected by the threshold voltages of t~he respect~ ~re ~SFETs, The offset voltage is at a comparatlvely high preci-~ion becauqe lt ls declded by the dlfference of the Fer~l levels of the gate electrode~ of the ~wo MISFETs (Q2) and tQ4) as stated previou~ly, Since, in a semiconductor integrated clrcuit9 the relative values of the reslst~ces of resistor elements are at a comparatively high precision, the ~oltage dl~islon ratio owing to the reslstors (21) and ~R2) ls at a comparatlvely high precision.
As a result, the detection level of the circuit of ~igure 53(a) can be set comparatl~ely accuratel-;.
In Figure 53(b), a waveform (d') lndicates the output of ~he gate circuit (5) during the data reten'ion m~de durlng which the gate clrc~-t (5) is not controll2d by the detection outDut, ~ ~ ~ 5~ 3 In the data retention mode, the input control signals (~) and (~E) lower ~aster than the supply voltage (Vcc) o~ the gate c~lrcuit (5). Therefore, when the dlfference of both the voltages has become above the logic threshold, the output waveform td') as stated above is generated.
This forms the cause of the malfunction explained before.
According to the circuit of ~he present embodiment, however, the control signal (c) is applied to the input of the gate circult (5)~ so tnat the waveform (d') is inhibited ~rom being pro~ided. Thus, the erroneous wri~e ln the data retention mode can be prevented, and data stored in the matrix memory are not destroyed.
In accordance with the embodiment set forth above, the erroneous write in the data retent$on mode can be perfectly prevented. Moreover, the detector circuit can be constructed with the slmple clrcuit arrangement a~d can be contalned in the memory chip, It is therefore unnecessary to care for the prevention of malfunctions on the side of the user of the semiconductor memory device.
For example, the gate circult which is controlled by the voltage detection output may obtain the chip select signal. All the memory cell select signa~s may b~e lnhibited so as to select no memory cell.
~his is because the erroneous wrlte can be preYented when one of conditions necessary for the executlon of the write operation is inhibited.
The voltage divider c~rcult which constitutes thQ
voltage detector clrcuit in the prevlous embodlment may utllize resis~ance by means of MISFETs inste2d o~
the resistor elements. Deslrably, the resistance of this - 1~8 -~5~,3 voltage di~ider clrcuit is made a large value ln order to make the power dissipation low, The twc MISFETs of the foregoing embodiment which have sllicon gate electrodes of conductlvity types opposi~e to each o~her are fabricated within a silicon monolithic semiconductor lntegrated circuit chip. Since these FETs are manufactured under substantially the same condi~lons except the conductivity ~ypes of the gate elèctrodes, the dlfference of the threshold voltages Y~
of both ~he FETs becomes approximately equal to the d~-ference o~ the Fermi levels of P-type silicon and N-type silico~. The P-type and N-type gate elec~rodes are doped with re~pecti~e impurities to the vicinities of the satura-tion densities, and the difference becomes approximately equal to the energy gap Eg of slllcon (about 1.1 V), which is util~zed as a reference voltage source.
The reference voltage generator device based on such a construction is low in the temperature dependency and small in the manu~acturing deviations~
The voltage detector circult 7 can be modi~ied varlously, That is, the re~erence voltage sources which exploit ~he dlf~erence o~ the Fermi le~els of semiconductors forming ~he gate elec~rodes of tw~ MOS FETs as shown in Figure 6(b), Flgure 8, Figure 9, Figure lO(a), ~igure ll(a), Flgure 12, Figure 13, Figure 14, Figure 15, Flgure 16 and F~gure 17 are ef~ecti~e as ~he reference volta&e source for the voltage detector ~ircult of ~his invention, To this end, there can be employed two FETs which have semiconductor gate electrodes of different conductlvlty ~5~3 -types as already explained with reference to ~lgure 59, for example, a MOS transistor with its gate electrode made of a P -type semlconduc~or or a P+-gate MOS translstor and a MOS transistor with its gate electrode made of an N~-type semiconductor or an IY+-gate MOS translstor. As already described with reference to ~igures 73(a) to 73(f), the above two FETs can be manufactured without the change or addltion of any step by the con~entional CMOS manufacturing process, In case of employlng ~he conventional CMOS ma~ufac-turing process, the self-alignment structure as shown in Figures 65(a) and 65(b) and Flgures 66(a) and 66(b) is obtained as stated below~ 3ince the MOS translstors are of the P-channel in this case, a P-type lmpur~ty is diffused into bo~h end parts of a gate electrode ad~olning the source.and draln in both the P~-gate MOS and ~he N~-gate MOS. In a central part of. the gate electrode, a P-type impurity ls diffused ~or the P~-gate MOS, and an N-type impurity is diffused for the N~-gate MOS, Between the cen~ral region and both the end par~s ad~oin-lng the source. and drain9 regions i in whlch no i~purlty is diffused are disposed. mus, lt ls considered that the difference of the P~-gate MOS and the N~-gate MOS is only the conductivity type (P or N) of ~he semlconductor form~ng 25 the central reglo~ of the gate.
~ urther, in order to reduce to the utmost the devia-tion (difference) of the effecti~e channel leng~hs of the MOS transistors attributed to the fact that the regions of the ga~es which are formed for the self-al~gnment a~d in 30 which t'le P-type imp~ity is dlffused shlft onto elther ~5~6~
the left or right side (source side or drain side) during manu~aoture on account of the error of the mask alignment, the columns of the source regions and the d~aln regions are alternately arranged, and the left hal~ and the right hal~ are put into a line symmetry ~rith respect to the channel direction as a whole. ~ccordlngly, even when the misregistration of ~le mask alignmen~ with respect to ~le char~lel direction (lQf~ward or rightward shifting) changes the effective channel len~ths of the FETs ~n ~h@ respective columns, the average effectlve channel lengths of the P~-gate MOS and the N~-gate ~ICS
in the respectlve columns connected in par211el have the s~ifting canceled as a whole and become substantially . constant, Besides by ma~ing the compositions of the gate elec-trodes different, unequal threshold voltages are realized by the ion implan~ation into channels as described with reference to Figure 7, by utilizing a doped gate oxide, by changing the thickness of gate insulatlng film~, etc, An example in Figure 54 is the example in whlch ~he battery checker of the ex2mple of Figure 20 ls applied to an electronic timepiece.
Tl~ T2~ T41 T49 and R41 and R42 constitute a clrcuit which checks the ~ol~age level of a mercury battery El having a nominal voltage o~ 1.5 V. A translstor pair (Tl, T2) in a differential portion is constructed of a P+ gate N-ch~nnel ~OS Tl and an N~ gate ~-channel ~IOâ
T2 t~e channel portions of which are sub;ect~d '~ ion implantatio~ so that the threshold voltages of both the transistors may lie within loO V to 1~5 V beinO the ~ .
~ 6 3 operating power supply range of the electro~ic timepiece.
The di~ference of the threshold voltages to serve as a reference voltage ls about 1.1 V in case of a silicon semiconductor. In order to set at about 1.4 V a level for de~ecting that the vol~age of the battery El has lowered, an ad~ustment is made by the resis~ance ratlo of the resistance means R41 and R42.
In order to make the current consump~lon negl ~ible in practical use, the battery checker is lntermi~ten ~y operated by a clock si~nal ~ whlch is ob~ained from a frequency divider circuit ~D and a timi~ circuit ~'.
An output of the battery checker is statically held by-a latch which is composed of NAND gates ~JA
and NA2 ~he timlng circuit TM is controlled by a logic leYel of an output from ~he latch circuit, whereby a dr~vlng output of a motor is changed and the ~ethod of mo~ing hand o~ the timepiece is changed so as to indica~e the lowering of the battery vol~age. The lowering of the battery voltage can also be lndlcated without chang-ing ~he movements of the hand and by, for exampl~, fl~cker-ing an electrooptic device such as a llquid crystal and light emi~ting diode.
Xn the figure, OSC indicates a crystal oscillator circuit which is constructed of a CTfilOS inverter and which al~o includes components outslde the IC, a crystal Xt and capacitances CG and CD. WS ~ndicates a waveform shaping circuit which converts the oscilla~,~on outpu~
from a slnusoldal wave into a rectangular Yra~,e. C~l indicates an excitatlon coil of a step ~otor for driv~ng the second hand. BFl and 3F2 indicate bu~ers ~trhich are ~ ~ ~ 5 ~ ~
cons~ructed of CMOS inverters and ~ich serve to drive the exclta~lon coil ~ while inverting the polaritles every second, All the circults withln the IC are operated by the mercury battery ~1 f the no~inal 1,5 V. ~l is the tlming pulse generator circult which revei~es a plurallty of frequency dlvision outputs of different frequencies from the frequency divider clrcuit ~D and the control output of the latch composed o~ MAl and NA2 and which generates pulses having any desired period a~d pulse width. The IC is of a monolithic ai semiconductor chip for a hand type electron~c wrist watch which is fabricated by the Si gate CMOS process alread~J e,Yplained ' with reference to Figures 73(a) - ?3 (f).
Figure 55 shows an example of the co3struction of a circult system for an electronic wrist watch con-taining a battery checker thereln. In this example, the conductances of FETs Q4 and Q5 of a differential circuit are made unequal as in Figure 39, and the detectlon level can be finely ad~usted by means o~ an adjusting reslstor R~ outside the IC.
Owing to the resls~or R~, de~iations ln the ma~u-facture can be per~ectly avoided in use, Now, an example in whlch the ~oltage regulator as shown in Figure 36(a) is applied to an electronlc tlme-piece wlll be explained with reference to Flgure 56, In Figure 56, OSC designates a crys~al osclllator, WS a waveform shapi~g circuit which converts a sinusoidal wa~e oscillation output into a rectangular wa~e, F~ a frequency di~ider circult, IM a tlmlng pulse generator ~ 3 circuit which prepares pulse~ of predetermined period and width from frequency division outputs, LF a level shift clrcuit which converts a signal of low level into a signal of high le~el, BC a bat~e~y lifetime detector, VC a voltage comparator, VR a vol~age re~ulator ~ch uses the voltage comparator VC, H a hold circuit, DT
an oscillation state detector, and ~M &n excl~a~ion coil of a step motor for driving a second hand.
The detector DT detects it through the f equency dl~ider FD and the timing circuit TM that the oscillator OSC has oscillated, In case of the oscillatio~, it actuates the volta~e regulator V~ to drop t~e operating voltage VOp of ~he oscillator OSC as well as .~S, FD, ~l etc. into a value below the battery voita~e (-1.5 ~).
The moment a battery E is turned "o~", ~he lnput node of an inverter I7 becomes the earth potential (logic "O") owing to a dlscharging resistor ~104~ so that an N-channel FET Q201 is brought i~to the "0~"
state and that the output o~ the regulator is made -1 5 V being the battery voltage. At this time, a ~T
Q203 is also turned "ONn, and the gate node of a ~ET Q202 is charged. This is to the end of pre~iously making the negative ~eedback loop of the regulator active lest ~he regulator ou~put should drop ~he moment the FET Q201 is subse~uently switched "OFF".
Wher the oscillator has started operatlng, the other logical circults are already in the operative s~ate, so that a pulse ~ ls supplied from the timing circult TM to the detector DT. ~ e~clusive OR circui~
EXl detects the issue of the pulse P'B One lnput thereo ~5~3 rece~ves the pulse ~B delayed by inverters I4 and I5 and an integration circuit C10l and Rlo~ ~itn respect to the other. Upon the issue of the pulse ~, accord-ingly, a pulse of a width corresponding to the delay time is provided at the output of ~le gate EXl, This pulse is lntegrated by a rectif~er circuit made up of a F~T
Q225' an inverter I6 and a capacitor C102? and turns "OFF" the N-channel FETs Q201 and Q203 P
a snort time from the beginning of the issue f ~B~
mus, the reO~ula~or VR generates a predetermined voltage (less than 1.5 V) at the source electrode o, the con-trolling P-channel FET Q202 by the nega~ive feedback cor.trol loop, ~nd it contributes to reduce the power dissipation ,~ of the electronic timepieceO
Hereunder, the opera~ion of the regula~or, especially the ~oltage comparator VC will be explalned, Slnce this comparator VC ef~ects an operation ~imilar to that of the comparator CP described with reference to the principle dia~ram of ~igure 35(a) and the characterlstic dlaOram of Figure 35(b), only a brlef explanation ~11 be given.
Regard~ng P-channel r~lOSF~Ts Q206 and Q207' in order to obtain the offset voltage Voff, the gate of Q206 is made the P-type as ln Ql of FiO~ure 60 and FiO~ures 67(a) and 67(b), and the gate of Q207 is made the i-type (intrinsic semloonductor) as in Q2 of FiO~ure 60 ~Lnd Figures 68(a) and 68(b). Accordingly, the threshold ~oltage Vth f Q207 becomes higher than ~hat ~ Q206 by abou~ 0~ V, wnich serves as the aforeclted offset voltage Voff.
On the other hand, sinoe both an N-channel ~ET Q2~8 and a P-channel FET Q209 are dlode-connected, the sum of 5~3 both the threshold voltages Yth i-e- (V~hp209 + Vthn208) is applied to ~he gate of Q207 being the non-inverting input (+) of the comparator VC, and the sum serves as the voltage Vre~2 as indicated ln the curve d in Figure 35(b).
On the other hand, the gate of the ~ET Q206 being the lnvertlng input (-) of the comparator is connected to the source of ~he controlling P-channel FET Q202 of the source follower type Accordingly, the output voltage VOUt of ~he voltage regulator VR which is generated at ~he source of the con-trolling FET Q202 under the control actlon of this control-ling FET Q202 driven by the comparator VC becomes VOUt _ thp209 Vthn208 + ~Voff (in case where Vin 2 Vthp ~
~ Vthn ~ ~Voff)~ When the input voltage Vin is low, the output voltage becomes VOUt - Vin as in the foregoing.
Of course, the output voltage VOUt of ~he voltage regu-lator VR is utilized as the operating voltage VOp of the oscillator OSG as well as WS, FDI ~M, etc.
Ir, order to render the power dlss~pation low, thls comparator has the opera~lng time llmited by a timing slgnal ~A owing to ~he on-o~f operatlon of the driven ~ET
Q211 f cour~e, the same applies to the c~rcult for ob~ainlng the reference ~oltage Vref2 To this end, a oapacitor C104 lq connected to ~he gate of Q207 and a 2S capacitance C105 is connected to the gate of Q202 so as to hold the voltage of the reference voltage~rref2 and to hold the gate Yoltage of Q202' respecti~ely. These capaci-~a~ces C104 and C105 are added sepa~ately from parasitic capacitances such as ga~e capacl~anceq A capacltor C103 serves to prevent any oscillation which is attributed to a phase rotation caused by the cascade connectlon of sev-eral ~ETs in the feedback loop.
Since ~he battery checker BC has a construction slmllar to that in Figure 54, the explanation is omltted.
At the output stage of the IC, drlvers I2 and I3 for the exc~tation coil directly use the battery of 1.5 V as the power supply in order to make the driving capabillty high Flgure 57 shows an example in which the voltage regulator VR and ~he battery chec~er BC according ~o this inventlon are applied to a digital display electronic tlmepiece.
In the figure, parts OSC, '~tS and r~D use an adJusted voltage lo~ter than 1.5 V as a power supply as in the ex~mple of Figure 56, and also loglcal clrcuits within an IC such as decoder DC and time correction circuit TC
u~e the lower voltage as a power supply.
DB designates a voltage doubler circult whlch boosts the voltage of 1.5 V to 3.0 V, which is used as a driYe vol~age for a li~uid crystal display DP (a driY.er ~s not shown). Each of LSl and LS2 indica~es a level shift circuit, which converts a low $1g~al level into a high one D,C.-wise and supplies lt to circuits of high supply vol~ages, It ls effective for rendering the power dissipatlon low and the expanslon of a service power supply range that, as thus far described, the low opera~ing power supply is used for the ordinary lo~lcal circuits within the IC which operate at low operating ~oltages, while the high operating power supply i~ used for the display - 117 ~
driver etc. at the lnput/output lnterface of the IC
whlch require high operating voltages.
: - 118 -
Claims (5)
1. A method of manufacturing a semiconductor device with at least a pair of insulated gate field-effect transistors having semiconductor gate electrodes of different conductivity types, comprising the steps of:
preparing a semiconductor substrate having a semiconductor region of one conductivity type extending to a major surface of said semiconductor substrate;
forming an insulating film over said major surface at a first portion of said semiconductor region and at a second portion of said semiconductor region, and forming a semiconductor layer of a first conductivity type over said insulating film overlying said first and second portions of the semiconductor region;
removing said semiconductor layer to form first and second semiconductor gate electrodes at said first and second portions of the semiconductor region respectively;
selectively forming a mask over said first semi-ductor gate electrode except for said second semiconductor gate electrode; and selectively introducing an impurity of a second conductivity type different from said first conductivity type and opposite to the conductivity type of said semiconductor region into said first and second portions of the semiconductor region using said mask, to form source and drain semiconductor regions of the second conductivity type on opposite sides of each of said first and second gate electrodes, and to convert the first conductivity type of said second semiconductor gate electrode to the second type as well as to convert the first conductivity type of the periphery positions of said first semiconductor gate electrode to the second conductivity type.
preparing a semiconductor substrate having a semiconductor region of one conductivity type extending to a major surface of said semiconductor substrate;
forming an insulating film over said major surface at a first portion of said semiconductor region and at a second portion of said semiconductor region, and forming a semiconductor layer of a first conductivity type over said insulating film overlying said first and second portions of the semiconductor region;
removing said semiconductor layer to form first and second semiconductor gate electrodes at said first and second portions of the semiconductor region respectively;
selectively forming a mask over said first semi-ductor gate electrode except for said second semiconductor gate electrode; and selectively introducing an impurity of a second conductivity type different from said first conductivity type and opposite to the conductivity type of said semiconductor region into said first and second portions of the semiconductor region using said mask, to form source and drain semiconductor regions of the second conductivity type on opposite sides of each of said first and second gate electrodes, and to convert the first conductivity type of said second semiconductor gate electrode to the second type as well as to convert the first conductivity type of the periphery positions of said first semiconductor gate electrode to the second conductivity type.
2. A method according to claim 1, wherein said semi-conductor layer is made of polycrystalline silicon.
3. A method according to claim 2, wherein said first conductivity type is the intrinsic-type, and said second con-ductivity type is the P-type.
4. A method according to claim 1, wherein said first con-ductivity type is the intrinsic-type, and said second con-ductivity type is the N-type.
5. A method according to any one of claims 1, 2 and 4, wherein, after the step of selectively introducing the impurity of the second conductivity type, the central portion of said first semiconductor gate electrode is introduced with an impurity of the same conductivity type as said semiconductor region defining said first and second portions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000395811A CA1145063A (en) | 1978-03-08 | 1982-02-08 | Reference voltage generator device |
Applications Claiming Priority (23)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2544478A JPS54119653A (en) | 1978-03-08 | 1978-03-08 | Constant voltage generating circuit |
| JP25444/1978 | 1978-03-08 | ||
| JP35545/1978 | 1978-03-29 | ||
| JP3554578A JPS54129348A (en) | 1978-03-29 | 1978-03-29 | Constant voltage output circuit |
| JP3924278A JPS54132753A (en) | 1978-04-05 | 1978-04-05 | Referential voltage generator and its application |
| JP39242/1978 | 1978-04-05 | ||
| JP111719/1978 | 1978-09-13 | ||
| JP11172478A JPS5539412A (en) | 1978-09-13 | 1978-09-13 | Insulating gate field effect transistor integrated circuit and its manufacture |
| JP11172578A JPS5539413A (en) | 1978-09-13 | 1978-09-13 | Schmitt trigger circuit |
| JP11172278A JPS5539411A (en) | 1978-09-13 | 1978-09-13 | Reference voltage generator |
| JP111720/1978 | 1978-09-13 | ||
| JP11171978A JPS5539607A (en) | 1978-09-13 | 1978-09-13 | Reference voltage generation device |
| JP111723/1978 | 1978-09-13 | ||
| JP11171778A JPS5539605A (en) | 1978-09-13 | 1978-09-13 | Reference voltage generation device |
| JP111725/1978 | 1978-09-13 | ||
| JP111718/1978 | 1978-09-13 | ||
| JP11172378A JPS5538677A (en) | 1978-09-13 | 1978-09-13 | Semiconductor memory with function of detecting power failure |
| JP111717/1978 | 1978-09-13 | ||
| JP111724/1978 | 1978-09-13 | ||
| JP111722/1978 | 1978-09-13 | ||
| JP11172078A JPS5539608A (en) | 1978-09-13 | 1978-09-13 | Reference voltage generation device |
| JP11171878A JPS5539606A (en) | 1978-09-13 | 1978-09-13 | Reference voltage generation device |
| CA000395811A CA1145063A (en) | 1978-03-08 | 1982-02-08 | Reference voltage generator device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1145063A true CA1145063A (en) | 1983-04-19 |
Family
ID=27582866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000395811A Expired CA1145063A (en) | 1978-03-08 | 1982-02-08 | Reference voltage generator device |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1145063A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110828440A (en) * | 2019-09-03 | 2020-02-21 | 东莞市华彩威科技有限公司 | Packaged LED integrated with constant current control chip |
-
1982
- 1982-02-08 CA CA000395811A patent/CA1145063A/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110828440A (en) * | 2019-09-03 | 2020-02-21 | 东莞市华彩威科技有限公司 | Packaged LED integrated with constant current control chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4559694A (en) | Method of manufacturing a reference voltage generator device | |
| US5159260A (en) | Reference voltage generator device | |
| US4498040A (en) | Reference voltage circuit | |
| US5629546A (en) | Static memory cell and method of manufacturing a static memory cell | |
| KR960002825B1 (en) | Reference voltage generating circuit temperature-compensated without additional manufacturing step and the semiconductor device using the same step and the semiconductor | |
| US4435652A (en) | Threshold voltage control network for integrated circuit field-effect trransistors | |
| GB2086652A (en) | An insulated gate transistor with sit characteristics | |
| CA1149081A (en) | Reference voltage generator device | |
| FR2559323A1 (en) | ELEMENTARY LOGIC CIRCUIT REALIZED USING GALLIUM ARSENIDE FIELD EFFECT TRANSISTORS AND COMPATIBLE WITH ECL 100 K TECHNOLOGY | |
| US5424656A (en) | Continuous superconductor to semiconductor converter circuit | |
| CA1145063A (en) | Reference voltage generator device | |
| GB2099650A (en) | Electrically programable read only memory | |
| CA1189637A (en) | Insulated gate field effect transistor | |
| JPH08111462A (en) | Semiconductor memory and fabrication thereof | |
| CA1143010A (en) | Reference voltage generator device | |
| US5535155A (en) | SRAM cell having load thin film transistors | |
| EP0214561A2 (en) | Random access memory | |
| CA1154880A (en) | Reference voltage generator device | |
| US4942312A (en) | Integrated-circuit having two NMOS depletion mode transistors for producing stable DC voltage | |
| JPH0378007B2 (en) | ||
| CA1146223A (en) | Battery checker | |
| GB2081458A (en) | Voltage comparitors | |
| US4236170A (en) | Gate controlled negative resistance semiconductor device | |
| KR100406533B1 (en) | Sram cell | |
| EP0612152A2 (en) | A level shift circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |