JPH0243203B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reference voltage device that can be built into a semiconductor integrated circuit (IC).

[Conventional technology]

Conventional IC internal reference voltage devices have mainly been constructed from Zener diodes. In this case, there are many variations in the Zener voltage and the temperature characteristics are poor, so external adjustment terminals and compensation elements are always required.
Furthermore, Japanese Patent Laid-Open No. 53-47953 describes an embodiment in which the difference in threshold voltage due to channel doping is used as a reference voltage device.

[Problem to be solved by the invention]

According to the method of JP-A No. 53-47953, it is not possible to obtain the desired reference voltage completely without adjustment because the variation in the doping amount and gate film thickness for the channel affects the variation in the reference voltage. It was difficult, required some sort of external adjustment function, and was extremely troublesome to use.

The purpose of the present invention is to eliminate such drawbacks, and in order to minimize variations due to the manufacturing process, different threshold voltages are set based on the difference in work function between the gate electrode of the MOS transistor and the silicon substrate. The object of the present invention is to provide a reference voltage device which generates the difference between the threshold voltages as a reference voltage, completely requires no adjustment, and is suitable for mass production.

[Means to solve the problem]

The reference voltage device of the present invention includes a first gate electrode made of polysilicon into which a first conductivity type impurity is introduced, and a first source formed by introducing the first conductivity type impurity into a silicon substrate. - A first MOS transistor including a drain region, comprising a central portion and end portions located on both sides of the central portion, into which the impurity of the first conductivity type is introduced, and a second conductive type into the central portion. a second gate electrode made of polysilicon into which a type of impurity is introduced;
a second source/drain region formed by introducing impurities of a conductivity type and simultaneously introducing impurities of the first conductivity type into the silicon substrate adjacent to the end portion; ,
The reference voltage is generated by a difference between different threshold voltages of the first and second MOS transistors, which are set based on the difference between the work function of the gate electrode and the work function of the silicon substrate.

〔Example〕

FIG. 1 shows an example in which a reference voltage device is used in a battery voltage detection circuit for an electronic watch. The reference voltage device composed of MOS transistors 1, 2, 3, and 4 is described in detail in the aforementioned Japanese Patent Laid-Open No. 53-47953, and MOS transistors 3 and 4 are considered as a pair with different threshold voltages. The difference between the threshold voltages is output to point A. MOS transistor 5 is switched by clock φ and performs a sampling operation. Resistor 6 and Resistor 7
is designed to divide the power supply voltage so that the position of point B when the desired power supply voltage is applied is the same as the potential of point A, which is the reference voltage output. Therefore, the output of the comparator 11 is at level "1" because the potential at point B is higher than the potential at point A at the initial power supply voltage. Further, as the power supply voltage decreases, the potential at point A becomes higher than point B, and the output of comparator 11 becomes level "0". The output of this comparator is stored in latch 12 by clock φ.

The problem with this device is the structure for making the threshold voltages of MOS transistor 3 and MOS transistor 4 different for generating a reference voltage.

FIG. 2 is a diagram showing the basic configuration of a MOS transistor of the reference voltage device of the present invention. In the present invention, the difference in threshold voltage is obtained by the difference in work function between the material of the gate electrode and the silicon substrate. M.O.S.
The threshold voltage V _th of the transistor is determined by the following formula.

V _th =φ _G −φ _S +2φ _F +Q _D /C ₀ +Q _SS /C ₀ where φ _G is the work function of the gate electrode, φ _S is the work function of the silicon substrate, φ _F is the Fermi level of the silicon surface, Q _D is the amount of charge on the silicon surface, Q _SS
is the interface unit, and C ₀ is the capacitance per unit area of the gate. This φ _G is uniquely determined by the material of the gate, and in the case of a silicon gate structure, φ _G can be arbitrarily determined depending on the amount and type of impurity doped into the gate electrode. Furthermore, φ _S and φ _F on the silicon side are also uniquely determined if the impurity distribution is constant.

Figure 2 shows an N-channel with a silicon gate structure.
A pair of MOS transistors is shown. Figure 2
The MOS transistor 32 corresponds to that shown in FIG. 1, and the MOS transistor 33 corresponds to that shown in FIG. 1, respectively. A P ^- well 25 is formed in the N ^- substrate 26,
21 to 24 are diffusion layers serving as sources and drains. 27 is an insulating layer of _SiO2 , and 28 to 31 are Al for electrodes. The gate electrodes are 34 and 35, and a conductive channel is formed below these through a gate oxide film. The gate electrode 34 of the MOS transistor 32 is doped with the same N ⁺ as the source and drain through a normal process. On the other hand, the gate electrode 35 of the MOS transistor 33 is doped with P ⁺ of the opposite type to the source and drain. In this case, taking the intrinsic fermi of φ _G of the gate electrode 35 as a reference, +0.3 to +1.5 V, and φ _G of the gate electrode 34 is −0.3 to −
It becomes 0.5V.

Therefore, even if there are large variations in φ _S , 2φ _F , Q _D /C ₀ , and Q _SS /C ₀ between processes, it will affect the MOS transistors simultaneously manufactured on the same substrate, so the threshold voltage By taking the difference between the two, a reference voltage of about 0.6 to 1.0 V can be generated depending on the amount of doping to the gate electrode. Normally, the doping amount can be controlled fairly stably, and even if there is some variation, it is within ±10 mV.

FIG. 3 is an embodiment showing the structure of a MOS transistor in which the gate electrode is doped with impurities of the opposite type to the source and drain in the reference voltage device of the present invention. The MOS transistor in Fig. 3 is an example of a P-channel MOS transistor.
Like 33 in FIG. 2, it has the structure of a MOS transistor in which the source and drain are diffused in the opposite type to the gate electrode in the normal silicon gate process. P ⁺ which becomes the source and drain on the N ^- substrate 41
Diffusion layers 42 and 43 are formed. At this time, the central portion 45 of the polysilicon gate electrode is masked to prevent P-type impurities from entering. However, P ⁺ enters both ends 46 of the gate. After this 4
N ⁺ is doped using the oxide film 44 formed on the portions other than 5 as a mask. Although this is an example of a P-channel MOS transistor, an N-channel is formed in exactly the same way. In this structure, the central part of the gate electrode is N ⁺ and both ends are P ⁺ , and the Siqui value voltage is high below the gate electrode 45, and the Siqui value voltage is low partially below the gate electrode 46, but the Siqui value voltage of the MOS transistor is The voltage can be considered higher than that of a MOS transistor with only a P ⁺ gate electrode. Therefore, in a MOS transistor with this structure, the gate electrode is doped with the same type of impurity as the source and drain.
A reference voltage device that generates a reference voltage based on the difference between threshold voltages of MOS transistors can be constructed.

Further, according to the configuration shown in FIG. 3, since impurities are introduced into the end portion 46 of the gate electrode and at the same time into the silicon substrate near the end, the source and drain 42 and 43 are self-aligned using the gate electrode as a mask. can be formed.

〔Effect of the invention〕

The present invention utilizes a stable gate work function to form two MOS transistors with different threshold voltages, and generates a stable reference voltage based on the difference between the different threshold voltages. According to the present invention, all factors under the gate that cause variations in the manufacturing process are removed, so a fairly stable reference voltage can be obtained, and an adjustment terminal for adjusting the reference voltage can be eliminated. . Furthermore, since the impurity doped into the polysilicon of the gate electrode is the type of impurity used for diffusion of sources and drains in the normal process, it is easy to cause differences in threshold voltages in the normal process.
A reference voltage device that can be configured as a MOS transistor and is suitable for mass production can be provided.

Further, since the threshold voltage is set based on the type and amount of impurity doped into the gate electrode, it is easy to set the generated reference voltage to a desired value.

Furthermore, since the source and drain are formed using the gate electrode as a mask, it is possible to miniaturize the MOS transistor.

For example, when the present invention is used as a reference voltage for a battery voltage detection circuit for an electronic watch, it can be used without any adjustment and
Since it can be easily incorporated into an IC, it completely eliminates the hassle of using it, making a major contribution to miniaturization, process reduction, and mass production.

[Brief explanation of the drawing]

FIG. 1 is a diagram of a battery voltage detection circuit for an electronic watch using a reference voltage device. FIG. 2 is a structural diagram of a pair of transistors with different threshold voltages, which is the basic configuration of the present invention. FIG. 3 is a structural diagram showing an embodiment of a silicon gate transistor having a high threshold voltage in the reference voltage device of the present invention. 3 is a MOS transistor with a high threshold value;
4 is a normal high value MOS transistor, 34
3 shows a gate electrode doped with N ⁺ and 35 shows a gate electrode doped with P ⁺ .

Claims (1)

[Claims] 1. A first gate electrode made of polysilicon into which a first conductivity type impurity is introduced, and a first source/drain formed by introducing the first conductivity type impurity into a silicon substrate. a first conductive type impurity is introduced into the central part, and the first conductive type impurity is introduced into the central part, and the first conductive type impurity is introduced into the central part. The impurity of the first conductivity type is introduced into the second gate electrode of polysilicon into which the impurity is introduced and the end portion, and at the same time, the impurity of the first conductivity type is introduced into the silicon substrate adjacent to the end portion. The second sauce formed by
a second MOS transistor comprising a drain region, and the first MOS transistor is set based on a difference between the work function of the gate electrode and the work function of the silicon substrate.
and a second MOS transistor. A reference voltage device that generates a difference between different threshold voltages of the second MOS transistor as a reference voltage. 2. The reference voltage device according to claim 1, wherein the work functions of the first and second gate electrodes are set by the conductivity type and amount of impurities introduced into the gate electrodes. 3 The threshold voltage V _th of the first and second MOS transistors is V _th =φ _G −φ _S +2φ _F +Q _D /C ₀ +Q _SS /C ₀ φ _G : Work function of gate electrode φ _S : Silicon substrate A patent claim characterized in that the work function is set based on the formula of φ _F : Fermi level on the silicon surface Q _D : Charge amount on the silicon surface Q _SS : Interface state C ₀ : Capacitance per unit area of the gate electrode 2. The reference voltage device according to item 2. 4. The reference voltage device according to claim 3, wherein the reference voltage is in a range of 0.6 to 1.0V.