JPS5950226B2 - Complementary MIS integrated circuit device - Google Patents
Complementary MIS integrated circuit deviceInfo
- Publication number
- JPS5950226B2 JPS5950226B2 JP54045355A JP4535579A JPS5950226B2 JP S5950226 B2 JPS5950226 B2 JP S5950226B2 JP 54045355 A JP54045355 A JP 54045355A JP 4535579 A JP4535579 A JP 4535579A JP S5950226 B2 JPS5950226 B2 JP S5950226B2
- Authority
- JP
- Japan
- Prior art keywords
- well region
- resistor
- type
- oxide film
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000000295 complement effect Effects 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 9
- 230000005669 field effect Effects 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000010408 film Substances 0.000 description 33
- 239000012535 impurity Substances 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 150000001638 boron Chemical class 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0927—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising a P-well only in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は電界効果を利用した可変抵抗部を有する相補型
の金属−絶縁物−半導体（以下ＭＩＳもしくはＭＯＳと
称する）集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary metal-insulator-semiconductor (hereinafter referred to as MIS or MOS) integrated circuit device having a variable resistance section using a field effect.
時計用の相補型ＭＯＳトランジスタ回路において、その
発振回路に発振の安定を行わせる目的で入力部と出力部
との間に高抵抗を入れることが考えられている。この抵
抗を半導体集積回路（ＩＣ）のチップに組込む場合に多
結晶Ｓｉの薄膜抵抗体として使用することが考えられた
。In complementary MOS transistor circuits for watches, it has been considered to insert a high resistance between the input section and the output section in order to stabilize the oscillation of the oscillation circuit. When this resistor is incorporated into a semiconductor integrated circuit (IC) chip, it has been considered to use it as a polycrystalline Si thin film resistor.
このようなＩＣのチップ基板にバイアス電圧を加えたと
ころ前記薄膜抵抗体の抵抗値が変化すること力絆リ明し
た。上記のような可変抵抗は、一定のバイアス電圧のも
とでは抵抗の端子間電圧の広い範囲にわたつて抵抗値の
良好なリニアリティを示した、なお、従来からある半導
体ＩＣにおける負荷ＭＯＳ抵抗は可変抵抗の一つと考え
られるが、これはトランジスタの電流一電圧特性を利用
したものであり、抵抗のリニアリティをそのままに抵抗
値のみを変化させるものではないと思われる。本発明の
他の目的は、相補型ＭＩＳ集積回路装置に適する薄膜抵
抗を提供することにある。It has been revealed that when a bias voltage is applied to the chip substrate of such an IC, the resistance value of the thin film resistor changes. The variable resistor described above showed good linearity in resistance value over a wide range of voltage between the terminals of the resistor under a constant bias voltage.Note that the load MOS resistance in conventional semiconductor ICs is variable. Although it is considered to be a type of resistor, it is thought to utilize the current-voltage characteristics of a transistor, and does not change only the resistance value while maintaining the linearity of the resistor. Another object of the present invention is to provide a thin film resistor suitable for complementary MIS integrated circuit devices.
本発明の更に他の目的は、以下の説明および図面から明
らかとなるであろう。Further objects of the invention will become apparent from the following description and drawings.
本発明に従うと、多結晶Ｓｉ（シリコン）からなる抵抗
体が、１つの導電型のＭＯＳＦＥＴ（絶縁ゲート型電界
効果トランジスタ）を形成するために半導体基板主面に
形成されたウェル領域と同時に形成されたウェル領域上
に絶縁膜を介して抵抗体とすべき多結晶層が形成される
。According to the present invention, a resistor made of polycrystalline Si (silicon) is formed simultaneously with a well region formed on the main surface of a semiconductor substrate to form a MOSFET (insulated gate field effect transistor) of one conductivity type. A polycrystalline layer to be used as a resistor is formed on the well region with an insulating film interposed therebetween.
以下、本発明を実施例について具体的に説明する。Hereinafter, the present invention will be specifically described with reference to Examples.
第１図は実施例のＭＩＳ集積回路装置の断面図である。FIG. 1 is a sectional view of an MIS integrated circuit device according to an embodiment.
同図において、１はｎ型Ｓｉ基板である。上記ｎ型Ｓｉ
基板１の主面にはＰ型ソース領域１０、ｊＰ型ドレイン
領域１１が形成され、上記ソース、ドレイン領域間の基
板１主面にはゲート酸化膜７ｂを介してＰ型多結晶Ｓｉ
層８ｂからなるゲート電極が形成されている。上記ソー
ス、ドレイン領域１Ｏ、ＩＬゲート酸化膜７６及びゲー
ト電極８’）ｂによつてＰチャンネルＭＯＳＦＥＴが構
成されている。Ｓｉ基板１の主面にはまたＰ型ウェル領
域６が形成されており、このＰ型ウエル領域６にはｎ型
ソース領域１４、ｎ型ドレイン領域１５が形成されてい
る。In the figure, 1 is an n-type Si substrate. The above n-type Si
A P-type source region 10 and a jP-type drain region 11 are formed on the main surface of the substrate 1, and a P-type polycrystalline Si layer is formed on the main surface of the substrate 1 between the source and drain regions via a gate oxide film 7b.
A gate electrode made of layer 8b is formed. A P-channel MOSFET is constituted by the source and drain regions 1O, the IL gate oxide film 76, and the gate electrode 8')b. A P-type well region 6 is also formed on the main surface of the Si substrate 1, and an n-type source region 14 and an n-type drain region 15 are formed in this P-type well region 6.
上記ソース、ドレイン領域１４，１５間のウエル領域６
の表面にはゲート酸化膜７ａを介してｎ型多結晶Ｓｉ層
８ａからなるゲート電極が形成されている。上記ソース
、ドレイン領域１４，１５、ゲート酸化膜７ａ及びゲー
ト電極８ａによつてｎチヤンネルＭＯＳＦＥＴが構成さ
れる。上記Ｓｉ基板１の主面にはまたＰ型ウエル領域２
３が形成されており、このＰ型ウエル領域２３上には熱
酸化膜７Ｃを介して多結晶Ｓｉ層８Ｃ１ないし８Ｃ３が
形成されている。上記多結晶Ｓｉ層８Ｃ２は抵抗体とし
て構成され、不純物イオン打ち込み法によりＰ型不純物
が比較的低濃度に導入されたＰ型とされ、上記Ｓｉ層８
Ｃ１及び８Ｃ３は上記Ｓｉ層８Ｃ２の端子部として構成
され、Ｐ型不純物が比較的高濃度に導入されたＰ型とさ
れている。上記Ｐ型ウエル領域２３は、上記多結晶Ｓｉ
層８Ｃ１ないし８Ｃ３からなる抵抗体に対するバイアス
電極を構成する。Well region 6 between the source and drain regions 14 and 15
A gate electrode made of an n-type polycrystalline Si layer 8a is formed on the surface of the gate oxide film 7a via a gate oxide film 7a. The source and drain regions 14 and 15, the gate oxide film 7a, and the gate electrode 8a constitute an n-channel MOSFET. The main surface of the Si substrate 1 also has a P-type well region 2.
3 is formed, and polycrystalline Si layers 8C1 to 8C3 are formed on this P-type well region 23 with a thermal oxide film 7C interposed therebetween. The polycrystalline Si layer 8C2 is configured as a resistor, and is of P type into which P type impurities are introduced at a relatively low concentration by an impurity ion implantation method.
C1 and 8C3 are configured as terminal portions of the Si layer 8C2, and are of P type into which P type impurities are introduced at a relatively high concentration. The P-type well region 23 is made of the polycrystalline Si.
A bias electrode for the resistor consisting of layers 8C1 to 8C3 is configured.
なお、第１図において、２５はＣＶＤ
（ＣｈｅｍｉｃａｌＶａｐＯｒＤｅｐＯｓｉｔｉＯｎ）
法等によつて被着されたＳｉＯ２からなる絶縁膜であり
、１６ないし２１はアルミニウムからなる電極である。In addition, in FIG. 1, 25 is CVD (ChemicalVapOrDepOsitiOn)
It is an insulating film made of SiO2 deposited by a method or the like, and 16 to 21 are electrodes made of aluminum.
第２図は上記ＭＯＳ−１Ｃ装置における可変抵抗体部の
動作態様を説明するための図面である。第１図第２図に
示したような可変抵抗体において、絶縁膜７。を介して
バイアス電極としてのＰ型ウエル領域２３から多結晶Ｓ
ｉ抵抗体８。２に電圧Ｖ１による電界が加えられる。FIG. 2 is a diagram for explaining the operation mode of the variable resistor section in the MOS-1C device. In the variable resistor as shown in FIG. 1 and FIG. 2, the insulating film 7. from the P-type well region 23 as a bias electrode through the polycrystalline S
An electric field due to the voltage V1 is applied to the i-resistor 8.2.
抵抗体８。２の導電型がＰ型であるので、ここに（＋）
の電界をかけると絶縁膜７。Since the conductivity type of resistor 8.2 is P type, here (+)
When an electric field is applied, the insulating film 7.
側から抵抗体に空乏層が拡がリキヤリア数が減少してそ
の抵抗値が増大する。逆に（−）の電界をかけるとキヤ
リアが増加し抵抗値が減少することになる。第３図はバ
イアス電圧Ｖ／，０Ｖ，Ｖ１７によつて変化する上記抵
抗体のＩ。A depletion layer spreads from the side to the resistor, the carrier number decreases, and its resistance value increases. Conversely, when a (-) electric field is applied, the carrier increases and the resistance value decreases. FIG. 3 shows the I of the resistor that changes depending on the bias voltages V/, 0V, and V17.
−ＶＯ特性の一例を示している。上記構造の相補型ＭＩ
Ｓ集積回路装置は次のようにして製造することができる
。- An example of VO characteristics is shown. Complementary MI of the above structure
The S integrated circuit device can be manufactured as follows.
以下、製造工程にそつた断面を示した第４図ａないしｂ
を使用して説明する。（ａ） ｎ型Ｓｉ基板（ウエハ）
１を用意し、表面に熱酸化膜（ＳｌＯ２）２を１０００
〜２０００人の厚さに覆つた状態で上記酸化膜の一部を
ホトレジスト膜３でマスクし、酸化膜を通してＢ（ボロ
ン）イオンを打込み（Ｂ：１Ｘ１０１３／ＣＩｎ２、１
００ＫｅＶ）、上記ホトレジスト膜３で覆われていない
酸化膜下のＳｉ基板の一部にＢ打込層４，４″をつくる
。Below, Figure 4 a to b shows a cross section along the manufacturing process.
Explain using. (a) N-type Si substrate (wafer)
1 is prepared, and a thermal oxide film (SlO2) 2 is placed on the surface of 1000
A part of the oxide film was masked with a photoresist film 3 while covering the film to a thickness of ~2,000 mm, and B (boron) ions were implanted through the oxide film (B: 1×1013/CIn2, 1
00 KeV), B implantation layers 4, 4'' are formed on a part of the Si substrate under the oxide film that is not covered with the photoresist film 3.
））上記ホトレジスト膜３をマスクとして、エツチング
により打込み層４上の酸化膜を除去する。)) Using the photoresist film 3 as a mask, the oxide film on the implantation layer 4 is removed by etching.
これによつて酸化膜２に（ｄ）の工程のマスク位置合わ
せ段差をつくる。ニ）前記ホトレジストマスク３を除去
し、新たに熱酸化により酸化膜５（厚さ１２００人）を
形成し、同時にボロンを拡散してＰ型ウエル領域６及び
２３（深さ５〜６μ）を形成する。As a result, a step for mask positioning in the step (d) is created in the oxide film 2. D) Remove the photoresist mask 3, form a new oxide film 5 (thickness: 1200 μm) by thermal oxidation, and simultaneously diffuse boron to form P-type well regions 6 and 23 (depth: 5 to 6 μm). do.
１）酸化膜５のホトエツチングを行い、基板およびウエ
ルの各アタテイブ領域１ａ，６ｂ及び２３ａを露出する
。1) Photoetch the oxide film 5 to expose the attenuated regions 1a, 6b and 23a of the substrate and well.
→ 熱酸化により上記露出表面にゲート酸化膜７ａ，７
ｂ及び７Ｃ（厚さ１２５０人）を形成し、この上にモノ
シラン（ＳｉＨ４）の熱分解による多結晶Ｓｉ層（厚さ
：５０００人）を形成し、次いで上記多結晶Ｓｉ層をホ
トエツチングし、ゲートおよび可変抵抗部とする部分８
ａ，８ｂ及び８Ｃを残して不要部を除去する。→ Gate oxide films 7a, 7 are formed on the exposed surface by thermal oxidation.
A polycrystalline Si layer (thickness: 5000 layers) is formed on this by thermal decomposition of monosilane (SiH4), and then the polycrystalline Si layer is photoetched to form a gate. and the part 8 which is a variable resistance part
Remove unnecessary parts leaving a, 8b and 8C.
前記可変抵抗部８Ｃに所望の抵抗値が得られるように抵
抗のイオン打込みを行なう。Resistor ions are implanted so that a desired resistance value is obtained in the variable resistance section 8C.
例えばボロンイオンを５０ＫｅＶのエネルギーでアクセ
プタ不純物濃度１０１４〜１０１５／ｄ打込む。このボ
ロンイオン打込みは、マスクを使用せずに半導体基板全
面に行なうことができ、また可変抵抗部８Ｃのみを露出
するようなレジスト等のマスクを使用して行うこともで
きる。「）多結晶シリコン８ａ，８ｂ及び゛８Ｃをマス
タとして、ｎチヤネルＭＯＳＦＥＴ形成用のソース及び
ドレイン領域部分の酸化膜７ａ．ＰチヤネルＭＯＳＦＥ
Ｔ形成用のソース及びドレイン領域部分の酸化膜７ｂ及
びｐ型ウエル領域２３上の酸化膜７Ｃをフツ酸と硝酸の
混合エツチ液でエツチング除去する。For example, boron ions are implanted at an acceptor impurity concentration of 1014 to 1015/d at an energy of 50 KeV. This boron ion implantation can be performed over the entire surface of the semiconductor substrate without using a mask, or can be performed using a mask such as a resist that exposes only the variable resistance section 8C. ``) Using polycrystalline silicon 8a, 8b and ``8C as a master, oxide film 7a of source and drain region portions for forming n-channel MOSFET.P channel MOSFET
The oxide film 7b in the source and drain regions for T formation and the oxide film 7C on the p-type well region 23 are removed by etching with a mixed etchant of hydrofluoric acid and nitric acid.
ｚ）半導体基板表面にＣＶＤ法により （ＶａｐＯｎＤ
ｅｐＯｓｉｔｉＯｎ）ＳｉＯ２９を被着させ、次にｐチ
ヤネルＭＯＳＦＥＴ形成部、すなわち多結晶シリコン８
ｂをゲート電極とする部分および抵抗の両端すなわち抵
抗の電極引き出し部分のＣＶＤＳｉＯ２９を選択的にエ
ツチングを行なう。z) On the surface of the semiconductor substrate by CVD method (VapOnD
epOsitiOn) SiO29 is deposited and then the p-channel MOSFET formation area, ie polycrystalline silicon 8
The CVDSiO 29 is selectively etched at the portion where b is used as the gate electrode and at both ends of the resistor, that is, at the electrode extension portion of the resistor.
次にボロンナイトライドを不純物源とする拡散によつて
ｐチヤネルＭＯＳ形成部のソース領域１０、ドレイン領
域ＩＬＰ型ウエル領域２３の電極取出し部２４、及び可
変抵抗部８Ｃの両端部８ｃ，，８ｃ，をｐ型の高濃度不
純物領域とする。Next, by diffusion using boron nitride as an impurity source, the source region 10 of the p-channel MOS forming part, the electrode lead-out part 24 of the drain region ILP type well region 23, and both ends 8c, 8c, of the variable resistance part 8C, is a p-type high concentration impurity region.
（ｈ）上記ＣＶＤＳｉＯ。(h) The above CVDSiO.
９をエツチング除去し、第２のＣＶＤＳｉＯ。9 was etched away, and the second CVDSiO was removed.
ｌ３をつけ、ｎチヤネルＭＯＳＦＥＴ形成部上のＣＶＤ
ＳｉＯ。ｌ３を選択エツチする。次にリン拡散によりｎ
チヤネルＭＯＳＦＥＴ形成部のソース領域１４及びドレ
イン領域１５形成し、同時に多結晶シリコン８ａをＮｆ
型にする。しかる後、第１図のように、上記ＣＶＤＳｉ
Ｏ。ｌ３を除去し、さらに全面に新らたなＣＶＤＳｉＯ
。等の絶縁膜２５を形成し、上記絶縁膜２５をコンタク
トエツチし、次いで真空Ａｌ（アルミニウム）蒸着法及
びホトエツチ法により、ソース、ドレイン領域および抵
抗体のコンタクト部に接続する電極１６，１７，１８，
１９，２０，２１を設けると共に、電極取り出し部２４
に電極２２を設けることにより相補型ＭＯＳ− ＩＣ装
置を完成する。上記実施例によると、以下の理由でその
目的を達成することができる。１ 相補型ＭＯＳＦＥＴ
を形成する半導体基板上にこの基板とは絶縁された状態
の抵抗体を構成することができる。Attach l3 and CVD on the n-channel MOSFET forming part.
SiO. Select l3. Next, due to phosphorus diffusion, n
A source region 14 and a drain region 15 of a channel MOSFET formation part are formed, and at the same time polycrystalline silicon 8a is coated with Nf.
Make it into a mold. After that, as shown in FIG.
O. Removed l3 and added new CVDSiO to the entire surface.
. The insulating film 25 is contact-etched, and then the electrodes 16, 17, 18 connected to the source and drain regions and the contact portions of the resistor are formed by vacuum Al (aluminum) evaporation and photo-etching. ，
19, 20, 21, and an electrode take-out portion 24.
A complementary MOS-IC device is completed by providing an electrode 22 at the top. According to the above embodiment, the purpose can be achieved for the following reasons. 1 Complementary MOSFET
A resistor can be constructed on a semiconductor substrate on which a resistor is insulated from the substrate.
２ｎチャネルＭＯＳＦＥＴのためのウエル領域６と同時
に形成されたウエル領域２３を用いることができ、さら
にそのウエル領域２３から抵抗体８ｃ。The well region 23 formed at the same time as the well region 6 for the 2n channel MOSFET can be used, and the resistor 8c is further formed from the well region 23.
に適当なバイアス電圧を与えることにより上記抵抗体８
ｃ。の抵抗値を所定の値と成すことができる。３８ｃ。By applying an appropriate bias voltage to the resistor 8
c. The resistance value can be set to a predetermined value. 38c.
を形成する部分の絶縁膜７ｃをウエル領域２３表面を酸
化した酸化膜とすることによつてその厚さ制御が容易と
なる。酸化膜７ｃの厚さが比較的正確になるので、領域
２３から抵抗体８ｃ。に加わるバイアス電圧を装置の製
造バラツキにかかわらずほぼ一定にすることができる。
４ 不純物の導入を比較的高精度にできるイオン打ち込
み法によつて行なつた構成であるので、抵抗体８ｃ。By forming the portion of the insulating film 7c in which the well region 23 is formed by using an oxide film obtained by oxidizing the surface of the well region 23, its thickness can be easily controlled. Since the thickness of the oxide film 7c is relatively accurate, the resistor 8c is removed from the region 23. The bias voltage applied to the device can be kept almost constant regardless of manufacturing variations in the device.
4. The resistor 8c has a structure in which impurity introduction is performed using an ion implantation method that allows relatively high precision.
の抵抗値を比較的正確に設定できる。The resistance value can be set relatively accurately.
第１図は本発明の一実施例のＩＣの断面図、第２図は上
記一実施例のＩＣの要部断面図、第３図はＶ１をパラメ
ータにした抵抗体のＩＤ−ＶＤ特性曲線図、第４図ａ乃
至ｈは上記第１図のＩＣの一部製造工程における断面図
である。
１ ・・・・・・ ｎ型Ｓｉ基板、５ ・・・・・・熱
酸化膜、６，２３・・・・・・ Ｐ型ウエル領域、７ａ
，７ｂ・・・・・・ゲート酸化膜、７ｃ・・・・・・可
変抵抗部の熱酸化膜、８ ・・・・・・多結晶Ｓｉ、８
ａ，８ｂ・・・・・・多結晶Ｓｉゲート、８ｃ。Fig. 1 is a cross-sectional view of an IC according to an embodiment of the present invention, Fig. 2 is a cross-sectional view of a main part of an IC according to the above-mentioned embodiment, and Fig. 3 is an ID-VD characteristic curve diagram of a resistor with V1 as a parameter. , FIGS. 4a to 4h are cross-sectional views of the IC shown in FIG. 1 during a partial manufacturing process. 1... N-type Si substrate, 5... Thermal oxide film, 6, 23... P-type well region, 7a
, 7b... Gate oxide film, 7c... Thermal oxide film of variable resistance section, 8... Polycrystalline Si, 8
a, 8b... Polycrystalline Si gate, 8c.
Claims (1)
電型の絶縁ゲート電界効果トランジスタと、上記半導体
基板の主面に形成された第２導電型ウェル領域に形成さ
れた第１導電型の絶縁ゲート電界効果トランジスタと、
上記第２導電型ウェル領域と同時に形成され所定電位が
与えられるウェル領域上に絶縁膜を介して形成された多
結晶シリコン層とを含み、上記ウェル領域上の多結晶シ
リコン層には、上記絶縁ゲート電界効果トランジスタの
ソースもしくはドレイン領域の形成と同時に形成された
高不純物濃度の端部領域が形成されてなり、上記ウェル
領域上の多結晶シリコン層が上記ウェル領域に与えられ
る所定電位により制御される抵抗素子とされてなること
を特徴とする相補型ＭＩＳ集積回路装置。1 an insulated gate field effect transistor of a second conductivity type formed on a main surface of a semiconductor substrate of a first conductivity type; and a first conductivity type formed in a well region of a second conductivity type formed on a main surface of the semiconductor substrate. an insulated gate field effect transistor of the type;
a polycrystalline silicon layer formed via an insulating film over the well region that is formed simultaneously with the second conductivity type well region and to which a predetermined potential is applied; A highly doped end region is formed simultaneously with the formation of the source or drain region of the gate field effect transistor, and the polycrystalline silicon layer on the well region is controlled by a predetermined potential applied to the well region. 1. A complementary MIS integrated circuit device, characterized in that it is a resistive element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54045355A JPS5950226B2 (en) | 1979-04-16 | 1979-04-16 | Complementary MIS integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54045355A JPS5950226B2 (en) | 1979-04-16 | 1979-04-16 | Complementary MIS integrated circuit device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11582373A Division JPS5321992B2 (en) | 1973-10-17 | 1973-10-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS551179A JPS551179A (en) | 1980-01-07 |
| JPS5950226B2 true JPS5950226B2 (en) | 1984-12-07 |
Family
ID=12716966
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54045355A Expired JPS5950226B2 (en) | 1979-04-16 | 1979-04-16 | Complementary MIS integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5950226B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH051228Y2 (en) * | 1985-06-13 | 1993-01-13 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5878740A (en) * | 1981-11-02 | 1983-05-12 | Sumitomo Rubber Ind Ltd | Method and apparatus for manufacturing tire |
-
1979
- 1979-04-16 JP JP54045355A patent/JPS5950226B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH051228Y2 (en) * | 1985-06-13 | 1993-01-13 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS551179A (en) | 1980-01-07 |
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