JPH02230305A - Reference voltage source - Google Patents
Reference voltage sourceInfo
- Publication number
- JPH02230305A JPH02230305A JP1154019A JP15401989A JPH02230305A JP H02230305 A JPH02230305 A JP H02230305A JP 1154019 A JP1154019 A JP 1154019A JP 15401989 A JP15401989 A JP 15401989A JP H02230305 A JPH02230305 A JP H02230305A
- Authority
- JP
- Japan
- Prior art keywords
- reference voltage
- difference
- gate
- mos transistor
- threshold voltages
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000463 material Substances 0.000 claims abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052710 silicon Inorganic materials 0.000 abstract description 11
- 239000010703 silicon Substances 0.000 abstract description 11
- 239000000758 substrate Substances 0.000 abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 229920005591 polysilicon Polymers 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 4
- 230000001939 inductive effect Effects 0.000 abstract 3
- 238000000034 method Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 235000014548 Rubus moluccanus Nutrition 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Control Of Electrical Variables (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体集積回路(IC)に内蔵可能な基準電圧
源に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reference voltage source that can be built into a semiconductor integrated circuit (IC).
従来IC内基準電圧源はツエナーダイオードにより構成
される例が主であった.この場合ツエナー電圧のバラッ
キは多く、温度特性が悪いので必ず外は調整端子、補償
素子を必要としていた.又特開昭53−47953号で
はチャネルドーブによるシキイ値の差を基準電圧源とす
る実施例が記載されているが、この方法はチャネルに対
するド一ズ量と、ゲート膜厚のバラツキにより、電圧源
のバラツキ量は大きく、完全に無調整で所望の電圧を得
ることはむずかしく、何らかの調整機能を外部に必要と
し、使う上で非常に煩わしかった。Conventionally, the reference voltage source within an IC has mainly been constructed from a Zener diode. In this case, there was a lot of variation in the Zener voltage, and the temperature characteristics were poor, so an adjustment terminal and compensation element were always required on the outside. Furthermore, Japanese Patent Laid-Open No. 53-47953 describes an embodiment in which the difference in threshold values due to channel dove is used as a reference voltage source, but this method is difficult to control the voltage due to variations in the dosing amount for the channel and the gate film thickness. The amount of variation in the power source is large, and it is difficult to obtain the desired voltage completely without adjustment, and some kind of adjustment function is required externally, which is extremely troublesome to use.
本発明の目的はこのような欠点を除去するものであり、
物質により一定の仕事関数の差を基準電圧として、製造
プロセスによるバラッキを極少とする方式を提供するこ
とにある。The object of the present invention is to eliminate such drawbacks,
The object of the present invention is to provide a method that minimizes variations due to the manufacturing process by using a constant work function difference depending on the material as a reference voltage.
第1図は本発明の基準電圧源を電子時計用の電池電圧検
出回路に応用したー実施例である。トランジスタ1,2
,3.4により構成される基準電圧源は先の特開昭53
−47953号に詳しく述べられておりトランジスタ3
とトランジスタ4はそのシキイ値が異なる゛ペアーとし
て、このシキイ値の差がA点に出力される.トランジス
タ5はクロックφによりスイッチングされ、サンプリン
グ動作を行なう.抵抗6と抵抗7は電源電圧を分割して
、B点の電位が所望する電源電圧で基準電圧出力である
A点の電位と同じになるよう設計される.従ってコンバ
レータ11の出力は初期の電源電圧においてはB点の電
位がA点の電位より高いのでレベル“1”となる。又電
源電圧が低下してくるとA点の電位はB点より高くなり
、コンパレータl1の出力はレベル“0″となる.この
コンパレータの出力をラッチl2でクロックφにより記
憶している.
この例において問題となるのは、基準電圧となるトラン
ジスタ3とトランジスタ4のシキイ値の作製方法である
。本発明ではシキイ値の差は、ゲート電極の材料とシリ
コン基板の仕事関数差により得るものである.通常トラ
ンジスタのシキイ値電圧vthは次の式により決定する
。FIG. 1 shows an embodiment in which the reference voltage source of the present invention is applied to a battery voltage detection circuit for an electronic watch. Transistor 1, 2
, 3.4 is the reference voltage source constructed by
Transistor 3 as detailed in No. 47953.
and transistor 4 are a pair with different threshold values, and the difference in threshold values is output to point A. Transistor 5 is switched by clock φ and performs sampling operation. Resistor 6 and resistor 7 are designed to divide the power supply voltage so that the potential at point B becomes the same as the potential at point A, which is the desired power supply voltage and the reference voltage output. Therefore, the output of the converter 11 becomes level "1" because the potential at point B is higher than the potential at point A at the initial power supply voltage. Also, as the power supply voltage decreases, the potential at point A becomes higher than point B, and the output of comparator l1 becomes level "0". The output of this comparator is stored in latch l2 using clock φ. In this example, the problem is how to create the threshold values of transistors 3 and 4, which serve as reference voltages. In the present invention, the difference in threshold value is obtained by the difference in work function between the material of the gate electrode and the silicon substrate. Normally, the threshold voltage vth of a transistor is determined by the following equation.
vth=φG−φ3+2φF +QD/CO+031/
Co 1ここでφ。はゲートの仕事関数、φ3は基
板の仕事関数、φ『はシリコンの表面のフェルミレベル
、Q.はシリコン表面の電荷量、Qssは界面準位、C
0はゲートの単位面積当りの容量を表わす.このφ。は
ゲートの材料により一義的に決定される.又シリコン側
のφS.φ,も不純物分布が一定ならばやはり一義的に
定まる。vth=φG−φ3+2φF +QD/CO+031/
Co 1 where φ. is the work function of the gate, φ3 is the work function of the substrate, φ′ is the Fermi level of the silicon surface, Q. is the amount of charge on the silicon surface, Qss is the interface state, C
0 represents the capacitance per unit area of the gate. This φ. is uniquely determined by the gate material. Also, φS on the silicon side. φ is also uniquely determined if the impurity distribution is constant.
一例としてシリコンゲート構造とすると、ゲートのドー
ピング量とタイプによりφ。は任意に決定しうる.第2
図はシリコンゲート構造のNチャネルトランジスタを示
す.N一基板26中にP−ウエル25が形成されている
,21〜24はソース・ドレインとなる拡散層である.
27はSin.の絶縁層であり28〜31は電極用のA
lである。As an example, in the case of a silicon gate structure, φ depends on the doping amount and type of the gate. can be determined arbitrarily. Second
The figure shows an N-channel transistor with a silicon gate structure. A P-well 25 is formed in an N-substrate 26, and 21 to 24 are diffusion layers that become sources and drains.
27 is Sin. 28 to 31 are A for electrodes.
It is l.
ゲート電極は34.35でありこの下はゲート酸化膜を
介して導電チャネルを形成する.通常の工程ではトラン
ジスタ32の方のゲート電極34にはソース・ドレイン
と同じN0がドープされている.一方トランジスタ33
のゲート電極35にはP0をドープする.この時ゲート
電極34のφGは真性フエルミを基準とすると+0.3
〜+〇.5V,ゲート電極35のφ6は−0.3〜−〇
.5■となる.
従ってφ3,2φF , Qo/Co , Qss/C
oが工程間でのバラツキが大きくても、この両方のトラ
ンジスタには共通であるので、シキイ値の差をとると、
ゲートのドーピング量に依存して0.6〜1.Ov程度
変化する基準電圧が発生できる.通常ドーピング量はか
なり安定にコントロール可能であり、又多少バラツイて
も±10mV以内に入る.
第3図は通常のシリコンゲート工程でのゲートにソース
・ドレインと逆タイプの拡散をする構造例である。N一
基板41にソース・ドレインとなるP゜拡散層42.4
3が形成される。この時ゲート電極の一部46にもP゛
が入る。この後酸化膜44をマスクとしてN゛をドープ
する.これはPチャネルトランジスタの例であるが、N
チャネルも全《同様に形成される.ゲート電極45の下
はシキイ値が低く、一部46の下はシキイ値が低いがト
ランジスタのシキイ値は高い方と見なせる。The gate electrode is 34.35 mm below which a conductive channel is formed via a gate oxide film. In a normal process, the gate electrode 34 of the transistor 32 is doped with N0, which is the same as the source and drain. On the other hand, transistor 33
The gate electrode 35 of is doped with P0. At this time, φG of the gate electrode 34 is +0.3 based on the intrinsic Fermi
〜+〇. 5V, φ6 of the gate electrode 35 is -0.3 to -0. 5■. Therefore, φ3, 2φF, Qo/Co, Qss/C
Even if there is a large variation in o between processes, it is common to both transistors, so if we take the difference between the threshold values, we get:
0.6-1. depending on the gate doping amount. A reference voltage that changes by approximately Ov can be generated. Normally, the doping amount can be controlled fairly stably, and even if there is some variation, it is within ±10 mV. FIG. 3 shows an example of a structure in which the gate is diffused in the opposite type to the source and drain in a normal silicon gate process. P° diffusion layer 42.4 which becomes the source/drain on the N-substrate 41
3 is formed. At this time, P' also enters a part 46 of the gate electrode. After this, N is doped using the oxide film 44 as a mask. This is an example of a P-channel transistor, but N
Channels are also formed in the same way. Although the shikiness value is low under the gate electrode 45 and the shikishi value is low under the part 46, it can be considered that the shikishi value of the transistor is high.
第4図は他の構造例であり、(a),[有]). (C
)は工程順を示す.(a)まず基仮53にゲート酸化膜
52をつけて、更にポリシリコン51をデポジットする
.この時ポリシリコンにはN゛を必要となる領域58の
みに濃くドープする。[有])その後ポリシリコンをエ
ッチングしゲート54を形成する。(C)その後ゲート
膜を必要外の部分を除去して55を形成し、全体にP+
をドーブしてソニス・ドレイン56.57を形成する。FIG. 4 shows another example of the structure, (a). (C
) indicates the process order. (a) First, a gate oxide film 52 is applied to the base 53, and then polysilicon 51 is deposited. At this time, the polysilicon is heavily doped with N only in the necessary region 58. After that, the polysilicon is etched to form a gate 54. (C) After that, unnecessary parts of the gate film are removed to form 55, and the whole is P+
dove to form a sonis drain 56.57.
ゲート54はあらかじめN〜となっているのでP+がド
ープされても変化しない。Since the gate 54 is set to N~ in advance, it does not change even if it is doped with P+.
本発明の他の方法として、/lゲートとMoゲートの如
《金属ゲート同志の仕事関数差を利用してもよいし、又
シリコンゲートと金属ゲートの仕事関数差としてもよい
.
本発明は安定なゲートの仕事関数を利用して基準電圧を
作成する方法であり、工程でのバラツキの原因となるゲ
ート下の要因はすべ゛て取り除かれるので、かなり安定
な基準電圧が得られる.本発明は例えば電子時計用の電
池電圧検出回路用の基準電圧として用いると、無調整で
かつ、■C内に簡単に内蔵できる点で、使用する上での
煩わしさを完全に除去し、小型化、工程削減、量産化に
対する寄与は大きい.As another method of the present invention, the work function difference between metal gates such as a /l gate and a Mo gate may be used, or the work function difference between a silicon gate and a metal gate may be used. The present invention is a method of creating a reference voltage using a stable gate work function, and since all factors under the gate that cause variations in the process are removed, a fairly stable reference voltage can be obtained. .. For example, when the present invention is used as a reference voltage for a battery voltage detection circuit for an electronic watch, it does not require adjustment and can be easily built into the C. It has a large contribution to the development of technology, process reduction, and mass production.
第1図は本発明による基準電圧源を利用した電子時計用
電池電圧検出回路を示す図.
第2図は本発明のためのシキイ値の異なるトランジスタ
ベアの構造例を示す図。
第3図はシリコンゲートトランジスタにおける高シキイ
値構造例を示す図。
第4図は高シキイ値トランジスタの製造工程例を示す図
.
3・・・高シキイ値
4・・・通常のシキイ値のトランジスタ34・・・N+
35・・・P0がドープされたゲート
− V3S
第l図
出願人 セイコーエプソン株式会社
代理人 弁理士 鈴木喜三郎他1名
第2図
手続補正書
(自発)FIG. 1 is a diagram showing a battery voltage detection circuit for an electronic watch using a reference voltage source according to the present invention. FIG. 2 is a diagram showing an example of the structure of a transistor bear with different threshold values for the present invention. FIG. 3 is a diagram showing an example of a high threshold value structure in a silicon gate transistor. Figure 4 is a diagram showing an example of the manufacturing process of a high threshold transistor. 3...High resistance value 4...Normal resistance value transistor 34...N+ 35...Gate doped with P0-V3S Figure 1 Applicant Seiko Epson Corporation Agent Patent attorney Kisaburo Suzuki et al. 1 person figure 2 procedural amendment (voluntary)
Claims (1)
を用いた2つのトランジスタのシキイ値の差を用いるこ
とを特徴とする基準電圧源。(1) A reference voltage source characterized by using the difference in threshold values of two transistors using gate materials whose gate electrodes have different work functions.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1154019A JPH02230305A (en) | 1989-06-16 | 1989-06-16 | Reference voltage source |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1154019A JPH02230305A (en) | 1989-06-16 | 1989-06-16 | Reference voltage source |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11617078A Division JPS5541595A (en) | 1978-09-20 | 1978-09-20 | Reference voltage source |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02230305A true JPH02230305A (en) | 1990-09-12 |
JPH0421214B2 JPH0421214B2 (en) | 1992-04-09 |
Family
ID=15575132
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1154019A Granted JPH02230305A (en) | 1989-06-16 | 1989-06-16 | Reference voltage source |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02230305A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0554673A (en) * | 1991-08-26 | 1993-03-05 | Nec Corp | Reference potential generating circuit |
US6222395B1 (en) | 1999-01-04 | 2001-04-24 | International Business Machines Corporation | Single-ended semiconductor receiver with built in threshold voltage difference |
-
1989
- 1989-06-16 JP JP1154019A patent/JPH02230305A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0554673A (en) * | 1991-08-26 | 1993-03-05 | Nec Corp | Reference potential generating circuit |
US6222395B1 (en) | 1999-01-04 | 2001-04-24 | International Business Machines Corporation | Single-ended semiconductor receiver with built in threshold voltage difference |
Also Published As
Publication number | Publication date |
---|---|
JPH0421214B2 (en) | 1992-04-09 |
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