JP2005109364A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which comprises a reference voltage generation circuit for generating a reference voltage on the basis of a threshold voltage difference between two or more MOS transistors and a differential amplification circuit for receiving the reference voltage from the reference voltage generation, and which eliminates the temperature dependency of the differential amplification circuit on its output voltage. <P>SOLUTION: The semiconductor device comprises the reference voltage generation circuit for generating the reference voltage at a reference voltage terminal Vref on the basis of the threshold voltage difference between MOS transistors M1, M2 having different threshold voltages due to different conductivities of gate electrodes 27, 29 of the same channel concentration formed in a P type well 3, and a differential amplification circuit 31 having an offset voltage for receiving the reference voltage from the reference voltage generation circuit. The offset voltage of the differential amplification circuit 31 is set so that the temperature coefficient of the output voltage based on the offset voltage cancels the temperature coefficient of the reference voltage issued from the reference voltage generation circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a reference voltage generating circuit that generates a reference voltage based on a threshold voltage difference between two or more MOS transistors having different threshold voltages, and a reference voltage from the reference voltage generating circuit is The present invention relates to a semiconductor device including an input differential amplifier circuit.

  There is known a reference voltage generating circuit composed of a depletion type MOS transistor and an enhancement type MOS (Metal Oxide Semiconductors) transistor having different threshold voltages (see, for example, Patent Document 1). In such a reference voltage generating circuit, as shown in FIG. 8, the gate and the source of a depletion type NMOS (N channel type MOS) transistor M9 are connected and their constant current characteristics are utilized. An enhancement type NMOS transistor M10 having a gate and a drain connected is connected in series so as to operate with a constant current of the transistor M9, and a voltage generated in the transistor M10 is taken out as a reference voltage (Vref). As the reference voltage, a threshold voltage difference between the transistors M9 and M10 is output.

In Patent Document 1, as a method of changing the threshold voltage between the transistor M9 and the transistor M10, a method of changing the impurity concentration of the substrate or the impurity concentration of the channel is given as an example. As the method, it has been proposed to change the ion implantation amount at the time of channel dope implantation.
However, the method of controlling the threshold voltage by changing the ion implantation amount has a problem that the channel concentration varies, and controllability of the threshold voltage has been demanded.

  Therefore, the inventors of the present invention have the same substrate concentration and channel concentration and change the conductivity of the gate electrode. For example, a depletion type NMOS transistor having an N-type gate electrode and an enhancement type NMOS transistor having a P-type gate electrode are provided. As a result, a configuration in which the metal / semiconductor work function difference (hereinafter also simply referred to as a work function difference) is used as a reference voltage was studied. As a result, it was confirmed that the change in the initial reference voltage was small even when the channel concentration was changed.

In addition, as a reference voltage generation circuit having another configuration, each of the first and second transistors connected to each other by being grounded and driven by two constant currents having a constant current ratio and diode-connected, and the first or second transistor Some have means for amplifying and adding the difference voltage between the two output voltages of the first transistor and the second transistor to the output voltage from the transistor.
In such a reference voltage circuit, in order to output a reference voltage having no temperature dependency, the means for amplifying and adding is composed of two OTAs (operational transconductance amplifiers) and a current mirror circuit. The second OTA receives the differential voltage, the second OTA has the output voltage from the first or second transistor applied to the negative phase input terminal, the positive phase input terminal is connected to the output terminal, and the output of the first OTA. Some are driven by a current proportional to the current and output the output terminal voltage of the second OTA (for example, see Patent Document 2).
JP-A-56-108258 JP 2002-270768 A

  In a reference voltage generation circuit using an NMOS depletion type transistor having an N-type gate electrode and an NMOS enhancement type transistor having a P-type gate electrode and changing the conductivity of the gate electrode to set the work function difference as a reference voltage, The amount of change in the threshold with respect to the temperature change was different between the gate electrode and the P-type gate electrode, and the output reference voltage showed a stable negative temperature coefficient. For example, in a constant voltage generation circuit or a voltage detection circuit, when a reference voltage is input to a differential amplifier circuit, the reference voltage is compared with a change in temperature, and an operation is performed by feedback between an output transistor and a resistor, the output voltage becomes a temperature. It becomes a problem to change. Therefore, a configuration in which the work function difference is used as a reference voltage by changing the conductivity of the gate electrode cannot be used.

  Further, the reference voltage generation circuit described in Patent Document 2 has a problem that the circuit configuration becomes complicated because the two OTAs and the current mirror circuit are provided as means for amplifying and adding.

  The present invention relates to a reference voltage generating circuit that generates a reference voltage based on a threshold voltage difference between two or more MOS transistors having different threshold voltages, and a differential amplifier that receives the reference voltage from the reference voltage generating circuit. An object of the present invention is to eliminate the temperature dependence of the output voltage of a differential amplifier circuit without complicating the circuit configuration of a reference voltage generation circuit in a semiconductor device including a circuit.

  The present invention generates a reference voltage based on a threshold voltage difference of two or more MOS transistors formed in the same well and having different channel voltages due to different conductivity of the gate electrode at the same channel concentration. And a differential amplifier circuit having an offset voltage to which the reference voltage from the reference voltage generator circuit is input, the differential amplifier circuit offset voltage being a temperature coefficient of an output voltage based on the offset voltage And the reference voltage output from the reference voltage generation circuit are set to cancel each other out.

In the semiconductor device of the present invention, an example is given in which the offset voltage of the differential amplifier circuit is set when the gate size ratio of the differential pair and / or the gate size ratio of the active load is not 1: 1. Can do.
The reference voltage generation circuit includes a depletion type NMOS transistor having an N-type gate electrode and an enhancement type NMOS transistor having a P-type gate electrode connected in series, and a reference output from the reference voltage generation circuit. As an example, the voltage has a negative temperature characteristic, and the output voltage of the differential amplifier circuit has a positive temperature coefficient.

  As an example of a circuit to which the present invention is applied, a reference voltage from a reference voltage generation circuit is input to one input terminal of an inverting input terminal and a non-inverting input terminal of a differential amplifier circuit, and an output voltage of the differential amplifier circuit Is input to the gate of the output transistor, and an output voltage output from the output transistor can be cited as a voltage stabilizing circuit input to the other input terminal of the differential amplifier circuit. As the reference voltage generating circuit and the differential amplifier circuit, the reference voltage generating circuit and the differential amplifier circuit of the present invention are provided.

  As another example of a circuit to which the present invention is applied, a reference voltage from a reference voltage generation circuit is input to one of the inverting input terminal and the non-inverting input terminal of the differential amplifier circuit, and The output voltage is input to the gate of the output transistor, the output voltage output from the output transistor is divided by a plurality of resistors, and the voltage divided by the resistors is input to the other input terminal of the differential amplifier circuit. The voltage generator circuit includes the reference voltage generator circuit and the differential amplifier circuit of the present invention as the reference voltage generator circuit and the differential amplifier circuit.

  As still another example of the circuit to which the present invention is applied, the output voltage of the reference voltage generation circuit is input to one of the inverting input terminal and the non-inverting input terminal of the differential amplifier circuit, and leads to the voltage to be detected. A voltage detection circuit in which a terminal is input to the other input terminal of the differential amplifier circuit can be cited. In the voltage generation circuit, the reference voltage of the present invention is used as the reference voltage generation circuit and the differential amplifier circuit. A generation circuit and a differential amplifier circuit are provided.

  In the present invention, by making the conductivity of the gate electrode of the MOS transistor constituting the reference voltage generating circuit different, the difference in the metal / semiconductor work function is made different to make the threshold voltage different. The reference voltage output from such a reference voltage generation circuit is stable without depending on the channel concentration, and has a certain stable temperature coefficient. The output voltage of the differential amplifier circuit having the offset voltage is set so that the temperature coefficient based on the offset voltage and the temperature coefficient of the reference voltage cancel each other. As a result, the temperature dependence of the output voltage of the differential amplifier circuit can be eliminated, and a constant output voltage of the differential amplifier circuit independent of temperature can be obtained. Furthermore, since it is not necessary to provide a circuit such as OTA in the reference voltage generation circuit itself, the circuit configuration of the reference voltage generation circuit is not complicated.

  In the reference voltage generating circuit and the differential amplifier circuit constituting the present invention, the reference voltage from the reference voltage generating circuit is input to one input terminal of the differential amplifier circuit, and the output voltage of the differential amplifier circuit is the gate of the output transistor. Applied to the voltage stabilizing circuit in which the output voltage from the output transistor is input to the other input terminal of the differential amplifier circuit, the reference voltage generating circuit and the differential amplifier circuit constituting the present invention have a reference Since the temperature dependence of the output voltage of the differential amplifier circuit can be eliminated without complicating the circuit configuration of the voltage generation circuit, the output voltage of the voltage stabilization circuit can be stabilized.

  In the reference voltage generating circuit and the differential amplifier circuit constituting the present invention, the reference voltage from the reference voltage generating circuit is input to one input terminal of the differential amplifier circuit, and the output voltage of the differential amplifier circuit is the gate of the output transistor. The output voltage from the drain of the output transistor is divided by a plurality of resistors, and the voltage divided by the resistors is applied to the other input terminal of the differential amplifier circuit. For example, the reference voltage generation circuit and the differential amplifier circuit constituting the present invention can eliminate the temperature dependence of the output voltage of the differential amplifier circuit without complicating the circuit configuration of the reference voltage generation circuit. The output voltage of the voltage generation circuit can be stabilized.

  In the reference voltage generating circuit and the differential amplifier circuit constituting the present invention, the output voltage of the reference voltage generating circuit is input to one input terminal of the differential amplifier circuit, and the terminal connected to the voltage to be detected is the differential amplifier circuit. If applied to the voltage detection circuit input to the other input terminal, the temperature dependence of the output voltage of the differential amplifier circuit that becomes the output voltage of the voltage detection circuit without complicating the circuit configuration of the reference voltage generation circuit Therefore, it is possible to improve the accuracy of the voltage detection capability.

1A and 1B are diagrams showing an embodiment, in which FIG. 1A is a cross-sectional view of a MOS transistor constituting a reference voltage generating circuit, FIG. 1B is a circuit diagram of a reference voltage generating circuit, and FIG. It is a circuit diagram.
First, the reference voltage generating circuit will be described with reference to (A) and (B).

  N-type diffusion layers (NB) 5, 7, and 9 are formed at intervals in a P-type well (Pwell) 3 formed on the surface side of the P-type silicon substrate (Psub) 1. An N type high concentration diffusion layer 11 is formed in the N type diffusion layer 5, an N type high concentration diffusion layer 13 is formed in the N type diffusion layer 7, and an N type high concentration diffusion layer 15 is formed in the N type diffusion layer 9. Is formed. Channel dope implantation regions 17 and 19 are formed on the surface of the P-type well 3 between the N-type diffusion layers 5 and 7 and between the N-type diffusion layers 7 and 9. Impurities are introduced into both channel dope implantation regions 17 and 19 at the same concentration.

Elements on the surface of the P-type silicon substrate 1, the surface of the P-type well 3, and the surfaces of the N-type diffusion layers 5, 7, 9 except on the N-type high concentration diffusion layers 11, 13, 15 and the channel dope implantation regions 17, 19. A field oxide film 21 for isolation is formed.
A gate oxide film 23 is formed on the channel dope implantation region 17, and a gate oxide film 25 is formed on the channel dope implantation region 19. The gate oxide films 23 and 25 are formed of a silicon oxide film and have the same film thickness.

An N-type gate electrode 27 is formed from the gate oxide film 23 to the field oxide films 21 and 21 adjacent to the gate oxide film 23, thereby forming an NMOS transistor M1.
A P-type gate electrode 29 is formed over the field oxide films 21 and 21 adjacent to the gate oxide film 25 from the gate oxide film 25 to form an NMOS transistor M2.

  The N-type diffusion layer 5 constituting the drain of the NMOS transistor M1 is connected to the input terminal VIN through the N-type high concentration diffusion layer 11. The N-type diffusion layer 7 constituting the source of the NMOS transistor M1 and the drain of the NMOS transistor M2 is connected to the reference voltage terminal Vref via the N-type high concentration diffusion layer 13. An N-type gate electrode 27 and a P-type gate electrode 29 are also connected to the N-type high concentration diffusion layer 13 and the reference voltage terminal Vref. The N-type diffusion layer 9 constituting the source of the NMOS transistor M2 is connected to the ground terminal GND through the N-type high concentration diffusion layer 15.

  In this reference voltage generating circuit, the impurity concentration of the P-type silicon substrate, the channel dope implantation region, the N-type gate electrode 27 and the P-type gate electrode 29, and the thicknesses of the gate oxide films 23 and 25 are the same as those of the N-type gate electrode 27. The NMOS transistor M1 has a depletion type, and the NMOS transistor M2 having a P-type gate electrode 29 is set to be an enhancement type. The threshold voltage difference between the NMOS transistors M1 and M2 is a reference voltage terminal. Output from Vref.

The constant voltage generation circuit will be described with reference to (C).
The constant voltage generation circuit includes an input terminal VIN, a reference voltage terminal Vref of the reference voltage generation circuit, a differential amplifier circuit 31 having an offset voltage, a PMOS (P-channel MOS) transistor M3 constituting an output transistor, resistors R1 and R2, and an output A terminal VOUT is provided.

  In the differential amplifier circuit 31, the drains of the NMOS transistors M6 and M7 constituting the differential pair are connected to the input terminal VIN via the PMOS transistors M4 and M5 constituting the active load. The gate electrodes of the PMOS transistors M4 and M5 are connected to each other and connected to one of the NMOS transistors M6 and M7, for example, the drain of the NMOS transistor M7, so that the PMOS transistors M4 and M5 serve as a load. The reference voltage is inputted from the reference voltage terminal Vref to the gate electrode of the NMOS transistor M6 constituting the inverting input terminal (−), and the feedback resistance potential (to the gate electrode of the NMOS transistor M7 constituting the non-inverting input terminal (+)). The potential by the resistors R1 and R2) is input. The sources of the NMOS transistors M6 and M7 are connected to each other, and are connected to the ground terminal GND through an NMOS transistor M8 that constitutes a constant current source. A connection point 33 between the PMOS transistor M4 and the NMOS transistor M6, which is an output terminal of the differential amplifier circuit 31, is connected to the gate electrode of the PMOS transistor M3 constituting the output transistor.

The threshold voltages of the NMOS transistors M1 and M2 of the reference voltage generation circuit shown in (A) and (B) will be described.
In general, the threshold voltage Vth of a MOS transistor is
Vth = Φ _MS + Q _SS / C _OX + 2Φ _F + (2ε _S ε ₀ qN _a ) ^1/2 / C _OX (V _BS + 2Φ _F ) ^1/2 (1)
It is represented by
In equation (1), Φ _MS : metal / semiconductor work function difference, Q _SS : gate oxide film interface charge density, C _OX : capacity per unit area of gate oxide film, Φ _F : bulk Fermi level, ε _S : dielectric constant of semiconductor, ε ₀ : vacuum dielectric constant, q: electronic charge, N _a : substrate concentration, V _BS : substrate-source voltage.

For example, the impurity concentration of the P-type silicon substrate 1 is 1.0 × 10 ¹⁶ cm ⁻³ , the impurity concentrations of the channel dope implantation regions 17 and 19 are 5.0 × 10 ^{12 to} 9.0 × 10 ¹² cm ⁻³ , and the gate. The thicknesses of the oxide films 23 and 25 are 30 nm (nanometer), the impurity concentration of the N-type gate electrode 27 is 9.0 × 10 ¹⁹ cm ⁻³ , and the impurity concentration of the P-type gate electrode 29 is 5.0 × 10 ¹⁹ cm. By setting ^-3 , the NMOS transistor M1 can be made a depletion type, and the NMOS transistor M2 can be made an enhancement type. In this case, the threshold voltage of the NMOS transistor M1 having the N-type gate electrode is −0.25 to −0.45 V (volt), and the threshold voltage of the NMOS transistor M2 having the P-type gate electrode is 0.1. It becomes about 4 to 0.6V.

  FIG. 2 is a diagram showing a change in the reference voltage at room temperature when the channel length ratio of the NMOS transistors M1 and M2 is changed in the reference voltage generation circuit shown in FIG. 1, and the vertical axis indicates the reference voltage (V), The horizontal axis represents the N + Poly / P + Poly electrode channel length ratio. Here, the N + Poly / P + Poly electrode channel length ratio represents a value obtained by dividing the channel length of the NMOS transistor M1 having the N-type gate electrode by the channel length of the NMOS transistor M2 having the P-type gate electrode. FIG. 1 shows a plurality of samples in which the channel concentration is adjusted by changing the channel dope implantation amount to change the threshold voltages of the NMOS transistors M1 and M2. The legend shows the threshold voltage of the NMOS transistor M1 having an N-type gate electrode.

  From FIG. 2, when the N + Poly / P + Poly electrode channel length ratio is around 0.85 to 1.15, the reference voltage changes much even if the channel doping is changed and the threshold voltage is changed. I understand that there is no. It can also be seen that there is a point where the tendency of the reference voltage with respect to the N + Poly / P + Poly electrode channel length ratio is reversed with respect to the change in channel concentration. This is the point at which the reference voltage hardly changes.

  FIG. 3 is a diagram showing changes in temperature coefficient when the channel length ratio of the NMOS transistors M1 and M2 is changed in the reference voltage generation circuit shown in FIG. 1, and the vertical axis shows the temperature coefficient (mV / ° C.), The horizontal axis represents the N + Poly / P + Poly electrode channel length ratio. 2 shows a plurality of samples in which the threshold voltage of the NMOS transistors M1 and M2 is changed by changing the channel dope implantation amount, and the legend shows the threshold voltage of the NMOS transistor M1 having an N-type gate electrode. .

  All data values were negative temperature coefficients. The higher the driving capability of a MOS transistor having an N-type gate electrode, the smaller the temperature change of the reference voltage. Similarly to the data in FIG. 2, the N + Poly / P + Poly electrode is similar in that the tendency of the reference voltage against the channel length ratio of N + Poly / P + Poly electrode is reversed with the change of channel concentration. Appears in the channel length ratio region.

  As described above, the reference voltage circuit formed of gate electrodes having different conductivity types and having a channel length ratio of approximately 1: 1 can output a stable reference voltage at room temperature with respect to the channel concentration. Furthermore, it can be seen that the temperature characteristic can be made with the same stable temperature coefficient.

Next, the temperature coefficient of the offset voltage and output voltage of the differential amplifier circuit 31 shown in FIG.
As a method of applying an offset voltage in the differential amplifier circuit 31, the current values of the currents Ia and Ib shown in FIG. 1C are obtained by changing the gate sizes (W / L) of the MOS transistors M4 and M5 constituting the active load. Can be mentioned, a method of making the gate sizes (W / L) of the MOS transistors M6 and M7 constituting the differential pair different, or a method of making them different.

FIG. 4 shows the relationship between the transistor size ratio (Ia / Ib) and the offset voltage of the differential amplifier circuit 31 when the gate sizes of the MOS transistors M4 and M5 constituting the active load are made different. The vertical axis represents the offset voltage (V), and the horizontal axis represents the transistor size ratio (Ia / Ib).
FIG. 4 shows that a desired offset voltage can be obtained by selecting the transistor size ratio.

FIG. 5 shows the relationship between the offset voltage of the differential amplifier circuit 31 and the temperature coefficient of the output voltage. The vertical axis represents the temperature coefficient (mV / ° C.), and the horizontal axis represents the offset voltage (V).
From FIG. 5, it can be seen that a desired temperature coefficient can be obtained for the differential amplifier circuit 31 by selecting an offset voltage value.
Thus, it can be seen from the relationship between FIGS. 4 and 5 that the transistor size ratio is selected to determine the offset voltage and the desired temperature coefficient is obtained.

  For example, in the reference voltage generation circuit, the channel length of the NMOS transistor M1 having the N-type gate electrode 27 and the channel length of the NMOS transistor M2 having the P-type gate electrode 29 are the same, and the threshold voltage of the NMOS transistor M1 is −0. The channel concentration of the NMOS transistors M1 and M2 was set to .3642V, and the temperature coefficient of the reference voltage output to the reference voltage terminal Vref was set to −0.75 mV / ° C. (see FIG. 3).

  On the other hand, in the differential amplifier circuit 31, the gate size of the MOS transistors M4 and M5 constituting the active load is varied to set the transistor size ratio (Ia / Ib) to 40 to obtain an offset voltage of 0.5V. Thus, the temperature coefficient of the output voltage was set to 0.75 mV / ° C. (see FIGS. 4 and 5).

As a result, the negative temperature coefficient of the reference voltage from the reference voltage terminal Vref and the positive temperature coefficient of the output voltage generated from the offset voltage of the differential amplifier circuit 31 can be canceled out, and the output voltage of the differential amplifier circuit 31 is It was confirmed to be constant.
As described above, in the constant voltage generation circuit shown in FIG. 1, since the temperature dependency of the output voltage of the differential amplifier circuit 31 can be eliminated, the output voltage from the output terminal VOUT of the constant voltage generation circuit can be stabilized. Can be planned.
In this embodiment, the offset voltage set for canceling the temperature characteristics of the reference voltage in the differential amplifier circuit 31 is a considerably large value, and is a dimension in the production process that is another factor that determines the transistor capability. It can be easily seen that there is almost no influence on the degree of variation.

  In the embodiment described above, the transistor size ratio (Ia / Ib) is set by changing the gate sizes (W / L) of the MOS transistors M4 and M5 constituting the active load in order to set the offset voltage of the differential amplifier circuit 31. Although the present invention is different, the present invention is not limited to this, and a method of changing the gate sizes (W / L) of the MOS transistors M6 and M7 constituting the differential pair, or a method of changing both of them. A desired offset voltage may be set.

FIG. 6 is a circuit diagram of a voltage stabilizing circuit as another embodiment.
The voltage stabilizing circuit is different from the constant voltage generating circuit shown in FIG. 1 in that the resistor R1 is not provided and the output voltage of the voltage stabilizing circuit is fed back to the non-inverting input terminal of the differential amplifier circuit 31. The voltage at the output terminal VOUT is the same as the reference voltage from the reference voltage terminal Vref. Other configurations are the same as those of the constant voltage generating circuit shown in FIG. 1C, and the configurations of the reference voltage generating circuit are also the same as those of FIGS. 1A and 1B. The amplifier circuit 31 has the same characteristics as the embodiment of FIG.

  In this voltage stabilization circuit, as in the constant voltage generation circuit shown in FIG. 1, the temperature dependence of the output voltage of the differential amplifier circuit 31 can be eliminated, so that the output from the output terminal VOUT of the voltage stabilization circuit The voltage can be stabilized.

FIG. 7 is a circuit diagram of a voltage detection circuit as still another embodiment.
The voltage detection circuit is different from the constant voltage generation circuit shown in FIG. 1 in that the output transistor M3 and the resistors R1 and R2 are not provided, and the voltage to be detected is applied to the non-inverting input terminal of the differential amplifier circuit 31. The input terminal Vsense connected to is connected, and the output terminal of the differential amplifier circuit 31 is the output terminal VOUT of the voltage detection circuit. Other configurations are the same as those of the constant voltage generating circuit shown in FIG. 1C, and the configurations of the reference voltage generating circuit are also the same as those of FIGS. 1A and 1B. The amplifier circuit 31 has the same characteristics as the embodiment of FIG.

  In this voltage detection circuit, as in the constant voltage generation circuit shown in FIG. 1, the temperature dependency of the output voltage of the differential amplifier circuit 31 can be eliminated, so that the output voltage from the output terminal VOUT of the voltage detection circuit can be reduced. Since temperature dependence can be eliminated, the accuracy of voltage detection capability can be improved.

  For example, in the above embodiment, the reference voltage generating circuit is formed by using two NMOS transistors, but the present invention is not limited to this, for example, the same as the configuration described in Patent Document 1 Thus, the reference voltage generating circuit may be formed using three or more MOS transistors.

  In addition, although an NMOS transistor is used as a MOS transistor constituting the reference voltage generation circuit, the present invention is not limited to this, and the reference voltage is determined using two or more PMOS transistors having different gate electrode conductivities. A generation circuit may be formed.

  The embodiments of the present invention have been described above. However, the above dimensions, shapes, numerical values, circuit configurations, and the like are examples, and the present invention is not limited to the embodiments, and the present invention described in the claims. Various modifications are possible within the scope of the invention.

1A is a cross-sectional view of a MOS transistor constituting a reference voltage generating circuit, FIG. 1B is a circuit diagram of a reference voltage generating circuit, and FIG. 1C is a circuit diagram of a constant voltage generating circuit. is there. It is a figure which shows the change of the reference voltage in room temperature when changing the channel length ratio of NMOS transistor M1, M2 in the reference voltage generation circuit which comprises the Example, a vertical axis | shaft is a reference voltage (V), and a horizontal axis is a horizontal axis. N + Poly / P + Poly electrode channel length ratio is shown. It is a figure which shows the change of a temperature coefficient when changing the channel length ratio of NMOS transistor M1, M2 in the reference voltage generation circuit which comprises the Example, a vertical axis | shaft is a temperature coefficient (mV / degrees C), and a horizontal axis is N + Poly / P + Poly electrode channel length ratio is shown. The relationship between the transistor size ratio (Ia / Ib) and the offset voltage of the differential amplifier circuit when the gate sizes of the MOS transistors M4 and M5 constituting the active load are made different in the reference voltage generating circuit constituting the embodiment is shown. FIG. It is a figure which shows the relationship between the offset voltage of the differential amplifier circuit which comprises the Example, and the temperature coefficient of an output voltage. It is a circuit diagram of the voltage stabilization circuit as another Example. It is a circuit diagram of the voltage detection circuit as another Example. It is a circuit diagram which shows the conventional reference voltage generation circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 P type silicon substrate 3 P type well 5, 7, 9 N type diffused layer 11, 13, 15 N type high concentration diffused layer 17, 19 Channel dope implantation area | region 21 Field oxide film 23, 25 Gate oxide film 27 N type gate Electrode 29 P-type gate electrode 31 Differential amplifier circuit 33 Connection point M1 NMOS transistor M2 having N-type gate electrode NMOS transistor M3 having P-type gate electrode PMOS transistors M4 and M5 constituting an output transistor PMOS constituting a differential pair Transistors M6 and M7 PMOS transistor M8 constituting a differential pair NMOS transistors R1 and R2 constituting a constant current source Resistor VIN input terminal VOUT output terminal Vref Reference voltage terminal Vsense input terminal

Claims (6)

  A reference voltage that generates a reference voltage based on a threshold voltage difference of two or more MOS transistors that are formed in the same well and have different channel voltages with the same channel concentration and different gate electrode conductivity. A differential amplifier circuit having an offset voltage to which a reference voltage from the reference voltage generation circuit is input, and the offset voltage of the differential amplifier circuit includes a temperature coefficient of an output voltage based on the offset voltage and the A semiconductor device in which temperature coefficients of reference voltages output from a reference voltage generating circuit are set to cancel each other.   2. The semiconductor device according to claim 1, wherein the offset voltage of the differential amplifier circuit is set so that the gate size ratio of the differential pair and / or the gate size ratio of the active load is not 1: 1.   The reference voltage generation circuit is configured by connecting a depletion type NMOS transistor having an N-type gate electrode and an enhancement type NMOS transistor having a P-type gate electrode in series, and the reference voltage output from the reference voltage generation circuit is The semiconductor device according to claim 1, wherein the semiconductor device has a negative temperature characteristic, and an output voltage of the differential amplifier circuit has a positive temperature coefficient. A reference voltage from a reference voltage generation circuit is input to one input terminal of an inverting input terminal and a non-inverting input terminal of the differential amplifier circuit, an output voltage of the differential amplifier circuit is input to a gate of an output transistor, and the output In a semiconductor device including a voltage stabilization circuit in which an output voltage output from a transistor is input to the other input terminal of the differential amplifier circuit.
A semiconductor device comprising the reference voltage generation circuit and the differential amplification circuit according to claim 1, as the reference voltage generation circuit and the differential amplification circuit. A reference voltage from a reference voltage generation circuit is input to one input terminal of an inverting input terminal and a non-inverting input terminal of the differential amplifier circuit, an output voltage of the differential amplifier circuit is input to a gate of an output transistor, and the output In a semiconductor device including a constant voltage generation circuit in which an output voltage output from a transistor is divided by a plurality of resistors, and the voltage divided by the resistors is input to the other input terminal of the differential amplifier circuit ,
A semiconductor device comprising the reference voltage generation circuit and the differential amplification circuit according to claim 1, as the reference voltage generation circuit and the differential amplification circuit. The output voltage of the reference voltage generation circuit is input to one of the inverting input terminal and the non-inverting input terminal of the differential amplifier circuit, and the terminal connected to the voltage to be detected is input to the other input terminal of the differential amplifier circuit. In a semiconductor device provided with a voltage detection circuit,
A semiconductor device comprising the reference voltage generation circuit and the differential amplification circuit according to claim 1, as the reference voltage generation circuit and the differential amplification circuit.

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