JPH0693579B2 - Channel potential control circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel potential control circuit for stabilizing the operation of a device such as a FET whose channel potential can be controlled by a gate voltage applied to the gate. .

[Outline of Invention]

The present invention is, for example, a transistor (FET) having a MOS structure.
In (1), the potential of the channel portion determined by the voltage applied to the gate is approximated, and correction is performed so that this value becomes constant, whereby fluctuations in Vth of the FET can be eliminated.

[Conventional technology]

In the case of a so-called bipolar transistor, the forward drop voltage V _BE between the base and the emitter is almost constant no matter what process is used.

On the other hand, in the FET, the fluctuation of the gate voltage (threshold voltage) Vth required for causing the strong inversion is extremely large, and about 0.2 V is allowed in a general C-MOS process. .

That is, Vth is the flat band voltage V _{FB of} the element described later.
In addition, the bending of the energy band (2
φ _FP : φ _FP is the Fermi potential of the substrate) and the charge is added to the depletion region. : Ks is the relative permittivity of semiconductor, ∈ ₀ is the permittivity of vacuum, q is the elementary charge, and N _A is the voltage required to generate the acceptor impurity density. Is the oxide film capacity per unit area).

Where V _FB is Where φ _MS is the metal-semiconductor work relationship difference Q _SS is the interface charge density per unit area ρ is the space charge density X ₀ is the oxide film thickness. Therefore, in the general process, with varying amounts of Q _SS by ion implantation or the like V _FB
To change the Vth value. But actually Q
Due to the variation in _SS , the Vth value fluctuates by about ± 0.2V.

And if such a variation in Vth is large, it becomes extremely difficult to keep the potential of the FET constant with the gate-source potential difference V _GS kept constant, and as a result, the drain current I _D fluctuates, For example, when a constant current source is used, the current value and the bias current of the inverting amplifier fluctuate,
It has a drawback that characteristics such as frequency characteristics vary greatly.

That is, with respect to the above equation (1), the relational expression between the gate voltage V _G and the interface potential φ _S when depleted is Is represented. Therefore, the variation Δφ _S of the interface potential from the interface potential in Vth when an arbitrary voltage is applied to the gate is given by the following equation.

By the way, in the case of a normal MOS process, the cause of Vth variation is that any one or more of V _FB , φ _FP , N _A , and Co in equation (1) varies. Therefore, when the gate voltage V _G is kept constant, if such fluctuations that fluctuate Vth occur,
In order to satisfy the equation (4), the interfacial potential Δφ _S when depleted must be changed.

This means that when the voltage V _G is constant at the gate, the interface potential when depleted due to variations in V th changes.

Therefore, first considering the saturation region, the current formula in the saturation region of the FET can be found, for example, in the literature “ASGrove,“ Phusics and Techn.
From Chapter 11 of "ology of Semiconductor Devices", it is given by the following equation.

However, W is the channel width L is the channel length μn is the electron mobility V _D sat is the drain voltage V _D when the saturation region starts, where V _D sat is V _D sat = φ _S −2φ _FP ( 6), the above equations (3) and (6) are substituted into the equation (5), and the drain current I _D is represented by the potential, Becomes Therefore, if the interface potential φ _S when depleted changes, the drain current I _D changes.

Next, considering the linear region, the current formula in the linear region is obtained by replacing V _D sat with the drain voltage V _D in the formula (5) from the above-mentioned literature. Then, by substituting the equation (3) into this equation and expressing the drain current I _D using the potential, Therefore, if the interface potential φ _S when depleted changes as in the saturated region, the drain current I _D changes.

Further, when the drain voltage V _D is extremely small in the linear region, that is, when V _D << 2φ _FP , the current equation at this time is considered from the above-mentioned literature by the following equation.

And if the above equation (3) is substituted into this equation, Also in this equation, if the interface potential φ _S when depleted changes, the drain current I _D also changes.

[Problems to be solved by the invention]

In the conventional circuit using, for example, an FET, there is a problem that the circuit operation is not stable because the fluctuation of the Vth of the element is large and the channel potential is changed accordingly.

[Means for solving problems]

The present invention provides a controlled element having a MOS structure having a source, a drain and a gate, and controlling the potential of a channel formed between the source and the drain by a gate voltage applied to the gate. 40)
In the channel potential control circuit for controlling the channel potential, the channel potential detecting element (10) is provided so as to control the channel potential by a gate voltage equivalent to the gate voltage applied to the gate of the controlled element. , The voltage and reference voltage (voltage source: resistor (30) (3
1)) and a detection circuit (comparison circuit: FETs (20) to (28)) for detecting the difference, and an element for detecting the above channel potential so that the detected difference becomes zero. Is a channel potential control circuit which performs feedback control of the gate voltage and controls the channel potential of the controlled element by using this controlled voltage.

[Action]

According to this circuit, the fluctuation of the potential can be eliminated in the element in which the channel potential can be controlled by the gate voltage applied to the gate of the FET or the like.
It is possible to stabilize the bias current of the inverting amplifier of the current value of the constant current source, etc., and make the characteristics such as frequency characteristics constant.

〔Example〕

In FIG. 1, (1) is a voltage / potential conversion circuit, and a potential corresponding to the potential from this circuit (1) is supplied to a comparison circuit (2). Also voltage source (3)
Is supplied to the comparison circuit (2). The output voltage of the comparison circuit (2) is supplied to the conversion circuit (1).

Further, in this circuit, feedback control is applied so that the potential corresponding to the potential from the circuit (1) becomes equal to the reference voltage from the voltage source (3). As a result, the output voltage of the comparison circuit (2) becomes a voltage for correcting the potential to a constant value.

This output voltage constitutes, for example, a constant current source (4).
By supplying the element whose channel potential can be controlled by the gate voltage applied to the gate of the FET or the like, the current flowing through the load (5) is stabilized and fluctuations in the characteristics of the load (5) are reduced. .

Further, FIG. 2 shows an example of a concrete circuit. In the figure, the voltage / potential conversion circuit (1) is composed of a FET (10), the drain of this FET is connected to a power supply V _DD , the source is grounded through a FET (11) that constitutes a current source, and this source is also connected. Is connected to the gate of one P-type FET (20) for impedance conversion, which constitutes the comparison circuit (2).

The voltage source (3) is formed by providing resistors (30) and (31) made of polysilicon or the like between the power source V _DD and the ground and dividing the resistors. Here, the absolute value of the resistance value of polysilicon changes, but the resistance division ratio hardly changes, so that an extremely stable reference voltage can be obtained. The midpoint of connection between the resistors (30) and (31) is connected to the gate of the other P-type FET (21) for impedance conversion, which constitutes the comparison circuit (2).

Further, the drains of the FETs (20) (21) are grounded, and the sources are connected to the power source V through the FETs (22) (23) for constant current sources.
Differentially connected P-type FETs (24) (2) which are connected to _DD and whose sources form a comparison circuit (2).
5) Connected to the gates respectively. This FET (24) (2
5) Source is the power supply V _DD through FET (26) for constant current source.
And the drain is grounded through the load current source (27) (28) of the current mirror configuration, and the FET (24)
Has its drain connected to the gate of the FET (10).

The connection line to the gate of the FET (10) is connected to the gate of the FET (40) that constitutes the constant current source (4).

The structure of the FETs (10) and (11) is as shown in FIG. 3A, and when the structure is as shown in the middle part of the figure, its potential is as shown in the lower part of the figure. Therefore, the potential formed for Vin (white background)
It is possible to obtain Vout having the same potential as. FET (11)
Is for discharging a minute current from Vout to prevent Vout from becoming higher than the potential of Vin due to the influence of noise or the like. Essentially, it is not necessary as shown in FIG. . Alternatively, a resistor (12) having a high resistance value may be connected as shown in FIG.

That is, in the above-mentioned circuit, the FET (10) is designed so that an extremely small amount of current can flow. In this state, the FET channel can be considered to have just changed from the depleted state to the strong inversion state. On the other hand, the FET at this time
It can be considered that the source of V is simply in a reverse bias state with the substrate, and as described in Chapter 10 of the above-mentioned document, the source voltage Vs is Vs = φ _S −2φ _FP ... ( 11) Here, although φ _FP varies somewhat depending on the process conditions, V _FB has a much larger effect on Vth variation, and in reality, the variation of φ _FP can be ignored.

Therefore, in the above circuit, the potential φ _S and the detection voltage are in a proportional function, and the voltage according to the potential can be detected.

The relational expression between the interface potential and the gate voltage when the surface is depleted is Is represented. Here, in a normal process, V _FB , N _A , and Co vary _greatly , and therefore, if V _G is kept constant, φ _S varies. Therefore, in the above-described circuit, the variation due to V _FB or the like can be canceled by controlling V _G , and φ _S can be made constant.

Considering, for example, the saturation region, the relational expression between the potential and the current is as shown in the above equation (7). Compared with this equation and the equation (5) using the gate voltage, the maximum of both equations is obtained. The difference is that the current equation using potential is V _FB
The term is not included. This also applies to the linear region.

Therefore, the fact that there is no V _FB term in the equation that expresses the current using the potential means that the FET current does not change even if Vth fluctuates if the surface potential when depleted is kept constant. .

Therefore, in the above circuit, by supplying the FET (40) with a voltage that keeps the potential constant, the current flowing through the FET (40) can be made constant. The FETs (10) and (40) are formed in the same process and have at least the same channel length L.

In this way, in the element whose channel potential can be controlled by the gate voltage given to the gate of FET,
By removing the fluctuation of the potential, the drain current can be stabilized.

Furthermore, the following shows an application example.

First, FIGS. 4 and 5 show the case where the device is used as a constant current source, which is connected to the source follower element (50) or the FETs (51) and (52) constituting a differential amplifier, respectively. In these examples, the current value of the element (40) forming the constant current source is stabilized, so that the circuit characteristics and the like can be stabilized. It can also be applied to constant current sources for other circuits.

Further, FIG. 6 shows an example applied to the input bias circuit of the inverting amplifier, in which the resistor (6
A voltage for making the above potential constant is supplied through 1) and is superimposed on the signal supplied by removing the direct current by the capacitor (62). Also in this circuit, the potential at the input bias point is stabilized, and the gain, linearity, frequency characteristic, etc. can be stabilized. Similar effects can be obtained even when applied to the input bias circuit of this circuit source follower.

This circuit also has the effect of stabilizing the circuit current in the circuit configuration in which the current is supplied by the bias.

〔The invention's effect〕

According to the present invention, the fluctuation of the potential of the element can be eliminated, so that the circuit operation can be stabilized.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an example of the present invention, FIGS. 2 and 3 are diagrams for explaining the same, and FIGS. 4 to 6 are configuration diagrams of application examples. (1) is a voltage / potential conversion circuit, (2) is a comparison circuit, (3) is a reference voltage source, (4) is a constant current source, and (5) is a load circuit.

Claims (1)

[Claims] 1. A controlled device having a source, a drain, and a gate, and having a MOS structure configured to control the potential of a channel formed between the source and the drain by a gate voltage applied to the gate. In the channel potential control circuit for controlling the channel potential, the channel potential detecting element is provided so as to control the channel potential by a gate voltage equivalent to the gate voltage applied to the gate of the controlled element. An element for detecting the channel potential, which has a detection circuit for comparing a voltage corresponding to the channel potential extracted from the element for detecting the reference voltage with the reference voltage and detecting the difference. Feedback control of the gate voltage of Both channel potential control circuit so as to control the channel potential of the controlled device by using the control voltage.