JP2765319B2 - Constant voltage circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant voltage circuit, and more particularly to a constant voltage circuit formed on a MOS integrated circuit.

[0002]

2. Description of the Related Art As is well known, a conventional constant voltage circuit is generally a band gap reference circuit composed of bipolar transistors, and a practical constant voltage circuit composed only of MOS transistors is not known. .

[0003]

However, MOS transistors also have various advantages, and it is desired to develop a constant voltage circuit that can be realized on a MOS integrated circuit. At this time, it should be noted that the temperature characteristics of the constant voltage circuit must be good. However, in the case of MOS transistors, the manufacturing deviation is large, and the temperature characteristics are not linear but bipolar like bipolar. The problem is how to control these characteristics.

It is an object of the present invention to provide a constant voltage circuit having a configuration suitable for realizing on a MOS integrated circuit.

[0005]

To achieve the above object, a constant voltage circuit according to the present invention has the following configuration. That is, the constant voltage circuit of the present invention is a constant voltage circuit composed of MOS transistors. An error amplifier that outputs a constant voltage having characteristics; the voltage generating circuit includes a constant current source;
A first transistor having a source directly grounded, a gate connected to the output side of the current source via a first resistor, and a drain connected directly or via a second resistor to the first resistor; A second transistor having a source grounded directly or via a resistor, a gate connected to the drain of the first transistor, and a drain connected to the output of the constant current source via a third resistor; A source connected directly to ground, a gate connected to the drain of the second transistor, and a drain connected directly to the output of the constant current source, or directly connected to a negative feedback loop controlling the constant current source the third transistor being; wherein the error amplifier is the ratio of gate width to gate length is 1: one input of the differential pair composed of two transistors is K ₁ is the constant current A differential circuit, which is the output voltage generated at a connection point between the differential circuit and the first and third resistors, and the other input is a divided voltage; provided between the differential circuit and a power supply; the ratio of the gate length is 1: K active load constituted a two transistor is ₂ and; wherein a level shift circuit for level shifting the output of the differential circuit; take the output of the differential circuit said it And an output circuit for outputting the constant voltage having desired characteristics to the outside and forming the divided voltage by dividing the output constant voltage with a resistor.

[0006]

Next, the operation of the constant voltage circuit of the present invention configured as described above will be described. According to the present invention, the output voltage of the voltage generation circuit is temperature-corrected by the error amplifier to obtain a constant voltage having desired characteristics. At this time, the temperature correction by the error amplifier can be made desired depending on whether or not K ₁ and K ₂ are equal to 1 or greater than 1, and the temperature characteristics can be improved.

Therefore, according to the present invention, it is possible to provide a constant voltage circuit having a configuration suitable for being realized on a MOS integrated circuit.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a constant voltage circuit according to one embodiment of the present invention. In FIG. 1, the constant voltage circuit includes a voltage generation circuit 1
And an error amplifier 2.

The voltage generating circuit 1 basically includes a power supply V _DD
A constant current source I ₀₀ provided on the side, composed out with three MOS transistors (M1, M2, M3). (First)
Transistor M1 has its source grounded directly, a gate connected to the output side of the (first) resistor R1 via the constant current source I _00, the resistance through the drain (second) resistor R2 R
Connected to 1. That is, in this embodiment, the drain may be connected are connected to the output side of the constant current source I ₀₀ through the resistor R2 and the R1 connected in series, omitting the resistor R2 and the drain and gate directly .

[0010] (second) transistor M2 has its source grounded directly, a gate connected to the drain of the transistor M1, a drain (third) output side via a resistor R3 constant current source I ₀₀ Connected to. The source may be grounded via a predetermined resistor.

[0011] (Third) transistor M3 has its source grounded directly, a gate connected to the drain of the transistors M2, the drain is connected directly to the output side of the constant current source I _00. As is well known, a constant current source I ₀₀ is sometimes controlled by the negative feedback loop, in which case the drain of the transistor M3 is connected directly to the negative feedback loop that controls the constant current source May be.

In this voltage generating circuit 1, if the drain currents of the three transistors are I _i , I ₀₀ -I ₃ = I ₁
Generating a reference voltage V _REF to the connection point + I ₂ operates as a resistor R1 and the R3. Hereinafter, a specific description will be given.

If the gate-source voltage of each transistor is _VGSi , the reference voltage V _REF is V _REF = V _GS1 +
Since R1 · I ₁ and V _GS1 −V _GS2 = R2 · I ₁ , Equation 1 is obtained from both equations.

[0014]

(Equation 1)

Accordingly, the temperature characteristic of the reference voltage V _REF can be expressed by Expression 2 obtained by differentiating Expression 1 with respect to temperature.

[0016]

(Equation 2)

Equation 2 can be approximated as Equation 3 when 1 << R1 / R2.

[0018]

(Equation 3)

Here, it is understood from Equation 3 that the value of dV _REF / dT can be positive, negative, or even zero depending on the magnitude relationship between dV _GS1 / dT and dV _GS2 / dT. it can.

Next, the error amplifier 2, and the differential circuit composed of a differential pair of transistors (M4, M5) and the constant current source I _01, the active load composed of two transistors (M6, M7) the transistors M8 and configured level shift circuit in the constant current source I _02, the transistors (M9, M10,
M11) and an output circuit including a capacitor C1, a resistor R6, and a resistor voltage dividing circuit (a series circuit of the resistors R4 and R5).

In the output circuit, a predetermined divided voltage is formed in addition to the original output constant voltage V _OUT , and the divided voltage is fed back to the differential circuit. That is, basically, a resistance voltage dividing circuit composed of a series circuit of the resistors R4 and R5 is provided between the source of the transistor M9 and the ground, and the output constant voltage V _OUT is output from the source of the transistor M9. However, in this embodiment, a transistor M11, which is a voltage passing element, is added, and a resistance voltage dividing circuit is provided between the source of the transistor M11 and the ground. This is appropriately selected depending on the load as the load of the differential circuit.

A reference voltage V _REF from a voltage generating circuit is applied to the gate of one of the two transistors M4 and M5 forming a differential pair of the differential circuit.
The divided voltage from the output circuit is applied to the gate of the other transistor M5. An active load is provided between the differential pair and the power supply V _DD, and the output of the differential pair is supplied to a level shift circuit and an output circuit.

Here, the two transistors M4 and M5 forming the differential pair have a gate width W and gate length L ratio (W
/ L) is, M4: M5 = 1: a K _1. The two transistors M6 and M7 constituting the active load have a ratio (W / L) of the gate width W to the gate length L of M6: M7 = K
₂ : 1. Accordingly, although the differential pair has an input offset, the offset voltage V _OS is obtained as follows.

First, in the differential circuit, the transconductance β ₁ of the transistor M4 is such that the ratio of the gate width W to the gate length L is (W / L) ₁ , the threshold voltage is V _T , the mobility is μ _n , and the unit area is When the gate oxide film capacitance and C _OX, since it is _{β 1 = μ n · C OX} · (W / L) 1/2, the transconductance of the transistor M5 becomes K ₁ · β _1.

Therefore, the drain current I _d4 of the transistor M4 can be expressed by Equation 4, the drain current I _d5 of the transistor M5 can be expressed by Equation 5, and the sum of the two drain currents can be expressed by Equation 6. Further, the offset voltage V _OS can be expressed by the difference between the gate-source voltages of both transistors (Equation 7).

[0026]

(Equation 4)

[0027]

(Equation 5)

[0028]

(Equation 6)

[0029]

(Equation 7)

An active load composed of two transistors (M6 and M7), which are an unbalanced pair, is represented by I _d4 = K ₂ · I
Since it operates so as to maintain the relation of _d5 , I _d4 is obtained as Eq. 8 and I _d5 is obtained as Eq. 9 from this relation and Eq. 6, so if these are substituted into Eqs. Thus, the offset voltage V _OS is obtained.

[0031]

(Equation 8)

[0032]

(Equation 9)

[0033]

(Equation 10)

[0034] Equation 10 shows that the offset voltage V _OS is inversely proportional to the square root of the mobility mu _n, mobility mu _n has a temperature characteristic, the ratio of the absolute temperature T and the T ₀ and mobility mu _n (T )) And the same μ _n (T ₀ ) ratio are related as in Expression 11.

[0035]

[Equation 11]

Therefore, the offset voltage V _OS is given by the following equation (12).
And it is almost proportional to the absolute temperature.

[0037]

(Equation 12)

Then, from equation 12, the offset voltage V
_OS is positive depending on whether K ₁ and K ₂ are greater than 1,
It is either negative or zero. That is, when K ₁ > 1, K ₂ > 1, V _OS > 0, when K ₁ = 1, K ₂ = 1, V _OS = 0, and K ₁ <1, K ₂ < When it is 1, V _OS <0.

The output constant voltage V _OUT and the reference voltage V _REF
Is given by Expression 13, the temperature characteristic of the output constant voltage V _OUT can be expressed by Expression 14.

[0040]

(Equation 13)

[0041]

[Equation 14]

In short, dV _REF / dT is positive, negative, or zero, and dV _OS / dT can be set to positive, negative, or zero, and its magnitude is determined by K ₁ and K _2. As such, dV _OUT / dT can be set to be positive, negative, or zero.

Here, considering the case of dV _OUT / dT = 0, dV _OS / dT is obtained from Expression 14 as Expression 15, but from Expression 12 as Expression 16.

[0044]

(Equation 15)

[0045]

(Equation 16)

In equation (16), since the absolute temperature T is compressed by the root (√) twice, it can be approximated as in equation (17).

[0047]

[Equation 17]

That is, from Expression 17, by appropriately selecting K ₁ , K ₂ and I ₀₁ , (W / L) ₁ , Expression 15 can be satisfied. Therefore, in this case, a constant voltage circuit in which the temperature characteristic of the output constant voltage V _OUT is zero can be realized.

The reference voltage V due to the fluctuation of the power supply V _DD
Fluctuation width of _REF may be reduced by increasing the transconductance g _m of the transistor (M1, M2, M3). Actually, the ratio (W / L) of the gate width to the gate length may be increased. This is the same idea as in the case of the bipolar transistor.

[0050]

As described above, according to the constant voltage circuit of the present invention, the output voltage of the voltage generation circuit is temperature-corrected by the error amplifier to obtain a constant voltage having desired characteristics. At this time, the temperature correction by the error amplifier can be made desired depending on whether or not K ₁ and K ₂ are equal to or greater than 1, and the temperature characteristics can be improved. There is an effect that a constant voltage circuit having a configuration suitable for realizing the above can be provided.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a constant voltage circuit according to one embodiment of the present invention.

[Explanation of symbols]

First voltage generating circuit 2 error amplifier M1~M11 transistor I ₀₀ a constant current source I ₀₁ a constant current source I ₀₂ constant current source V _DD power R1~R6 resistor C1 capacitor

Claims (1)

(57) [Claims] 1. A constant voltage circuit comprising MOS transistors; the constant voltage circuit performs a temperature correction operation using a voltage generation circuit and an output voltage of the voltage generation circuit as a reference voltage, and outputs a constant voltage having desired characteristics. An error amplifier for outputting; a constant current source; a source directly connected to ground, a gate connected to an output side of the current source via a first resistor, and a drain connected to the first current source. A first transistor connected directly or via a second resistor to the resistor; a source connected directly or via the resistor to ground, a gate connected to the drain of the first transistor, and a drain connected to the third resistor A second transistor connected to the output side of the constant current source via a ground; a source connected directly to ground; a gate connected to the drain of the second transistor; A third transistor directly connected to the output side of the source, or directly connected to a negative feedback loop for controlling the constant current source, wherein the error amplifier has a gate width to gate length ratio of 1; : _One input of a differential pair composed of two transistors of K1 is the output voltage generated at a connection point between the constant current source and the first and third resistors, and the other input is a differential circuit is a divided voltage; provided between the differential circuit and the power supply, the ratio of the gate width to the gate length is 1: a K ₂ is composed of two transistors an active load and; said differential circuit A level shift circuit for performing a level shift operation on the output of
An output circuit which extracts an output of the differential circuit, outputs the output as a constant voltage having the desired characteristic to the outside, and forms the divided voltage by dividing the resistance of the output constant voltage. Constant voltage circuit.