JPH1049244A - Reference current and voltage circuit and differential amplification device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an amplification device which has variation in amplification gain suppressed as to an amplification device which uses a MOS-FET. SOLUTION: The device has a 1st MOS-FET and a 2nd MOS-FET which has nearly the same characteristics with the said FET and also has a reference resistance connected to its source or drain, the sources of those MOS-FETs or reference resistances connected to the source of the 1st MOS-FET and the source of the 2nd MOS-FET are connected in common, and the ratio of currents flowing to those MOS-FETs is held at a previously set value. Further, a control means is provided which controls the composite current of currents flowing to those MOS-FETs so that a potential which is nearly equal to the difference voltage between the gate-source voltage of the 1st MOS-FET and the gate-source voltage of the 2nd MOS-FET is applied across the reference voltages; and the controlled composite current is used as a reference current and a voltage developed at the source-side terminal of the MOS-FETs connected in common is used as a reference voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference current / voltage circuit and a differential amplifier used for stabilizing the amplification gain of an amplifier using a metal-oxide-semiconductor-field-effect transistor (MOS-FET). It concerns the device.

[0002] In recent years, from the viewpoint of reducing power consumption, an electronic circuit operating at a low power supply voltage has been desired. Although the voltage of digital circuits has been reduced, analog circuits must be operated at the same power supply voltage.

However, bipolar transistor circuits that have been widely used for analog circuits essentially require a base-emitter voltage (for example, about 0.7 to 0.8 V) or more and a collector-emitter voltage higher than the bandgap voltage. Therefore, there arises a problem that the output amplitude cannot be obtained at a low power supply voltage and the DC bias condition is not satisfied.

On the other hand, in a circuit using a MOS-FET, the drain-source voltage may be small (for example,
Since the required threshold voltage of the gate-source voltage is a controllable parameter (the threshold value changes according to the change in the impurity concentration of the channel), the voltage is lower than that of the bipolar transistor. Operation is possible. Also,
This is also advantageous in terms of integration with digital circuits.

However, in a circuit using a conventional MOS-FET, there is no control circuit for controlling the fluctuation of the amplification gain due to the fluctuation of the temperature or the manufacturing process, and there has been a problem that the fluctuation of the amplification gain is large. Therefore, it is necessary to reduce fluctuations in amplification gain.

[0006]

2. Description of the Related Art FIG. 10 is a block diagram of a main part of a conventional example. In the figure, 61 is a constant current source, 62 is an Nch MOS-FE that works as a constant current source
T and 63 are Nch MOS-FE that works as a constant current source of the differential amplifier circuit
T, 64a and 64b are Nch MOS FETs forming a differential pair, 65a, 65
b is the load resistance. The constant current sources 62 and 63 constitute a current mirror circuit.

The signal flow in FIG. 10 is as follows. The constant current I ₀ from the constant current source 61 is Nch MOS-FET (hereinafter referred to as MO
(Omitted as S-FET.)
A current of I ₁ = (M ₀ / M ₁ ) I ₀ flows through the FET 63.

As a result, the voltage of the amplification gain times the difference voltage (V ₁ -V ₂ ) between the voltages V ₁ and V ₂ applied to the gates of the MOS-FETs 64a and 64b is applied between the drains of the MOS-FETs 64a and 64b. Is obtained. Here, RR Gray / RG issued by Baifukan on 1991.9.10
An expression for calculating the transfer conductance G _m of a source-coupled pair circuit is shown in (12.9) on page 282 of `` Analog Integrated Circuit Design Technology for Super LSIs (2nd volume) '' translated by Mayer and translated by Joe Nagata. .

G _m = (I _SS ) (μ _n · C _OX · W / L) ^1/2 On the other hand, (1.169) and (1.174) on page 59 of the above-mentioned reference (the first volume) show that C _ox = ε _ox / t _ox k ′ = μ _n · (ε _ox / t _ox ) is shown, and when the gain coefficient β = k′W / L is introduced, (μ _n · C _{OX in the} above-described transfer conductance G _m
・ W / L) is β using these equations.

Therefore, the small signal amplification gain G of the MOS-FETs 64a and 64b is approximately represented by G = _Gm × R = R × (β × I) ^1/2 (1).

[0011] Here, R is the load resistance, I is the same as I _SS in G _m at a current value of the constant current source, beta is a transistor gain factor of MOS-FET. Here, since the load resistance value R and the gain coefficient β in the equation (1) fluctuate depending on the conditions of the manufacturing process and environmental conditions such as temperature, the amplification gain largely changes due to these factors.

[0012]

As described above, the MOS-FET
It is known that the gain coefficient β differs for each manufacturing process and greatly decreases as the temperature increases.

Further, load resistors are often integrated in an LSI chip for cost reduction and broadband, but the resistance value R differs depending on the manufacturing process due to variations in impurity concentration and dimensional accuracy. Accuracy is poor.

For example, when the fluctuation of the resistance value is about 30%, the MOS-FE
Assuming that the gain coefficient of T fluctuates by about 30%, the small signal amplification gain fluctuates by about 50%. As described above, the small signal amplification gain G greatly changes due to changes in various conditions.

On the other hand, in an amplifying circuit using a bipolar transistor, the gain also varies, but it has been conventionally known to use a bandgap reference (BGR) circuit for stabilizing the gain.

However, this uses a resistor and a pn junction diode, which have almost the same characteristics as the resistance and the bipolar transistor of the amplifier circuit, to compensate for the gain, and uses a MOS-FET that does not use the characteristics of the pn junction. It cannot be applied to circuits.

As described above, in the conventional MOS-FET amplifier circuit, it has been difficult to stabilize the gain with respect to fluctuations in environmental conditions and fluctuations in manufacturing process conditions. The present invention uses a resistor having substantially the same characteristics as the elements of the MOS-FET amplifier circuit and the MOS-FET to change the current value so as to suppress the fluctuation of the gain coefficient, thereby obtaining the MOS-FET amplifier circuit. An object is to reduce amplification gain fluctuation.

[0018]

FIG. 1 is a diagram illustrating the principle of the first and third embodiments of the present invention. FIG. 1A is a diagram illustrating the principle of the first embodiment of the present invention.
(B) is an explanatory view of the principle of the third invention.

First, a first MOS-FET and the first MOS-FET
A second MOS-FET with almost the same characteristics as a FET, with a reference resistor connected to either the source or the drain
And the sources of the first MOS-FET and the second MOS-FET, or the source of the first MOS-FET and the second MOS-FE
Connect the reference resistor connected to the source of T in common.

Also, the first MOS-FET and the second MOS-FE
The current ratio flowing through T keeps a preset value, and
The gate-source voltage of the first MOS-FET and the second MO
The first and second MOS-FETs are applied so that a potential substantially equal to the difference voltage between the gate and source of the S-FET is applied to both ends of the reference resistor.
Provide control means to control the combined current that combines the current flowing through the FET.

Then, the controlled combined current is used as a reference current, and the first MOF-FET and the second
The voltage that appears at the source terminal of the S-FET is used as the reference voltage.

According to a second aspect of the present invention, in the first and second MOF-FETs, the sources of which are connected to a common constant current source,
The MOS-FET has a differential input terminal connected directly to the drain of the second MOS-FET and the drain of the second MOS-FET connected via the reference resistor, so that the potentials between the differential input terminals are substantially equal. A differential amplifier for controlling the value of the combined current of the constant power supply, and a power supply and a ground plane, which are respectively connected between the differential input terminals and flow through the first and second MOS-FETs. First and second resistors for determining a current ratio are provided.

The controlled combined current is used as a reference current, and a voltage appearing at both ends of the power source or the ground plane and the common source side terminal is used as a reference voltage. According to a third aspect of the present invention, the drain of the first MOF-FET is used as a gate, and the gate of the second MOS-FET is used as a first MOS-FET.
Or the gate of the first MOS-FET to the second
And the drain of the second MOS-FET is connected to the gate.

The source of the first MOS-FET and the second MO
The reference resistor connected to the source of the S-FET is connected to a common constant current source, and the drains of the first and second MOS-FETs are connected to a current mirror circuit.

Then, in the current mirror circuit, the first MO
Control is performed so that the ratio of current flowing through the S-FET and the second MOS-FET maintains a preset value, and the controlled combined current is used as a reference current.

According to a fourth aspect of the present invention, there is provided a differential amplifier using a MOS-FET.
A MOS-FET and a resistor having a characteristic variation factor substantially equal to the MOS-FET and the reference resistance are used as a differential pair and a load resistance, respectively.

The current of the reference current / voltage circuit or the current substantially equal to the current of the reference current / voltage circuit using a current mirror circuit is used as a current source of the differential amplifier circuit.

According to a fifth aspect of the present invention, the current mirror circuit according to the fourth aspect is configured by cascode connection. According to a sixth aspect of the present invention, the reference current / voltage circuit and the differential amplifier circuit according to the fourth and fifth aspects are integrated on the same LSI chip.

Next, the principle of the present invention will be described with reference to FIG. 1; however, between the gate and the drain of the first MOS-FET in FIG. The gate and drain of the second MOS-FET may be connected, but this case is not shown. Further, since the principle of FIG. 1B is substantially the same as the principle of FIG. 1A, only the principle of FIG.

The gain coefficient of the first MOS-FET is β, and the gain coefficient of the second MOS-FET is, for example, the gate width.
When N times, the gain becomes Nβ which is N times the gain coefficient of the first MOS-FET. N is a positive number.

On the other hand, I _D = (k ′ / 2) (W / L) (V _GS −V _t ) ² shown in (1.175) of the first volume of the above-mentioned reference, and β = k′W / L Using the first MOS-FET,
When the currents I ₁ and I ₂ flowing through the second MOS-FET are obtained, they are approximately expressed by the following equations. That is, I ₁ = (β / 2) ・ (V _GS1 − V _t ) ² (2) I ₂ = (Nβ / 2) ・ (V _GS2 − V _t ) ² (3) where V _GS1 , V _GS2 : first and second MOS-FET of the MOS-FET of the gate-source voltage V _t: where the threshold voltage of the MOS-FET, a voltage equal to be applied across the first and second MOS-FET When control is performed such, the potential difference V _GS1, V _GS2 is applied across the reference resistor R _1, the following relationship holds.

[0032] _{R 1 × I S = V GS1} - V GS2 (4) = (2 · I 1 / β) 1/2 - (2 · I 2 / Nβ) 1/2 It should be noted that, for the sake of simplicity I ₁ = If M × I ₂ , the current is represented by the following equation.

I ₂ = 2 · A ² / (R ₁ ) ² β (5) where A = M ^1/2 − (1 / N ^1/2 ) Thus, the current I ₂ is equal to the reference resistance R ₁ Inversely proportional to the square of
A reference current that is inversely proportional to the gain coefficient β is obtained.

Here, it is assumed that the resistance of the amplifier and the characteristics of the MOS-FET are sufficiently uniform and that the relative variations of the characteristics are substantially equal. When the resistance value R and the gain coefficient β of the amplifier are equal to the P times and the Q times of the above R ₁ and β, respectively, the value of the reference current I ₂ is used as the amplifier current, and the current value I ₂ is calculated by the following equation. Substituting into (1), G = P ・ R ₁・ Q ^1/2・ β ^1/2・ 2 ^1/2・ A ・ (1 / R ₁ ) ・ 1 / (β) ^1/2 = P ・ Q ^1/2・ 2 ^1/2・ A = constant (6), and the small signal gain G becomes the reference resistance value R ₁ and the gain coefficient value β
Characteristics that do not depend on.

The voltage generated at both ends of the first MOS-FET, that is, the value of V _GS1 is given by the following equation from the above equation (2). V _GS1 = (2 · M ^1/2 · A ^1/2 ) / (R ₁ · β) + V _T (7) Since β in equation (7) decreases as the temperature increases, the first The term increases in value as the temperature increases. Also, V
_The value of _T decreases as the temperature increases.

Accordingly, if the coefficient of the first term is appropriately set, the coefficient can be used as a reference voltage for which the temperature dependency can be designed such that the temperature dependency of the voltage is almost eliminated. However, in this case, (7) because it is impossible to precision-dependent reference resistance value R ₁ is removed by formula, the reference resistance is required to have a high accuracy.

As described above, according to the present invention, by using the reference current controlled so as to cancel the fluctuation of the reference resistance value and the gain coefficient as the current value of the differential amplifier circuit, the fluctuation of the gain of the differential amplifier circuit is obtained. Can be kept small.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a diagram showing the essential parts of the first and fourth embodiments of the present invention, and FIG. 3 is an explanatory diagram (part 1) of a simulation of the embodiment shown in FIG. Power supply voltage: current value when the reference resistance value is changed, (b) is an explanatory diagram of the power supply voltage: current value when the temperature is changed, and FIG. 4 is a simulation explanatory diagram (part 2) of the embodiment shown in FIG. (C) is an explanatory diagram of the frequency when the temperature is changed: the gain of the differential amplifier circuit, and (d) is an explanatory diagram of the frequency when the temperature is changed: the gain of the differential amplifier circuit.

FIG. 5 is a view showing a main part of the first and fifth embodiments of the present invention, FIG. 6 is a view showing a main part of the second and fourth embodiments of the present invention, and FIG. 7 is shown in FIG. 7A is a diagram illustrating a simulation of the embodiment, in which FIG. 7A is a power supply voltage when the temperature is changed: the voltage value at the point X, and FIG. FIG.

FIGS. 8A and 8B are diagrams showing the main parts of the third and fourth embodiments of the present invention. FIGS. 9A and 9B are explanatory diagrams of the simulation of the embodiment shown in FIG. 8, and FIG. Voltage: MOS-FE
FIG. 4B is a diagram illustrating a current value flowing through a T-43, and FIG.

The same reference numerals indicate the same objects throughout the drawings. In addition, portions that have been described in detail in the conventional example will be briefly described, and portions of the present invention will be described in detail.

Hereinafter, FIGS. 2 to 9 will be described. First, the first and fourth embodiments of the present invention will be described with reference to FIGS.
FIG. 2 shows a differential amplifier circuit to which a bias circuit for gain compensation is added.

In the figure, reference numerals 10 and 11 denote Nch MOS-FETs serving as a reference, 1
7 is reference resistance, 12 is operational amplifier, 16a, 16b is reference
A resistor that supplies a constant current to the MOS-FET, 13 is an Nch MOS-FET that works as a constant current source, 14 is an Nch MOS-FET that works as a constant current source of the differential amplifier circuit, 15a and 15b are differential pair Nch MO
S-FETs 18a and 18b are load resistors.

The Nch MOS-FET 11 has a gain factor N times that of the Nch MOS-FET 10 by, for example, setting the gate width to N times. In addition, the first MO with Nch MOS-FET 10
The S-FET is connected to the second MOS-FE with Nch MOS-FET 11 and reference resistor 17.
Construct T. The constant current sources 13 and 14 form a current mirror circuit.

The operational amplifier 12 adjusts the gate potential of the MOS-FET 13 so that the potentials of the differential inputs become substantially equal, and changes the current. Since the voltages applied to both ends of the resistors 16a and 16b are almost equal, the current flowing through the reference MOS-FETs 11 and 10 is
It is determined by the resistance ratio of 16a, 16b.

Accordingly, the first MOS-
The value of the current flowing through the FET and the second MOS-FET has a characteristic that is inversely proportional to the square of the resistance value of the reference resistor 17 and inversely proportional to the gain coefficient of the Nch MOS-FETs 30 and 31.

The current of the MOS-FET 13 is divided into the first MOS-FET and the second
This is the sum of the currents flowing through the MOS-FETs, and has the same characteristics as the currents of the respective circuits. Also, the current flowing to the constant current source 14 of the differential amplifier circuit is
It has almost the same characteristics as FET 35.

Therefore, the reference resistor 17 and the resistors 18a and 18b use resistors whose characteristic fluctuations are relatively equal, and the Nch MOS-FET
If the MOS-FETs whose characteristic fluctuations are relatively equal between the Nch MOS-FETs 15a and 15b and the Nch MOS-FETs 15a and 15b are used, the small signal gain of the differential amplifier circuit is kept constant.

As described above, according to the present invention, the amplification gain becomes constant irrespective of the fluctuation of the resistance and the Nch MOS-FET, and the design of the amplifier can be facilitated. Generally, in an integrated circuit, since the elements such as resistors and MOS-FETs in the same LSI chip go through the same manufacturing process, the fluctuations in the process conditions are almost the same and the distances are close. The fluctuation of environmental conditions such as temperature and temperature is almost the same.

Therefore, it is considered that the relative ratios of the fluctuations of the element parameters such as the gain coefficient value β and the resistance value R are considered to be substantially the same in the chip, and the condition that the characteristics of the resistance and the MOS-FET are uniform is a problem. Can be fulfilled without.

Thus, the use of the present invention for an integrated circuit is very effective. FIG. 3 shows a simulation result (part 1) of the embodiment shown in FIG. 2, wherein (a) is a power supply voltage: DC current characteristic when the reference resistance value fluctuates ± 30% from the standard value, and (b) is a graph. FIG. 4 is a diagram showing a power supply voltage: DC current characteristic when the ambient temperature fluctuates from −50 to + 100 ° C.
This is a current flowing through the Nch MOS-FET 13.

FIG. 4 shows a simulation result (part 2) of the embodiment shown in FIG. 2. FIG. 4 (c) shows the frequency when the reference resistance value fluctuates ± 30% from the standard value: the differential amplifier circuit. FIG. 9D is a diagram showing the frequency characteristic when the ambient temperature fluctuates from −50 ° C. to + 100 ° C .: the gain characteristic of the differential amplifier circuit.

As shown in FIGS. 3 and 4, as a result of the simulation, the variation of the gain coefficient due to the resistance and temperature causes
It can be seen that the current changes so as to cancel the change in the resistance and the gain coefficient, and as a result, the variation in the small signal gain is suppressed to a very small value.

The first and fifth embodiments of the present invention will be described with reference to FIG. As shown in the figure, a circuit connected in cascode as a constant current source is shown. In the figure, 20 and 21 are the reference Nch MOs.
S-FET, 27 is a reference resistor, 22 is an operational amplifier, 26a and 26b are resistors, 23a and 23b are Nch MOS-FETs acting as constant current sources, 24a,
24b is an Nch MOS-FET that works as a constant current source for the differential amplifier,
25a and 25b are Nch MOS-FETs 28a and 28b forming a differential pair, and are load resistors.

Nch MOS-FETs 23a and 23b functioning as constant current sources
And 24a, 24b constitute a current mirror circuit. here,
Since the current of the MOS-FET depends on the drain-source voltage V _DS , even if the gate-source voltage V _{GS of the} MOS-FET is the same,
There is a problem that the current is different if the V _DS is different.

Therefore, as shown in FIG. 5, if an Nch MOS-FET serving as a constant current source is connected in cascode, a larger power supply voltage is required, but the V _DS dependence of the current is reduced, and the constant current source is reduced. The current values of 23a, 23b and 24a, 24b can be made closer.

The second and fourth embodiments of the present invention will be described with reference to FIG. The embodiment of the present invention shown in FIGS.
Although an S-FET was used, a similar configuration can be made using a Pch MOS-FET. FIG. 6 shows a circuit using a Pch MOS-FET. In FIG. 6, reference numerals 30 and 31 denote reference Pch MOS-FETs, reference numeral 37 denotes a reference resistor, reference numeral 32 denotes an operational amplifier, reference numerals 36a and 36b represent resistors, reference numeral 33 denotes a Pch MOS-FET serving as a constant current source, and reference numeral 34 denotes a differential amplifier circuit. Pch MOS-FETs acting as constant current sources, 35a and 35b constitute a differential pair
Pch MOS-FETs, 38a and 38b are load resistors.

The Pch MOS-FET 31 has, for example, a gate width of N
The gain coefficient is N times larger than that of the Pch MOS-FET 30. The first MOS-FET is replaced with the Pch MOS-FE
The second MOS-FET is constituted by T31 and the resistor 37, respectively. The constant current sources 33 and 34 form a current mirror circuit.

Further, in this embodiment, the potentials of the first MOS-FET and the second MOS-FET are determined with reference to the ground, and can be easily used as a reference voltage. As the reference voltage, for example,
The voltage at the point x in FIG. 6 is used. The voltage at the point x is obtained by adding the voltage effect of the resistor 36b to the voltage of the above equation (7), but the qualitative tendency is the same except that the coefficient of the first term of the equation (7) is different. What is necessary is just to design including minutes.

FIG. 7 shows a simulation result of the embodiment shown in FIG. FIG. 7A shows a DC voltage characteristic when the temperature changes from −50 to 100 ° C., and FIG. 7B shows a temperature between −50 and + 100 ° C.
This is a DC current characteristic when the temperature changes to ° C. In FIG. 7, the horizontal axis is the power supply voltage, the vertical axis is (a) the voltage at the x point, and (b) is the Pch M
This is the current flowing through the OS-FET 33.

According to the simulation results, when the power supply voltage is 2 V or more, the voltage at the point x is stable regardless of power supply fluctuations and temperature fluctuations, and is effective as a reference voltage.

Third and fourth embodiments of the present invention will be described with reference to FIG. In FIG. 8, reference numerals 40 and 41 are reference Nch MOs.
S-FET, 46 is a reference resistor, 42a and 42b are Pch MOS-FETs that constitute a current mirror circuit, 43 is an Nch that works as a constant current source
MOS-FET, 44 is Nch which works as a constant current source of the differential amplifier circuit
MOS-FETs, 45a and 45b are Nch MOS-FETs forming a differential pair, 4
7a and 47b are load resistances.

The Nch MOS-FET 41 has, for example, a gate width N times larger and a gain coefficient N
Double it. And the Nch MOS-FET 40 is the first MOS-FET
The N-channel MOS-FET 41 and the resistor 46 constitute a second MOS-FET, and the constant current sources 43 and 44 constitute a current mirror circuit.

Then, the first MOS-FET and the second MOS-FET
Is controlled at a fixed ratio by the current mirror circuits 42a and 42b, and since the gate potentials of the Nch MOS-FET 40 and the Nch MOS-FET 41 are the same, the Nch MOS-FET 40 and the Nch
The potential difference of V _GS of the S-FET 41 is applied to the resistor 46.

Therefore, according to the above equation (5), the current value
It is inversely proportional to the square of the resistance value of 46, and inversely proportional to the gain coefficient of the NchMOS-FET 41. FIG. 9 shows a simulation result of the embodiment shown in FIG. FIG. 9 (a) shows the DC current characteristics when the resistance value fluctuates ± 30%, and FIG. 9 (b) shows the DC current characteristics when the temperature changes from −50 to + 100 ° C. The horizontal axis in FIG. 9 is the power supply voltage, and the vertical axis is the current flowing through the MOS-FET 43.

As a result of the simulation, it is found that the current changes so as to compensate for the change in the resistance and the gain coefficient due to the change in the gain coefficient due to the resistance and the temperature. The embodiment shown in FIG. 8 is different from the embodiment shown in FIG. 2, FIG. 5, and FIG.
Since the operational amplifier is omitted, the circuit configuration is simplified.

However, as can be seen from the comparison between FIG. 3 and FIG.
The embodiment shown in FIG. 8 is slightly susceptible to power supply voltage fluctuation in that it has a slope, but is advantageous in that the circuit scale is small.

[0068]

As described above in detail, according to the present invention, there is an effect that a reference current / reference voltage circuit for correcting an amplification gain fluctuation of an amplifier using a MOS-FET can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the principle of the first and third aspects of the present invention,
(a) is an explanatory view of the principle of the first present invention, and (b) is an explanatory view of the principle of the third present invention.

FIG. 2 is a main part configuration diagram of a first and a fourth embodiment of the present invention;

FIGS. 3A and 3B are explanatory diagrams (part 1) of the simulation of the embodiment shown in FIG. 2, in which (a) is a power supply voltage when the reference resistance value is changed: current value, and (b) is a power supply voltage when the temperature is changed. : It is explanatory drawing of a current value.

FIG. 4 is an explanatory diagram (part 2) of the simulation of the embodiment shown in FIG. 2, where (c) is the frequency when the temperature is changed: the gain of the differential amplifier circuit, and (d) is the frequency when the temperature is changed. : Is an explanatory diagram of the gain of the differential amplifier circuit.

FIG. 5 is a main part configuration diagram of the first and fifth embodiments of the present invention.

FIG. 6 is a main part configuration diagram of a second and a fourth embodiment of the present invention.

7A and 7B are explanatory diagrams of the simulation of the embodiment shown in FIG. 6, wherein FIG. 7A is a power supply voltage when the temperature is changed: the voltage value at the point X, and FIG. 7B is a power supply voltage when the temperature is changed: MOS- FIG. 4 is an explanatory diagram of a current value flowing through the FET 33.

FIG. 8 is a main part configuration diagram of a third and a fourth embodiment of the present invention.

9A and 9B are explanatory diagrams of the simulation of the embodiment shown in FIG. 8, wherein FIG. 9A is a power supply voltage when the temperature is changed: a current value flowing through the MOS-FET 43, and FIG. 9B is a power supply voltage when the temperature is changed. : MO
4 is an explanatory diagram of a current value flowing through an S-FET 43. FIG.

FIG. 10 is a configuration diagram of a main part of a conventional example.

[Explanation of symbols]

 10, 11 Reference Nch MOS-FET 17 Reference resistance 12 Operational amplifier 16a, 16b Resistance 13, 14 Constant current source 15a, 15b Differential pair 18a, 18b Load resistance 20, 21 Reference Nch MOS-FET 27 Reference resistance 22 Operational amplifier 26a, 26b Resistance 23a, 23b Constant current source 25a, 25b Differential pair 28a, 28b Load resistance

Claims (6)

[Claims] A first MOS-FET and said first MOS-FET;
A second MO having substantially the same characteristics as the S-FET and having a reference resistor connected to one of the source and the drain.
An S-FET, and the sources of the first MOS-FET and the second MOS-FET or the source of the first MOS-FET and the second
, The reference resistor connected to the source of the first MOS-FET and the second MOS-FET are connected in common.
The current ratio flowing through the S-FET maintains a preset value, and is substantially equal to the difference voltage between the gate-source voltage of the first MOS-FET and the gate-source voltage of the second MOS-FET. Control means for controlling a combined current obtained by combining currents flowing through the first and second MOS-FETs so that the same potential is applied to both ends of the reference resistor; A reference current / voltage circuit, wherein a voltage appearing at a source side terminal of a first MOS-FET and a second MOS-FET connected in common is used as a reference voltage. 2. The first MOS-FET of the first and second MOS-FETs whose sources are connected to a common constant current source.
The drain of the FET has a differential input terminal directly connected to the drain of the second MOS-FET via the reference resistor, and the above-mentioned constant value is set so that the potentials between the differential input terminals become substantially equal. A differential amplifier for controlling the value of the combined current of the power supply; and a current ratio connected between one of the power supply and the ground plane and the differential input terminal and flowing through the first and second MOS-FETs. A configuration in which first and second resistors to be determined are provided, and a controlled combined current is used as a reference current, and a voltage appearing at both ends of a power supply or a ground plane and the common source side terminal is used as a reference voltage. The reference current / voltage circuit according to claim 1, wherein: 3. The first MOS-FET has a drain as a gate and a second MOS-FET has a gate as a first MOS.
The gate of the S-FET or the first MOS-FE
The gate of T is connected to the gate of the second MOSFET, the drain of the second MOSFET is connected to the gate, and the source of the first MOSFET and the second MOSFET are connected.
The reference resistance connected to the source of
The drains of the first MOS-FET and the second MOS-FET are respectively connected to a current mirror circuit. In the current mirror circuit, a current ratio flowing through the first MOS-FET and the second MOS-FET is determined in advance. 2. The reference current circuit according to claim 1, wherein control is performed so as to maintain a set value, and the controlled combined current is used as a reference current. 4. A differential amplifying device using a MOS-FET, wherein the first and second MOS-FETs according to claim 1 and a MOS-FE having a characteristic variation factor substantially equal to the reference resistance.
T and the resistor are used as a differential pair and a load resistor, respectively, and the current of the reference current / voltage circuit or the current substantially equal to the current of the reference current / voltage circuit using the current mirror circuit is used as the current of the differential amplifier circuit A differential amplifying device characterized by having a configuration as a source. 5. The current mirror circuit according to claim 4,
A differential amplifying device comprising a cascode connection. 6. A differential amplifier, wherein the reference current / voltage circuit and the differential amplifier according to claim 4 are integrated on the same LSI chip.