JPH07183743A - Voltage-current conversion circuit - Google Patents

Abstract

PURPOSE:To reduce the variance factors by substituting the source resistance between sources of differential MOS transistors TRs with a MOS TR and continuously setting a mutual conductance gm by its gate voltage. CONSTITUTION:The source (or the drain) and the drain (or the source) of a third MOS FET N0 are connected between sources of first and second MOS FETs N1 and N2. Control circuits 12 and 11 for voltages of gate and back gate terminals of this third MOS FET N0 are provided to determine the mutual conductance gm of a voltage-current conversion circuit by only gain coefficients betaof MOS FETs. Then, variance factors are reduced in comparison with a circuit consisting of differential MOS FETs and resistors. Since the mutual conductance gm is determined by the ratio of gain coefficients beta of differential MOS FETs to the gain coefficient beta of the MOS FET N0 connected between their sources, the circuit is affected by only variance factors due to the shapes of coefficients beta.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage-current conversion circuit, and more particularly to a voltage-current conversion circuit which uses a field effect MOS transistor (MOSFET) formed on a semiconductor integrated circuit chip to reduce variation factors and improve linearity. Regarding the circuit.

[0002]

2. Description of the Related Art A conventional MOS differential voltage-current conversion circuit will be described with reference to the drawings. The symbols used in this specification mean that I and ΔI are currents, V and ΔV are voltages, and
R is the resistance, rs is the internal source resistance of the MOS transistor, β is the gain coefficient of the MOSFET, and gm is the mutual conductance of the differential voltage-current conversion circuit.

FIG. 6 shows an example of a conventional circuit configuration diagram. In the figure, N ₁ and N ₂ are the first and second differential NMOSFs, respectively.
ET, V ₁ and V ₂ respectively represent the first and second input terminals and the input voltage, I ₀ represents the constant current source, and I ₁ and I ₂ respectively represent the first and second output currents. . Further, the differential output current ΔI is defined by the following equation (1).

The input / output characteristics of this circuit configuration are shown in FIG.
As shown in (a) and equation (2), the tangent line b at the point where the differential input voltage becomes 0 and the current amplification factor gm takes the maximum value gnmax (see equation (3)) in FIG. The nonlinearity E obtained from the difference between the tangent line and the input / output characteristic curve is defined by the equation (4) using the equations (1) and (2), and is shown in FIG. 7 (b).

[0005]

Numerical values shown in FIGS. 7A and 7B are for I ₀ = 1 mA and β = 1 × 10 ^-3 A / V ² . From this figure, it can be seen that the absolute value of the non-linearity E also increases as the differential input voltage ΔV increases and the differential output voltage ΔI increases. This is I of MOSFET
_This is a phenomenon that occurs in the _D- V _GS characteristic because the change in the drain current I _D is not proportional to the gate-source voltage V _GS of the MOSFET.

The gm of this circuit is determined by the source internal resistance rs of the MOS transistor, and it is difficult to set the continuous gm. Although it is possible to change gm by varying the constant current I ₀ , a change in characteristics due to a change in voltage between both terminals of the constant current source due to a change in gate-source voltage of the differential transistor, and gm is a constant current. There is a problem that it is proportional to the route of and difficult to control.

This characteristic can be similarly considered when the first and second MOSFETs are replaced with PMOSFETs.

FIG. 8 shows a circuit diagram of another conventional example. In the figure,
This shows the case where the source resistance 2R ₀ is provided at the sources of the first and second differential NMOSFETs N ₁ and N ₂ . In addition, I ₀₁ and I ₀₂ are the first and second constant current sources, respectively.
I ₁ and I ₂ represent the first and second output currents, respectively. Here, the constant current I ₀₀ and the differential output current ΔI are defined by the following equation (5). The input / output characteristics in this circuit configuration are shown in FIG. 9A and equation (6), and the differential input voltage is 0 and the current amplification factor gm is the maximum value gnm in FIG. 9A.
The tangent line b at the point where ax is taken (see the equation (7)) is obtained, and the non-linearity E obtained from the difference between this tangent line and the input / output characteristic curve is given by the equation (8) using the equations (5) and (6). Defined in Fig. 9
It shows in (b).

[0010]

Here, the numerical values shown in FIGS. 9A and 9B are I ₀₀ = 1 mA, β = 1 × 10 ^-3 A / V ² , R ₀ = 1 kΩ.
And when. From FIGS. 9A and 9B, it can be seen that as the differential input voltage ΔV increases and the differential output current ΔI increases, the absolute value of the nonlinearity E also increases. This is due to the MOS characteristic of the I _D -V _GS characteristic.
Drain I _D for the gate-source voltage V _GS of the FET
Is not proportional to each other, that is, the differential input voltage ΔV is not proportional to the voltage ΔV _R (differential output current ΔI) across the source resistance as shown in equation (6).

At this time, gm is determined by the source resistance R and the series resistance with the rs of the MOS transistor. Especially, when the source resistances R and rs are about the same, the factors of variation of gm are the above two types. When using a plurality of circuits, it becomes difficult to keep the ratio of gm between the circuits constant.

That is, for example, if R and rs are varied by 30% in the increasing direction and the actual values are R'and rs 'with respect to the design values R and rs, then R' = 1.3R ... (9) rs ′ = 1.3 rs (10) R ′ + rs ′ = 1.3 (R + rs) (11) Here, if R >> rs, the equation (11) becomes the following equation (12) R '+ rs' = 1.3R (12) It can be considered that the variation factor is almost only R.

Therefore, even if there are a plurality of differential circuits in which R has some difference on the same chip, its gm is inversely proportional to only R, so that the ratio of gm can be kept constant.

However, if R and rs are about the same, then R = rs, then (11) becomes (13), and R '+ rs' = 2.6R (13) R or rs alone cannot determine. It is necessary to design in consideration of variations in both. Therefore, the ratio of gm between the differential circuits cannot be kept constant.

The gm of this circuit is determined by rs,
It is difficult to set continuous gm (when I ₀ is constant). Further, when R is large, the area of the semiconductor integrated circuit chip is increased. This characteristic is that the first and second NMOSF
The same can be considered when ET is replaced with PMOSFET.

FIGS. 10A and 10B show still another circuit diagram of the conventional example. This is reported in JP-A-60-7211 and JP-A-60-66510. However, differential voltage is applied to a gate of a MOS transistor provided between differential output terminals. The gain is variable. However, since the MOS transistor is provided between the output terminals, the circuit configuration is obviously different from that of the present invention. Further, the linearity of the differential output is not particularly improved.

FIG. 11 shows another circuit diagram of the conventional example.
This is reported in JP-A-2-81505, but the differential gain is made variable by applying a voltage to the gate of the MOS transistor provided between the emitter terminals of the differential bipolar transistor.

This circuit has a composite circuit structure of a MOS transistor and a bipolar transistor, and in the region where the gain coefficient of the MOS transistor is large, there are two types of gm variation factors, and it is somewhat difficult to maintain a constant gm ratio between the circuits. It will be difficult. Regarding the linearity of the differential output, a MOS transistor is particularly used because the original base-emitter voltage of the bipolar transistor is less dependent on the emitter current and the element is not connected in series to the bipolar transistor. It doesn't improve.

[0020]

As described above, in the conventional circuit, the current amplification factor gm depends on the source resistance R and the MO.
The continuous setting is difficult because it is determined by the rs of the S transistor. The current amplification factor gm is the source resistance R and MO.
It is determined by the rs of the S transistor, and especially when R and rs are about the same, the factors of variation of gm become the above two types, and when a plurality of differential circuits are used, it becomes difficult to keep the ratio of gm between circuits constant. Become. Further, when the source resistance R is large, the chip area of the semiconductor integrated circuit is increased.

The object of the present invention is to solve these problems,
It is an object of the present invention to provide a current-voltage conversion circuit in which the current amplification factor gm can be continuously set and the characteristic variation is reduced.

[0022]

According to the present invention, there are provided first and second MOSFETs having respective gates as first and second input terminals to form a differential input section, and first and second MOSFETs.
Third MOSFET in which a source (or drain) and a drain (or source) are connected to the respective sources or drains of the above MOSFETs, and the sources or drains of the first and second MOSFETs and the third MO
The first and second constant current sources respectively connected between the respective connection points of the source and drain of the SFET and the ground and the gate voltages of the first and second MOSFETs are input and the third voltage is input.
A gate voltage control circuit that supplies a voltage to the gate terminal of the MOSFET, and a back gate voltage control circuit that inputs the voltage at each of the connection points and supplies a control voltage to the back gate of the third MOSFET. Characterize.

[0023]

1 is a circuit diagram showing the basic configuration of a differential current / voltage conversion circuit according to a first embodiment of the present invention. Further, the symbols and configurations representing the elements are common to all the examples, and the first and second constant current sources are provided to the respective source terminals of the first and second MOSFETs (N ₁ , N ₂ or P ₁ , P ₂ ). Differential voltage-current conversion in which I ₀₁ and I ₀₂ are respectively connected, and the source (or drain) and drain (or source) of another third MOSFET N ₀ are connected between the source terminals of the first and second MOSFETs. It is a circuit. Furthermore, MOSFET N ₀
The gate voltage control circuit 11 and the back gate voltage control circuit 12 are provided.

FIG. 2 is a circuit diagram of a second embodiment of the present invention, and FIGS. 3A and 3B are input / output characteristic diagrams thereof. In this circuit, the connection point of R ₁ and R ₂ connected in series to the input terminals V ₁ and V ₂ is connected as a control circuit for the gate terminal voltage of N ₀ . That is, the back gate voltage of V _G given by the following equation is added.

V _G = (V ₁ + V ₂ ) / 2 (20) When the current flowing through each element of this circuit is obtained, βs is N ₀
The following gain equations (21) to (24) are obtained.

[0026]

Next, when Is is expressed using voltage from (21), (22) and (24),

[0028]

[0029] Then, (26), and promises of the first {} Since than both are equal (27), V ₃ -V ₄ and V ₁ -
When the relationship of V ₂ is obtained, the following equation is obtained.

[0030]

Then, V ₃ and V ₄ are obtained. Substituting (28) into (21) and (22) results in the following.

[0032]

Further, (31), (32), (21), (2
When the output currents I ₁ and I ₂ are calculated from 2),

[0034]

Therefore, from (35) and (36), the differential output current ΔI is given by the following equation (37).

ΔI ₁ −I ₂ = (β / 2) {(1-α) ΔV (2V _T + X)} (37) Further, similar to the conventional example, the differential voltage is also shown in FIG. 3 (b). The mutual conductance gm of the current conversion circuit, the non-linearity E, and the established range are defined in equations (38) and (39).

[0037]

Since V _T is positive in this equation (39), linearity is improved as compared with the first conventional example, and there is no variation factor related to the resistance R. It becomes easier to adjust the ratio of.

In this embodiment, the NMOSFET is a PMOSF.
The same can be considered when the ET is replaced with the PMOSFET by the NMOSFET and the constant current source is replaced by the reverse direction.

FIG. 4A is a circuit diagram of the third embodiment of the present invention, in which two diodes D ₁ and D ₂ whose anodes are connected to the input terminals V ₁ and V ₂ are commonly connected to the cathode N.
The gate terminal voltage of ₀ is connected as the control circuit 11. That is, V _G given by the following equation is added.

V _G = V ₁ (V ₁ > V ₂ ) (40) V _G = V ₂ (V ₂ > V ₁ ) (41) A modification of the gate voltage control circuit 11 is shown in FIG. b) ~
There is (f), and almost the same characteristics are obtained, respectively,
Since only a small amount of leakage current basically flows between V _{1 and} V ₂ , the load on the input terminal is not heavy. Further, in the conventional example, in a region where the differential input ΔV is large, the rate of increase of the output current ΔI is decreased and the linearity is decreased.
Since the higher voltage of V ₁ and V ₂ is output than 0) and (41), the conductivity of N ₀ is increased and the linearity can be further improved.

Also in this embodiment, the NMOSFET is replaced by the PMOSF.
The same can be considered when the ET is replaced with the PMOSFET by the NMOSFET and the constant current source is replaced by the reverse direction.

FIG. 5A is a circuit diagram of a fourth embodiment of the present invention, in which two diodes D ₁ and D ₂ having nodes V ₃ and V ₄ respectively connected to the cathodes are connected in common to the anode, and N
It is connected as the control circuit 12 for the back gate terminal voltage of ₀ . That is, V _B given by the following equation is added.

V _B = V ₄ (V ₁ > V ₂ ) ... (42) V _B = V ₃ (V ₂ > V ₁ ) ... (43) As a modification of this back gate voltage control circuit 12, 5 (c) and 5 (d), almost the same characteristics are obtained. If it is not used at a high speed, the configuration shown in FIG. 5B is acceptable and the circuit can be simplified. Basically V ₃ −
Load to the output current since only flow a small amount of leakage current between V ₄ is never called heavy. This circuit can also be used in combination with any circuit of the first or second embodiment.

[0045]

As described above, in the current-voltage conversion circuit of the present invention, the third voltage is provided between the sources of the first and second MOSFETs.
The source (or drain) and drain (or source) of the MOSFET are connected to each other, and a control circuit for controlling the voltage of the gate and the back gate terminal of the third MOS transistor is provided. Can be determined only by the gain coefficient β of
There are few variations, and the transconductance gm of this circuit is determined by the ratio between the gain coefficient β of the differential MOSFET and the gain coefficient β of the MOSFET connected between the sources thereof. It has the characteristic that it is only affected. Further, the linearity of the input characteristic can be improved by the gate voltage control circuit that applies the gate voltage.

Further, by changing the signal output to the gate terminal of the third MOSFET, the third MOSF
Since the mutual conductance of ET can be changed, the mutual conductance of the voltage-current conversion circuit can be changed as necessary.

Further, although the circuit structure of the present invention is impossible or considerably difficult to form by the bipolar process alone, the circuit design in the circuit of the MOS process becomes easy, and the high resistance (low gain) is obtained. It is also possible to reduce the element size in the area. Further, since all the circuits can be constructed by the MOS process, the cost can be reduced by simplifying the process.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a basic configuration of a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a second embodiment of the present invention.

FIG. 3 is a diagram showing input / output characteristics and non-linearity characteristics of the second embodiment.

4A to 4F are circuit configuration diagrams of a third embodiment of the present invention.

5A to 5D are circuit configuration diagrams of a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram of a conventional differential voltage power supply conversion circuit.

7A and 7B are diagrams showing input / output characteristics and non-linearity characteristics of the conventional example of FIG.

FIG. 8 is another circuit diagram of a conventional example.

9A and 9B are views showing the input / output characteristic and the non-linear characteristic of FIG.

10A and 10B are other circuit configuration diagrams of a conventional example.

FIG. 11 is still another circuit configuration diagram of the conventional example.

[Explanation of symbols]

N ₀ to N ₄ N-channel MOS transistor P ₁ to P ₂ P-channel MOS transistor 2R ₀ source resistance and the resistance value I ₀ a constant current source I _1, I ₂ output current V _1, V ₂ input terminals and the voltage V _B N ₀ Back gate voltage V _G N ₀ gate voltage 11 N ₀ back gate voltage control circuit 12 N ₀ gate voltage control circuit

Claims (6)

[Claims] 1. A first and a second MOSFET having respective gates as first and second input terminals to form a differential input section.
And a third MOSFET in which a source (or drain) and a drain (or source) are connected to the sources or drains of the first and second MOSFETs, respectively.
T, and first and second connection points connected between the respective connection points of the sources or drains of the first and second MOSFETs and the sources and drains of the third MOSFET and the ground.
Of the constant current source, the gate voltage control circuit for inputting the gate voltage of the first and second MOSFETs to supply the voltage to the gate terminal of the third MOSFET, and the voltage for each of the connection points respectively A back-gate voltage control circuit that supplies a control voltage to the back gate of the third MOSFET. 2. A differential input section having first and second MOSFETs.
2. The voltage-current conversion circuit according to claim 1, which has a structure for flowing an output current into or out of the output current. 3. The gate voltage control circuit has first and second resistors connected between the first and second input terminals and the gate of the third MOSFET, respectively. The described voltage-current conversion circuit. 4. The gate voltage control circuit comprises first and second diodes connected between the first and second input terminals and the gate of the third MOSFET, respectively. The described voltage-current conversion circuit. 5. The back gate voltage control circuit comprises first and second diodes connected between the first and second input terminals and the gate of the third MOSFET, respectively. 1. The voltage-current conversion circuit described in 1. 6. The voltage-current conversion circuit according to claim 3, wherein the resistance values of the first and second resistors are equal.