JP3037187B2 - MOS differential voltage-current converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential voltage-to-current converter (hereinafter, referred to as a differential circuit), and particularly to a field-effect transistor (hereinafter, referred to as a MOSFET) formed on a semiconductor integrated circuit chip. The present invention relates to a differential circuit in which a variation factor due to a process variation at the time of manufacturing is reduced and linearity is improved.

[0002]

2. Description of the Related Art Some differential circuits using MOSFETs of this kind have already been proposed. Among them, the configuration and operation of the conventional example which is the premise of the present invention will be described with reference to the drawings.

A first conventional example described below is disclosed in Japanese Unexamined Patent Publication No.
No. 83743. Referring to FIG. 7 which shows a circuit diagram of a differential circuit described in the publication, this circuit includes:
N-channel MOSFETs (hereinafter referred to as N-type MOSFETs). The drain electrodes of N ₁ and N ₂ are connected to respective current output terminals.
N ₁ and N ₂ are connected to other circuits suitable for operating in the saturation region, and their source and back gate electrodes are commonly connected to constant current sources DG ₁ and DG ₂ respectively. difference to the source electrode of the N ₁ is connected to the drain (or source) electrode of the N-type MOSFET · N _0, connecting the source (or drain) electrode of the N-type MOSFET · N ₀ to the source electrode of the N-type MOSFET · N ₂ The dynamic circuit is an N-type MOSFET N
Gate voltage control unit G-3 to adjust an amplification gain by controlling the gate voltages of _0, and supplies the voltage to the back gate electrode of the N-type MOSFET · N ₀ back gate voltage control unit B-3
Are further comprised. Gate voltage control unit G-3
Is configured by connecting resistance elements R ₁ and R ₂ in series between a terminal T ₁ and a terminal T ₂ , and connecting a series connection point of these two resistance elements to an output terminal TG ₃ .

[0004] The back gate voltage control unit B-3 is, in each of the two P-type transistors P ₁ and P ₂ gate
While One only connect the source electrodes together to the terminal T _3, the other is respectively a diode equivalent connected to T _4, the source electrode, i.e. the anode side third N-type MOSFET ·
The back gate electrode of N ₀ is commonly connected via a terminal TB.

The input / output characteristics of the differential circuit having the above configuration
8 and 9 showing nonlinearity E, respectively.
Reference: N-type MOSFET N₀Gate voltage of
A control unit G-3 and a back gate voltage control unit B-3 are provided.
N-type MOSFET N₀ Control of the gate voltage
Output current I₁, I_TwoAnd N-type MOSFET N₀
Current I_SThe circuit structure that the resistance value in the differential circuit does not affect
Continuous setting of transconductance gm of configuration and differential circuit is possible.
I'm working.

The main contents will be described below.

[0007] The gate voltage control unit G-3, the resistance of the first input voltage V ₁ and the second input voltage V ₂ R ₁ and R ₂
Controls the gate electrode of the N-type MOSFET · N ₀ in in divided voltage. That is, the gate voltage V given by the following equation
_G is supplied.

In the following, the current I _S flowing through the N-type MOSFET N ₀ and the non-linearity E of the current I _S are obtained.

The voltage at each node is represented by the symbol shown in FIG. 7 and the current flowing through each circuit element is calculated as follows:
It becomes like (6).

I ₁ is the current of the _first N-type MOSFET N ₁ , I ₂ is the current of the second N-type MOSFET N ₂ , I _2
S is a current of the third N-type MOSFET · N _0.

[0011]

[0012]

[0013]

[0014]

Here, β _S is a gain coefficient of N ₀ .

[0016] Then Equation (2), if expressed by using node voltage I _S into Equation (5) (3), we obtain the following equation (7).

By transforming equation (6) and substituting the relationship of equation (1),

Subsequently, assuming that both are equal from equations (7) and (8), the equation in the first parenthesis on both sides is reduced to give V
_When the relationship between ₃ −V ₄ and V ₁ −V ₂ is obtained,

However,

[0020]

Subsequently, V ₃ and V ₄ are obtained. Substituting equation (9) into equations (2) and (3),

[0022]

However,

Further, by substituting equations (12) and (13) into equations (2) and (3), output currents I ₁ and I ₂ are obtained,

[0025]

Therefore, from the equations (15) and (16), the differential output current ΔI is

[0027] Thus, I _S and the differential circuit of the gm / 2 = dI
_{When S} / dΔV is obtained,

[0028]

Further, the transconductance gmmax and the non-linearity E in a balanced state of the differential circuit are expressed by the following equation (2).
0) to (21).

[0030]

Here, each circuit constant of FIG.
If you give it like

Numerical examples of the input / output characteristics and the non-linearity E of the differential circuit are obtained as shown in FIGS.

The above equations (17) to (21) do not depend on the resistance value in the differential circuit, but only on the gain coefficients β and β _{S of the} MOSFET and the constant current source I ₀ , and especially on the same chip. It becomes easy to adjust the ratio of gm when there are a plurality of differential circuits.

A second conventional example of the conventional differential circuit is disclosed in
No. 0-66510. Referring to FIG. 10 which shows a circuit diagram of a differential circuit described in the above publication, this circuit includes gate electrodes of P-type MOSFETs P ₃ and P ₄ for commonly connecting a back gate electrode and a source electrode to a power supply potential VCC. And these gate electrodes are connected to P
Also connected to the drain electrode of the type MOSFET · P _3, each of the drain electrodes are connected by P-type MOSFET · P ₅ terminal TG of the gate electrode of the P-type MOSFET · P ₅
Connect to together, and connecting the drain electrode of the P-type MOSFET · P ₃ to the input terminal T ₁ of the differential input voltage to the gate electrode of the N-type MOSFET · N ₉ connected to the drain electrode of the N-type MOSFET · N ₉ , P-type MOSFET · P ₄
Connect the drain electrode of the drain electrode of the N-type MOSFET · N ₁₀ connecting the gate electrode of the N-type MOSFET · N ₁₀ to the input terminal T ₂ of the differential input voltage, these N-type MO
SFET · N ₉ and N ₁₀ backgate electrode and the source electrode of the commonly connected to a constant current source DG ₅ of the lower power supply side respectively, constructed by connecting a drain electrode of the N-type MOSFET · N ₁₀ to the output terminal T _OUT Is done.

This differential circuit comprises a P-type MOSFET P ₃
And MOSFET · P ₅ provided to the drain electrode of the P ₄
The differential gain can be varied by applying a voltage to the gate electrode.

A third conventional example of the conventional differential circuit is disclosed in
-81505. Referring to FIG. 11 showing a circuit diagram of a differential circuit described in the publication, this circuit connects a collector electrode to a power supply potential VCC via a resistance element R _L1 and connects a base electrode to an input terminal of a differential input voltage. T
Each Emmita electrode of the bipolar transistor Q ₂ to which to connect to connect the collector electrode through the bipolar transistors Q ₁ and the power supply potential resistive element VCC R _L2 and the base electrode to the input terminal T _I2 of the differential input voltage connected to the _I1 the P-type MOS is connected between a P-type MOSFET · G _T
With connecting FET · G _T gate electrode to the terminal T _GC, connect the emitter electrode of the bipolar transistor to Q ₁ low potential power supply side to the constant current source DG _6, a constant current to the emitter electrode of the bipolar transistor Q ₂ of the lower power supply side Source DG ₇
Connected to, connect the collector electrode of the bipolar transistor Q ₁ to the output terminal T _O1, the bipolar transistor Q _2
Is connected to the output terminal T _O2 .

This differential circuit also has a MOSF provided between the emitter electrodes of differential bipolar transistors Q ₁ and Q _2.
By applying a voltage to the gate electrode of the ET · G _T, it has a differential gain variable.

[0038]

SUMMARY OF THE INVENTION As described above, the first
In the conventional example, the optimization of the gate voltage from the viewpoint of linearity improvement of the circuit configuration of and the gate voltage control unit for, for the case where N-type MOSFET · N ₀ operates in a saturation region, to consider further improvements It was to be.

In the second conventional example, since the MOSFET is provided between the drain electrodes of the differential MOSFET, that is, between the voltage output terminals, the linearity of the differential output is not improved.

The third conventional example has a circuit configuration in which a MOSFET and a bipolar transistor are combined.
In a region where the gain coefficient of ET is large, the variation factor of the mutual conductance gm = dΔI / dΔV of the differential circuit is caused by MOS.
There are two types related to FETs and bipolar transistors, and it is difficult to keep the ratio of gm between circuits constant when there are a plurality of differential circuits in the same chip. The linearity of the differential output is due to the fact that the intrinsic base-emitter voltage of the bipolar transistor is less dependent on the emitter current and that no element is connected in series with the bipolar transistor.
It is not improved by using T.

Therefore, the third M which is the premise of the present invention
A gate voltage control unit G-3 for supplying a voltage to the gate electrode of the OSFET · N ₀ for supplying a voltage to the third back gate electrode of the MOSFET · N ₀ back gate voltage control unit B
Even if the differential voltage-to-current conversion circuit having the differential voltage-current conversion circuit having the -3 is not considered, if the output voltage of the gate voltage control unit G-3 is not taken into consideration, further improvement is required to improve the linearity of the differential circuit. And

An object of the present invention has been made in view of the above-mentioned conventional disadvantages. In a differential circuit in which a source resistance between source electrodes of a differential MOS transistor is replaced by a MOS transistor, a gate voltage control of the MOS transistor is performed. Another object of the present invention is to optimize the output voltage of the differential section and improve the linearity of the differential circuit.

The MOS differential voltage-to-current converter of the present invention is characterized in that the drain electrodes of the first and second field-effect transistors are connected to respective current output terminals, and the respective source and back gate electrodes are connected to the first and second gates. And a drain (or source) electrode of a third field-effect transistor connected to a source electrode of the first field-effect transistor, and a source electrode of the second field-effect transistor. A differential circuit connecting a source (or drain) electrode of the third field-effect transistor to the third field-effect transistor to control an amplification gain by controlling a gate voltage of the third field-effect transistor; 3 of the voltage to the back gate electrode of the field effect transistor and a back gate voltage control means <br/> supplied, before Gate voltage control means, the third constant current source
A fourth electrode commonly connecting the gate electrode and the drain electrode
A source electrode of a field effect transistor;
A first differential input connected to the gate electrode of the transistor
A first input terminal for inputting a voltage and the second field effect transistor;
A second differential input voltage connected to the gate electrode of the transistor;
Between a first input terminal and a second input terminal.
The resistance elements are connected in series, and these two resistance elements are connected in series.
Connect the gate electrode to the point and the drain electrode to the voltage source.
And a source electrode of a fifth field-effect transistor,
Each is commonly connected to a fourth constant current source, and
From the drain electrode to the gate of the fourth field effect transistor
It has a configuration for extracting a voltage control signal .

[0044]

Further, the gate voltage control means, the third and the source electrode of the fourth field-effect transistor for commonly connecting the gate electrode and the drain electrodes to the constant current source, before Symbol gate electrode to the first input terminal and a source electrode of the fifth field-effect transistors connected to the connected and a voltage source and a drain electrode, pre SL connecting the gate electrode to the second input terminal and a sixth field effect of connecting the drain electrode to a voltage source Tran
A source electrode of the register, as well as commonly connected to a fourth constant current source, respectively, may have a structure for taking out a gate voltage control signal from said fourth field effect transistor <br/> drain electrode of.

[0046] In addition, the back gate voltage control means
Is the back gate voltage of the third field effect transistor.
On the anode side of the first and second diode means
And the cathode of the first diode means.
The pole is connected to the source electrode of the first field effect transistor.
The cathode electrode of the second diode means is connected to the second
It may have a configuration for connection to the source electrode of the second field-effect transistor .

Further , the first and second power
The source electrode of each field effect transistor and the third
For connection to the back gate electrode of a field effect transistor
The terminal of the back gate voltage control means provided may be in an open state.

[0048] Also, the first and second field effect transistors constituting a differential circuit, may be be a P-type field effect transistor flush out N-type field effect transistor or output current flow into the output current.

[0049] In addition, the third field effect transistor
And it may be to the first and the second of the same conductivity type as the field effect transistor.

[0050] Furthermore, the third field effect transistor, may also be a different conductivity type first and second field-effect transistor.

[0051]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a gate voltage control section for supplying a voltage to the gate electrode of a third MOSFET of the above-described conventional differential circuit, and a back voltage for supplying a voltage to a back gate electrode of the third MOSFET. In a differential voltage / current conversion circuit having a gate voltage control unit, the output voltage is optimized from the viewpoint of improving the linearity of the differential circuit by configuring the gate voltage control unit with an active circuit. I do. To optimize the output voltage here means to make the input / output characteristics of the differential circuit linear, that is, the input voltage ΔV = V ₁ −V in a range of a certain differential input voltage.
₂ , the output currents I ₁ and I ₂ , and the difference I ₁ −I
The current I _{3 of the second} and third MOSFET N ₀ has a proportional relationship, and V satisfies the equation (23) exactly or approximately.
Getting _G.

Here, K is a proportional constant.

Hereinafter, the optimum output voltage of the gate voltage control unit G will be calculated.

First, second and third MOSFET N
Taking the case where N ₁ , N _2, and N ₀ are composed of N-type MOSFETs as an example, it is assumed that the differential circuit has the configuration shown in FIG. First and second MOSFET N
₁ and N ₂ or third MOSFET N ₀ is P-type M
Similar consideration can be given to the case where an OSFET is used.

Here, the back gate control circuit B has the same configuration as that used in the first conventional example.

First and second N-type MOs constituting a differential circuit
SFET · N _1, N ₂ operates in a saturation region, the nodes and voltages V ₁ the differential _{circuit, V 2, V 3, V} 4, V
_G, V _B and the MOSFET, the constant current source DG _1, DG _2,
Current I _1, I ₂ flowing in _{DG 4, I 01, I 02} , the I _G,
1A, equations (24) and (25) hold from Kirchhoff's current law at the nodes V ₃ and V ₄ , and the voltages of the N-type MOSFETs N ₁ and N ₂ Equations (26) and (27) hold from the current relationship.

From the relationship between the voltage and current of the N-type MOSFET N ₀ , the equation (28) holds when N ₀ is in an unsaturated region, and N
Equations (29) and (30) hold when the type MOSFET N ₀ is in the saturation region. Equation (31) is required from the necessary conditions for optimizing the linearity of the differential circuit.

[0058]

[0059]

[0060]

V _G −V ₄ −V _T > 0 and V _G −V ₃ −V
_{When T} > 0 (N ₀ unsaturated region)

[0062] In the case of _{V G -V 4 -V T <0} (V 3 <V 4
N ₀ saturation region at

[0063] <In the case of _{0 (V 3> V G -V} 3 -V T V 4
N ₀ saturation region at

[0064]

Expressions (24) and (25) are replaced by Expressions (26) and (2)
7) are substituted to eliminate I ₁ and I ₂ and V ₃ and V
_{When 4} is obtained, equations (32) and (33) are obtained.

[0066]

Equations (28) to (30) are each expressed by V
Solving for _G and substituting equations (31)-(33) gives
Equations (34) to (36) are obtained.

[0068]

[0069]

[0070] Equation (34) is the optimal solution of V _G to be determined on the N-type MOSFET · N ₀ non-saturation region, the equation (3
5) and (36) is the optimal solution of V _G to be determined is N-type MOSFET · N ₀ in the saturation region, the output of the gate voltage control unit for the input and output characteristics linear differential circuit in each operating region provides a voltage V _G.

The equations (34) to (35) will be discussed below.

The equation (34) is the average of the input voltages V ₁ and V ₂ of the differential circuit (V ₁ + V ₂ ) / 2 (the first term on the right side of the equation).
Equation (35) is the input voltage V ₁ of the differential circuit (the first
Term), and equation (36) represents ΔV = V ₁ −V ₂ , K, and ΔV in the input voltage V ₂ of the differential circuit (the first term on the right side of the equation), respectively.
The correction term depending on I ₀₀ , β, and β _S (the second and third terms on the right side of the equation) is added.

A case in which only the first term (V ₁ + V ₂ ) / 2 of the equation (34) is configured as a circuit corresponds to the circuit of the first conventional example, as in the gate voltage control section G-3 in FIG. I do.

Here, for example, each of the second and third terms is developed in the form of a power of K · ΔV.

Equation (34) is expanded around C = K ・ ΔV = 0, and equations (37) and (38) are obtained.
· ΔV = -I _00/2 of the deployed around formula (39) and (40), equation (36) when the deployed around the _{K · ΔV = + I 00/} 2 Equation (41) and (42) Obtained respectively.

[0076]

[0077]

[0078]

[0079]

[0080]

In addition to the first term of the equations (34) to (36), the open equations (37) to (4) of the second and / or third terms
Strictly including 2), or approximately constitutes a circuit for realizing the output voltage V _G of the gate voltage control unit G, it may be improved linearity of the differential circuit. This expansion expression will be referred to in an embodiment described later.

From the above-described expansion equations, equations (34) to (3)
If the sum of the second and third terms in 6) is obtained in advance, β and β
_{If S} is not significantly different, equations (43a) to (43c) are obtained as approximate equations.

The second and third terms of equation (34)

The second and third terms of equation (35)

The second term + third term of equation (36)

An embodiment according to the present invention and a modified example thereof will be described below. In these embodiments and the modifications thereof, the first, second, and third MOSFETs have the same structure as the first conventional example except for the insides of the gate voltage control unit G and the back gate voltage control unit B. Type MOSFET
In the following description, it is assumed that the differential circuit portion other than the back gate voltage control section G has the configuration shown in FIG.

That is, referring to FIG. 1A showing a circuit diagram of an embodiment of the present invention, this differential circuit comprises drains of _first and _second N-type MOSFETs N ₁ and N ₂ . the electrodes were connected to a respective current output terminals, other suitable circuit is connected to N-type MOSFET · N ₁ and N ₂ is operated in the saturation region to the terminal, each of the source electrode and the back gate electrode with each commonly connected to a constant current source DG ₁ and DG _2, N-type MO
SFET · N N-type MOSFET · N ₀ to the source electrode of ₁
Connect the drain (or source) electrode of the N-type MOS
Differential circuit connecting the source (or drain) electrode of the N-type MOSFET · N ₀ to the source electrode of the FET · N ₂ is,
Gate voltage control unit controls the gate voltage of the N-type MOSFET · N ₀ adjusts the amplification gain G-1, N-type MOSFE
And a back gate voltage control unit B-1 for supplying a voltage to the back gate electrode of T · N ₀ .

The case of the well-known circuit shown in FIG. 1 will be described for the back gate voltage control section B-1. That is, the drain electrodes of the two N-type transistors N ₇ and N ₈ are connected to the terminals T ₃ and T ₄ , respectively, and the gate and source electrodes are connected in common to make them equivalent to a diode respectively. To the third N-type MOSFET
It is configured by connecting to the back gate electrode of T.N ₀ via the terminal TB.

That is, it is assumed that the voltage V _B given by the equations (44) and (45) is added.

[0090]

The back gate voltage controller B- shown in FIG.
As a modification of No. 1, there is the circuit shown in FIG.
Almost the same characteristics can be obtained.
The open structure as shown in FIG. 3B is acceptable and the circuit can be simplified. In addition, the equivalent diode N-type MOSFET N
₇ and N ₈ is connected in the reverse direction, since only flow a small amount of leakage current between terminals T ₃ and T _4, the load with respect to the operation of the differential circuit is sufficiently light.

The gate voltage controller G of the present invention shown in FIG.
-1, the third constant current source DG ₄ which is connected to the high-position power supply side
A fourth N connecting the gate electrode and the drain electrode in common
And the source electrode of the type MOSFET · N _4, the differential input voltage V
_First and _second input terminals T ₁ for inputting ₁ and V ₂
The first and second resistance elements R ₁ and R ₂ are connected in series between T and T ₂ , and the fifth connection point connects the gate electrode to the series connection point of these two resistance elements and connects the drain electrode to the voltage source. with commonly connecting the source electrode of the N-type MOSFET · N ₅ to the fourth constant current source DG ₃ connected to the low potential power supply side respectively, the fourth N-type MOSFET · N ₄
To take out the gate voltage control signal VG from the drain electrode of. Here, the voltage of the common connection point of the source electrode and the constant current source DG ₃ of N-type MOSFET · N ₄ and N ₅ V _0G, a constant current source DG ₃ from the V _0G The current flowing through the I _0G, V ₅ a voltage of the drain electrode of the N-type MOSFET · N _5, the gain factor of the current flowing through the drain electrode I _5, N-type MOSFET · N ₄ and N ₅ beta _G and beta _0G , the output voltage of the terminal TG ₃ and VG.

The gate voltage control section G-1 in this circuit
And calculates the output voltage V _G below.

For example, when the resistance values of R ₁ and R ₂ are equal and the potential at the connection point is (V ₁ + V ₂ ) / 2, the fifth N-type MOSFET N ₅ has a sufficiently high drain electrode voltage, Consider the case where the equation (46) is satisfied and the operation is performed in the saturation region. When the equation (47) is also satisfied,

[0095]

The gain coefficients of N ₄ and N ₅ are β _G and β
_0G, and I ₅ , I _G , I _0G are obtained,

[0097]

[0098]

Thus, solving equation (49) for V _G and equation (50) for V _{0G yields} equation (5)
1) and (52) are obtained,

[0100]

[0102] Then, the equation (51), Substituting Equation (52), the output voltage V _G of the gate voltage control unit G-1 is the formula (53a) ~ (53c).

[0102]

[0103]

Here, H is expressed by equation (54).

In the equation (54), H is 0 for ΔV.
Since this is the next term (constant term), Expression (53a) and Expression (43a) are compared, and if they are equal to each other, Expression (55)
a) is obtained.

Similarly, when the expressions (53b) and (43b) are compared in the same manner, the expression (55b) is obtained when the zero-order term and the first-order term are set to be equal.

[0107]

Similarly, when Equations (53c) and (54c) are compared in the same manner, Equation (55c) is obtained if the zero-order term and the first-order term are equal.

[0109]

From the above results, I _0G , I _G , β _0G , β _G on the right side of equation (55a) are appropriately determined, and the N-type MOSF
When ET · N ₀ satisfies the same relationship in the unsaturated region, Expression (53a) corresponds to the zero-order term for ΔV in Expression (43a), and the present embodiment is a zero-order approximation for the unsaturated region. This is an example of realizing the above.

From the equations (55b) and (55c), when the N-type MOSFET N ₀ satisfies the same relation in the saturation region, the equations (53b) and (53c) become the equations (43)
b) and (43c) correspond to the 0th-order and 1st-order terms for ΔV, and the present embodiment is an example in which the 0th-order and 1st-order approximations are realized in the saturation region.

However, when the gate voltage control section is realized by the circuit configuration of the present embodiment, actually, the expression (55)
The relations a) to (55c) need not be established, and the equation (3)
7) and (38) (or (43a) Formula (39) - (42) (or (43 b) at one subsequent order term and the saturation region of) and (43c)) also considering, optimization of V _G It may be determined in an advantageous manner.

[0113] determine the expressions of I _S below.

[0114] As described above, in the present embodiment, case classification in Table formula I _S is generated by or N-type MOSFET · N ₀ is a non-saturation region or a saturation region, the equation (3
2), (33) and (53a) - a (53c), the formula (28) when is substituted to (30) determining the expression for I _S in each case, N-type MOSFET · N ₀ is a non-saturation region Δ
Range of V, and I _S is the following formula (56), in (57), V ₄
> By the following equation when the at V ₃ is N-type MOSFET · N ₀ in a saturated region (58) and (59), N-type in V ₄ <V ₃ M
When OSFET · N ₀ is in the saturation region, the following equation (60) is used.
And (61), respectively.

[0115]

[0116]

[0117]

[0118]

[0119]

Here, H is the equation (54).

As described above, the expressions (56) to (61) of I _S are as follows:
It is used when calculating a numerical solution described later.

From equation (57), when the differential input voltages are balanced, that is, when ΔV = V ₁ −V ₂ = 0, the N-type MOSFET N ₀ is in an unsaturated region, and When gm / 2 = dI _S / dΔV is obtained, Expression (62) is obtained.

The value of the equation (62) is dI _s / d when the value is the conventional value.
If the circuit constant of the present embodiment is determined to be equal to ΔV, gm in a state where the differential circuits are balanced can be obtained.

FIG. 2 showing the input / output characteristics of the differential circuit when the respective circuit constants of the gate voltage control section G-1 shown in FIG. 1 are set as in the following equation (63), and FIG. Referring to FIG. 3 showing a numerical example, here, the input / output characteristics are calculated from the equations (56) to (61) of the current I _{S and} the nonlinearity E
Was calculated using equation (20), as in the first conventional example.

Here, dI _S / dΔV (ΔV = 0) was calculated from the equations (54) and (62).

From FIG. 2 and FIG. 3, the differential circuit has I ₁ > 0
And in the state of I ₂ > 0, the gate voltage control unit G-1
The optimization of the output voltage V _G, N-type MOSFET · N
It is understood that the absolute value of the non-linearity E decreases in both the saturated region and the non-saturated region when ₀ is ₀ , and the linearity is improved.

In the gate voltage control section G-1 of the above-described embodiment, the conductivity types of all MOSFETs are reversed, all constant current sources are reversed, and the constant voltage sources are reversed in height. The same can be considered for the case.

The first and second MOSFETs N
_{The same} can be said for the case where ₀ and N ₁ and / or the third MOSFET N ₀ are constituted by P-type MOSFETs.

FIG. 4 shows a circuit diagram of a gate voltage control unit G-2 as a modification of the gate voltage control unit G-1 of the present invention.
FIG. 5 showing the input / output characteristics of the differential circuit when the gate voltage control unit G-2 is used, and FIG. 6 showing the non-linearity E of the differential circuit when the gate voltage control unit G-2 is used. This modification will be described with reference to FIG.

Referring to FIG. 4, FIG.
The same reference numerals are given to constituent elements common to the above.

[0131] The gate voltage control unit G-2, the fourth N-type MOSFET commonly connecting the gate electrode and the drain electrode to the third constant current source DG ₄ which is connected to the high potential power supply side,
And the source electrode of N _4, the first to enter the differential input voltages V ₁
A gate electrode connected to the input terminal T ₁ and the source electrode of the fifth N-type MOSFET · N ₅ for connecting the drain electrode to the voltage source, a second input terminal T for inputting a differential input voltage V _{2 2} commonly connected to the sixth fourth constant current source DG ₃ the source and the electrode of the N-type MOSFET · N _6, a are respectively connected to the lower power supply side to connect to connect the gate electrode and a voltage source and a drain electrode Together with the fourth N-type MOSFET
It has a configuration for taking out a gate voltage control signal V _G from the drain electrode of T · N ₄ via the terminal TG _3.

This modification is directed to a third N-type MOSFET.
In non-saturation region of N _0, the formula (37), an example that realizes the second order approximation in (38), calculates the output voltage V _G of the gate voltage control unit G-2 in the circuit below.

Fifth and sixth N-type MOSFETs N ₅
And N ₆ have a sufficiently high drain electrode voltage, and the equation (6)
Considering the case where 4) and (65) are satisfied and operating in the saturation region, and when the expression (66) is also satisfied,

[0134]

[0135]

The gain coefficient of the N-type MOSFET N ₄ is β _G
Assuming that the characteristic coefficients of N ₅ and N ₆ are β _0G , the current I
_{5, I 6, I G,} I 0G is represented by the formula (67) - (70),

[0137]

[0138]

[0139]

[0140] Thus, for the equation (69) V _G, (7
0) is solved for V _0G , respectively, and equations (71) and (7)
2) is obtained.

[0141]

[0142] Then, the equation (71), Substituting Equation (72), the output voltage V _G of the gate voltage control unit G-2 is the formula (73).

However, H is divided depending on the state of the currents I ₅ and I ₆ of the N-type MOSFETs N ₅ and N _6. H when I ₅ > 0 and I ₆ > 0 is H Formula (74) H in the case of I ₅ = I _0G −I _G and I ₆ = 0 is given by the formula (7)
5) H in the case of I ₅ = 0 and I ₆ = I _0G −I _G is expressed by the formula (7)
6)

[0144]

[0145]

Here, in the equation (74), H has a zero-order term (constant term) and a second-order term of ΔV from the expansion equation.
When Expression (73) and Expression (43a) are compared and the corresponding terms are made equal to each other, Expression (77) is obtained.

When N ₀ satisfies the relationship of Expression (77) in the unsaturated region, if Expression (74) is used as H, Expression (73) is obtained.
Corresponds to the zero-order and second-order terms of ΔV in equation (43a), and this modified example is an example of realizing the zero-order and second-order approximations.

On the other hand, when the equations (75) and (76) are used, the zero-order term has the zero-order term, and the zero-order term in the equation (43a) can be regarded as being equal, but the first-order term has no corresponding part. .
However, equation (75) targets only the region where ΔV is positive, and
Since equation (76) targets only the region where ΔV is negative, 1
The following expression can be an approximate expression of the second and subsequent terms of the expression (43a).

However, when the gate voltage control section is realized by the circuit configuration of this modified example, the equation (78) is not necessarily used.
Does not need to be satisfied, and 3 in equations (37) and (38)
Also consider subsequent sections may be determined in favor of the optimization of V _G.

An expression representing the current I _S is obtained below.

[0151] Depending on whether the case of this modified example is also a non-saturation region or N-type MOSFET · N ₀ As with the embodiment described above is a saturated region, as in equation (56) - (61) A case occurs in the equation of the current I _S. Equation (56)-
(61) is used in the numerical solution calculation described later. However, H at this time uses equations (74) to (76).

When the differential input voltages are balanced, that is, when ΔV = V ₁ −V ₂ = 0, the N-type MOSF
ET · N ₀ is a non-saturation region, and gm / 2 =
When dI _S / dΔV is obtained,

Here, H is the equation (74).

The value of equation (79) is dI _S / d in the case of the conventional case.
If the circuit constant of the present modified example is determined so as to be equal to ΔV, g in a state where the same differential circuit as in the related art is balanced is obtained.
m is obtained.

FIG. 5 shows input / output characteristics of the differential circuit when the respective circuit constants of FIG. 4 are set as in the following equation (80), and FIG. 6 shows a numerical example of the nonlinearity E. Here, the definition of the non-linearity E is the same as in the first conventional example.

Here, dI _S / dΔV (ΔV = 0) was calculated from the equation (79).

5 and 6 that the differential circuit has I ₁ > 0
And in the state of I ₂ > 0, the gate voltage control unit G-2
It can be seen that the absolute value of the nonlinearity E of the N-type MOSFET N ₀ is reduced in both the saturation region and the non-saturation region, and the linearity is improved by optimizing the output voltage.

In the above-described modified example, the same can be considered when the conductivity types of all MOSFETs are reversed, all constant current sources are reversed, and the constant voltage sources are reversed in height.

[0159]

As described above, in the MOS differential voltage-to-current conversion circuit of the present invention, the drain electrodes of the first and second MOSFETs are connected to respective current output terminals, and the respective source electrodes and back gate electrodes are connected to the first and second gates. Connected to the first and second constant current sources, respectively, and
A differential circuit that connects the drain (or source) electrode of the third MOSFET to the source electrode of the SFET and connects the source (or drain) electrode of the third MOSFET to the source electrode of the second MOSFET, MOSFET
A MOS differential voltage / current conversion circuit further comprising: a gate voltage control means for controlling the gate voltage of the third MOSFET to adjust the amplification gain; and a back gate voltage control unit for supplying a voltage to the back gate electrode of the third MOSFET. By configuring the gate voltage control means using an active element composed of a MOSFET, the input / output characteristics of the differential circuit are more linear in both the saturated region and the unsaturated region of the third MOSFET. Since the output voltage of the gate voltage control means is changed, the mutual conductance of the differential voltage-to-current conversion circuit can be changed as required by simply changing the output voltage of the gate voltage control unit. The linearity of the input / output characteristics of the circuit was improved.

Also, the gate voltage control unit of the present invention
It can be configured with only the S process, and the differential MOSFET
And gain factor of MOSFET between source and MOSFET of gate voltage control unit and back gate voltage control unit
Since the relative accuracy of the gain coefficient is easily obtained, the design is easy, which is advantageous for improving the linearity.

Further, since all the circuits can be formed by the MOS process, the cost can be reduced by simplifying the process.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention.

FIG. 2 is a diagram illustrating input / output characteristics of a differential circuit according to one embodiment.

FIG. 3 is a diagram illustrating non-linear characteristics of a differential circuit according to one embodiment;

FIG. 4 is a circuit diagram of a modification of the gate voltage control unit according to the embodiment of the present invention.

FIG. 5 is a diagram illustrating input / output characteristics of a differential circuit in a modification of the gate voltage control unit.

FIG. 6 is a diagram illustrating non-linear characteristics of a differential circuit in a modification of the gate voltage control unit.

FIG. 7 is a circuit diagram showing a first example of a conventional differential voltage-to-current converter.

8 is a diagram showing input / output characteristics of the conventional example of FIG. 7;

FIG. 9 is a diagram showing non-linear characteristics of the conventional example of FIG. 7;

FIG. 10 is a circuit diagram of a second example of a conventional differential voltage-to-current converter.

FIG. 11 is a circuit diagram of a third example of a conventional differential voltage-to-current converter.

[Explanation of symbols]

 B-1, B-2, B-3 Back gate voltage control unit β Gain coefficient of first and second MOSFETs  β_S Gain factor of the third MOSFET  β_G Gain factor of the fourth MOSFET  β_0G Gain coefficients of fifth and sixth MOSFETs  G-1, G-2, G-3 Gate voltage controller I₀₀, I₀₁, I₀₂ Current value of constant current source I₁, I_Two Current I of the first and second N-type MOSFETs_S The current I of the third N-type MOSFET I_Five, I₆ Current of the fifth and sixth MOSFETs I_G, I_0G Current value of constant current source N₁~ N_Ten N-type MOSFET P₁~ P_Five P-type MOSFET R₁, R_Two Resistance element R in gate voltage control unit_L1, R_L2 Resistance element of differential circuit V₁, V_Two Voltage V of differential input terminals T1 and T2_Three~ V₆, V_0G Node voltage V_B N₀Back gate electrode voltage V_G N₀Gate electrode voltage

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-63-309010 (JP, A) JP-A-2-32610 (JP, A) JP-A-58-186208 (JP, A) JP-A-7-309 183742 (JP, A) JP-A-8-228115 (JP, A) JP-A-8-330861 (JP, A) JP-A-10-49244 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03G 1/00-3/18

Claims (7)

(57) [Claims] 1. A drain electrode of a first and a second field-effect transistor is connected to a current output terminal, and a source electrode and a back gate electrode are connected to a first and a second gate, respectively.
Connected to the constant current sources of
The drain (or source) electrode of the third field effect transistor is connected to the source electrode of the third field effect transistor, and the source (or drain) electrode of the third field effect transistor is connected to the source electrode of the second field effect transistor. A gate voltage control means for controlling the gate voltage of the third field effect transistor to adjust the amplification gain, and a back circuit for supplying a voltage to a back gate electrode of the third field effect transistor. and a gate voltage control means, said gate voltage control means, gate electrode to the third constant current source
Fourth field effect transistor for commonly connecting the pole and the drain electrode
A source electrode of the transistor and the first field-effect transistor.
The first differential input voltage is connected to the gate electrode of the
First input terminal and the second field effect transistor
To the second differential input voltage
The first and second resistive elements are directly connected to the second input terminal.
Connect in columns and gate at the point of series connection of these two resistive elements
Fifth connecting electrode and connecting drain electrode to voltage source
And the source electrode of the
4 and the fourth electric field.
Gate voltage control signal from the drain electrode of the effect transistor
A MOS differential voltage-to-current conversion circuit having a configuration for extracting a signal. Wherein said gate voltage control means, the third and the source electrode of the fourth field-effect transistor for commonly connecting the gate electrode and the drain electrodes to the constant current source, before Symbol gate electrode to the first input terminal and a source electrode of the fifth field-effect transistors connected to the connected and a voltage source and a drain electrode, pre SL connecting the gate electrode to the second input terminal and a sixth field effect of connecting the drain electrode to a voltage source Transis
A source electrode of the capacitor, as well as commonly connected to a fourth constant current source, respectively, said fourth MOS differential voltage-to-current of claim 1 having a configuration for taking out a gate voltage control signal from the drain electrode of the field effect transistor Conversion circuit. 3. The method according to claim 1, wherein the back gate voltage control means includes a first gate connected to a back gate electrode of the third field effect transistor.
And the anode side of the second diode means is commonly connected, the cathode electrode of the first diode means is connected to the source electrode of the first field-effect transistor, and the cathode electrode of the second diode means is connected to the second diode means. 3. The MOS differential voltage-to-current conversion circuit according to claim 1, wherein the MOS differential voltage-current conversion circuit has a configuration connected to the source electrodes of the two field effect transistors. 4. The first and second field effect traverses.
Source electrode of each transistor and the third field-effect transistor.
It shall be the open terminals of the <br/> back gate voltage control means provided for connecting the back gate electrode of the transistor
請 Motomeko 1 or 2 MOS differential voltage-to-current converter circuit as claimed. The method according to claim 5 wherein said first and said second field effect transistor constituting a differential circuit, flowing the output current N
Claim 1 shall be the type field effect transistor or a P-type field effect transistor pouring off the output current, 2, 3 or 4
2. A MOS differential voltage-current conversion circuit according to claim 1. Wherein said third field effect transistor, MOS differential voltage-to-current conversion to that claim 1, 2, 3 or 4 wherein said first and said second same conductivity type field effect transistor circuit. The method according to claim 7 wherein said third field effect transistor, the first and the claims 1 shall be the second field effect transistor and the conductivity type different from 2, 3 or 4 MOS differential voltage-to-current conversion circuit according .