JPH0738348A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To lower an operating power supply voltage without losing a high speed property and versatility of an operation of the semiconductor integrated circuit. CONSTITUTION:A gate and a drain of PMOS transistors (M403, M405) for constituting a load of the semiconductor integrated circuit are connected to a source and gate of NMOS transistors (M401, M408), respectively, and by a current value by which a prescribed voltage is generated between the source and the gate of the NMOS transistor, the NMOS transistor is driven by a current.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit, and more particularly to a technique for lowering the operating voltage of an analog MOS semiconductor integrated circuit and for speeding up and widening the band during low voltage operation.

[0002]

2. Description of the Related Art FIG. 7 is a circuit diagram showing a first example of a conventional high speed differential amplifier. This differential amplifier includes NMOSFETs M404 and M406 that form an input differential pair, PMOSFETs M403 and M405 that form a load, and NMOSFET M407 that forms a current source. The current value of the current source M407 is the gate bias VB41.
Set by. The differential inputs VI1 and VI2 are applied to the gates of the input differential pair M404 and M406, and the drains of these transistors are used as output terminals for the differential output V1.
O81 and VO82 are output. Voltage gain of this differential amplifier | (VO82-VO81) / (VI2-VI
1) | is generally a good approximation for DC at g _mN / g
given in _mP . Here, g _mN is the mutual conductance of M404 and M406, and g _mP is the mutual conductance of M403 and M405. The transconductance of the MOSFET in the saturation region is (μC _0X W _ID / L) ^1/2 (μ:
Carrier mobility, C _0X : capacitance of gate oxide film per unit area, W: gate width, L: gate length, I _D : drain current), and carrier mobility μ is generally 2 in NMOSFET compared to PMOSFET. ~ 3 times larger.
Therefore, it is possible to reliably obtain a DC voltage gain g _mN / g _mP of the circuit of FIG. Also, the circuit of FIG. 7 generally has a small maximum output amplitude.
From the characteristics of the low voltage gain and the small output amplitude, the circuit of FIG. 7 generally has high speed (generally, it is known that the GB product, that is, the product of the DC voltage gain G and the frequency band B is almost determined by the manufacturing process. ing). In order for the circuit of FIG. 7 to operate with the DC voltage gain g _mN / g _mP , M404 and M406 need to operate in the saturation region.
When the voltage gain of the circuit of FIG. 7 is not sufficient, differential amplifiers are further cascade-connected as shown in FIG. The differential pair M901 and M903 are PMOSFETs, and the load transistors M902 and M904 are NMOSFETs. The outputs VO81 and VO82 of the circuit of FIG. 7 are M90.
1, input to the gates of M903 and output VO9
Is obtained at the output terminal of the transistor M903 in a single-ended form. When the amplifiers are connected in cascade as shown in FIG. 8, the high speed performance is slightly deteriorated, but since the input is amplified by the first stage differential amplifier including M403 to M407, the signal delay in the differential amplifier including M901 to 904 is increased. Is not a big problem.

FIG. 9 is a circuit diagram of a third example of a conventional differential amplifier. NMOSFETs M404 and M406 form an input differential pair, and PMOSFETs M403 and M405.
Are load transistors of the differential pair M404 and M406. NMOSFET M407 forms the current source. P
MOSFET MA01 and NMOSFET MA0
Reference numeral 2 constitutes a bias circuit that supplies a gate bias to the load transistors M403 and M405. This circuit corresponds to the load transistor M403,
While the gate and drain of M405 are short-circuited, the load transistors M403 and M403 of FIG.
The gate and drain of 405 are separated. Therefore,
The common mode potentials of the outputs VO81 and VO82 in the circuit of FIG. 7 are lower than the common mode potentials of the outputs VOA1 and VOA2 of the circuit of FIG. 9, and as a result, the circuit of FIG. The common mode input range is narrower.

Now, referring to FIG. 7, input voltages VI1 and VI
If the common-mode voltage of 2 is V _COM , then NMOSFET M4
From the condition that 04 and M406 operate in the saturation region, (VDD− | V _TP | −α) −V _S ≧ V _COM −V _S −V _TN (1). The left side is M40 when VI1 and VI2 are equal.
4, the voltage between the drain and the source of M406, and the right side is the voltage between the gate and the source of M404 and M406. Further, V _S is the potential of the node where the sources of M404 and M406 and the drain of M407 are connected, and α is the load M40.
3, the source-gate voltage of M405 (which is equal to the source-drain voltage in FIG. 7) to M403, M405
Is a value obtained by subtracting the absolute value of the threshold voltage V _TP (<0) of, and α ≧ 0 according to the ON condition of M403 and M405.
V _TN is the threshold voltage of M404 and M406. From the formula (1), V _COM <VDD + V _TN − | V _TP | −α (2). In the circuit of FIG. 9, similarly, M404, M4
From the condition that 06 operates in the saturation region, (VDD−α) −V _S ≧ V _COM −V _S −V _TN (3), and thus V _COM ≦ VDD + V _TN −α (4). The left side of equation (3) is M40 when considering that M403 and M405 must operate in the saturation region.
4, M406 is the maximum drain-source voltage, and α is the minimum source-drain voltage required for M403 and M405 to operate in the saturation region. M4
The reason why 03, M405 needs to operate in the saturation region is that otherwise, the voltage gain of these transistors is significantly reduced and the circuit does not operate normally. Comparing equation (3) and equation (4), FIG.
Circuit upper limit of the in-phase input range compared to the circuit of Figure 7 is | V _TP
You can see that it is higher only by |. Therefore, the circuit of FIG. 9 can operate to a lower minimum power supply voltage than the circuit of FIG. 7. In addition, here, in order to adjust the conditions, FIG.
9 and the circuit current of the differential amplifier is the same. Therefore,
It was considered that the gate potentials of M403 and M405 also match between FIG. 7 and FIG.

Next, the operating speed of the circuit of FIG. 9 will be described. In the circuit of FIG. 7, since the drains of the load PMOSFETs M403 and M405 connected to the output terminals VO81 and VO82 are connected to their respective gates, the output amplitude is small and the voltage gain is stable and several times as described above. Is obtained. However, in the circuit of FIG.
The drains of the FETs M403 and M405 are output terminals VOA1 and VOA2 and the NMOSFET M40, respectively.
4, because it is connected only to M406, the output VOA1 is M
403 and M404 can take any potential that operates in the saturation region, and the output VOA2 is M405 and M40.
Since 6 can take an arbitrary potential operating in the saturation region, the output amplitude is large. Further, since the DC voltage gain of the circuit of FIG. 9 is given by g _mP / (g _dN + g _dP ), it is about 10 times larger than that of the circuit of FIG. Where g _dN and g _dP are NMOSFET M40
4, M406, PMOSFET M403, M405 channel conductance. Therefore, the circuit of FIG. 9 is generally slower than the circuit of FIG.

FIG. 10 is a circuit diagram showing a fourth example of a conventional differential amplifier. In the case where differential amplifiers are cascade-connected in a ring shape to form a ring oscillator, the circuit of FIG. 9 has NMOSFETs (MB01, MB01) as shown in FIG.
02) and NMOSFETs (MB03, MB04) to add a source follower level shift stage. This is because when the circuit of FIG. 9 is connected in cascade, the circuit can lower the common-mode input voltage rather than directly setting the outputs VOA1 and VOA2 to the inputs VI1 and VI2 of the next stage, so that the power supply voltage can be lower. It is possible to operate even if lowered to.

FIG. 11 is a circuit diagram showing a fifth example of a conventional differential amplifier. This differential amplifier has bidirectional diode-connected NMOSFETs MC1 and MC2 added in order to improve the drawback that the output amplitude is large, which is one of the causes of lowering the operation speed of the circuit of FIG. . However, since the MOSFET normally has a threshold value of about 1 V and the common mode voltage of the outputs VOA1 and VOA2 is between the ground potential and the potential of the positive power supply VDD, the threshold values of MC1 and MC2 are back gated. Since it is further increased by, the speedup effect of MC1 and MC2 in the circuit of FIG. 11 cannot be sufficiently obtained.

FIG. 12 is a circuit diagram showing a sixth example of a conventional differential amplifier. This differential amplifier is disclosed in JP-A-60-90.
No. 407, so-called folded
It is an example of a cascode amplifier, and can operate at high speed and with a low power supply voltage. BD1 and BD2 are NPN bipolar transistors with grounded emitters, BD3 and BD4 are PNP bipolar transistors with grounded bases, and RD1 to R
D6 is a resistor, VOD1 and VOD2 are output terminals, VBD
Is the base bias voltage of the grounded base transistors BD3, BD4. The circuit shown in FIG. 13 is obtained by reconfiguring the circuit of FIG. 12 with MOSFET technology. The NMOSFETs ME1 and ME2 form an input differential pair, the NMOSFET ME3 forms a current source, and the PMO
The SFET ME6 and ME7 are cascode transistors whose gates are grounded. In addition, PMOSFET ME4, ME
5 is a load transistor, ME8 and ME9 are load transistors, VOE1 and VOE2 are output terminals, VBE1 is a gate bias voltage of the load transistors ME4 and ME5, V
BE2 is the gate bias voltage of the cascode transistors ME6 and ME7, VBE3 is the load transistor ME8,
This is the gate bias voltage of ME9. In the circuit of FIG. 13, since the gates of ME4 and ME5 are biased with a constant voltage similarly to the circuit of FIG. 9, the source-drain voltage is set to the load transistors M403 and M40 of the circuit of FIG.
It can be made smaller than the case of 5. As a result, similarly to the circuit of FIG. 9, the upper limit of the common-mode input voltage becomes higher than that of the circuit of FIG. 7, which is suitable for use when the power supply voltage is low. Also, since it is a cascode connection, it has high speed. However, in the case where the voltage-controlled oscillator (VCO) is configured by cascade-connecting in a ring shape and using VB41 as a control voltage, the oscillation range is narrow and the versatility is lacking. Because when VB41 is increased to increase the circuit current, the transconductance of ME1 and ME2 increases, but the cascode transistors ME6 and M
This is because the transconductance of E7 becomes small on the contrary, and the speed of the circuit as a whole does not change so much, so that the oscillation frequency cannot be changed in a wide range. Also, since this differential amplifier is cascode-connected, as described above, it is possible to have high-speed performance based on the characteristics of cascode-connection, but since the amplitudes of the outputs VOE1 and VOE2 are large, sufficient high-speed performance is not necessarily achieved. You can't always get it.

FIG. 14 is a circuit diagram of a conventional bandgap reference voltage circuit. PMOSFET M303, M30
5, M307 form a current mirror circuit. NMOSF
The gates of ETM304 and M306 are commonly connected, and the gate thereof is connected to the drain of M306. The junction diode D301 is connected via the resistor R301.
The source of M304 is connected in the forward direction between the ground terminal, the junction diode D302 is connected in the forward direction between the source of M306 and the ground terminal, and the junction diode D303 is connected through the resistor R302 to the drain of M307. And the ground terminal are connected in the forward direction. Generally, D301 has a junction area n (> 1) times that of D302, D303 has the same junction area as D301, and the resistance R302 has a resistance value m (> 1) times that of the resistor R301. M303, M305, M307 and M30
4 and M306 have the same gate length and gate width, respectively. At this time, the voltage of the output VO3 is given by (kT / g) [mlnn + ln [kTlnn / (g · r · I _s )] (5), and if the value of m is adjusted so that the temperature characteristic disappears, almost energy It is known that the band gap becomes large. Here, k is the Boltzmann constant, q is the elementary charge, T is the absolute temperature, r is the resistance value of R301, and I _S is the saturation current of D301.

The minimum operating power supply voltage of this circuit is usually M
This is determined by the condition that M304 must be saturated in the series connection part including 303, M304, R301, and D301, and the condition that M305 must be saturated in the series connection part including M305, M306, and D302. The reason why M304 must be saturated is that the voltage given by equation (5) cannot be output unless the same current as on the M306 side flows. The same applies to M305. The condition for M304 to operate in a saturated state is given by VDD ≧ (voltage between source and drain of M303) + [(voltage between gate and source of M304) −V _TN ] + V _R301 + V _F1 (6). Here, V _R301 is a voltage applied across the resistor R301 and is given by (kTlnn) / q, and V _F1 is D3.
01 forward bias voltage, V _TN is NMOSFET
Is the threshold voltage of.

Here, in order to make the power supply voltage VDD as low as possible, the right side of the equation (6) is made as small as possible. That is, the minimum value of (the voltage between the source and drain of M303) can be set to | V _TP | from the ON condition of M303.
The minimum value of (gate-source voltage of M304) is M30
It can be set to V _TN from the ON condition of 4. as a result,
Formula (5) becomes VDD ≧ | V _TP | + V _R301 + V _F1 (7) The same applies to M305, and the saturation condition for minimizing the power supply voltage VDD is VDD ≧ V _TN + V _F2 (8). Normally, the value of | V _TP | is about 1 V and V _R301 is 30-
100 mV, V _F1 , and V _F2 are 0.5 to 0.7 V. Therefore, the minimum operating power supply voltage of the circuit of FIG.
It is about 1.8 V, and it can be seen that most of them are determined by the threshold value of the PMOSFET. In other words, the minimum operating power supply voltage of the circuit of FIG. 14 is substantially determined by the circuit configuration in which the gate and drain of M303 are connected. This is
The same applies to the circuit of FIG.

[0012]

The above-mentioned conventional analog MOSFET technology often uses a circuit configuration for connecting a gate and a drain. However, this circuit configuration makes it difficult to reduce the operating power supply voltage. There is. In addition, a circuit that avoids the configuration in which the gate and the drain are connected has a problem that it lacks high speed and versatility. An object of the present invention is to provide a semiconductor integrated circuit that can operate with a low power supply voltage without losing high speed operation and versatility.

[0013]

A first semiconductor integrated circuit according to the present invention has first and second transistors of opposite conductivity type, one ends of which are connected to a first power supply, respectively. One end of the transistor not connected to the first power supply, a control terminal of the second transistor, and one end of the second transistor not connected to the first power supply and the first The control terminals of the transistors are connected to each other.

In the second semiconductor integrated circuit of the present invention, the drains of the first and second first conductivity type MISFETs and the sources of the third and fourth second conductivity type MISFETs are connected to the first power supply. , The gate of the first MISFET is connected to the drain of the third MISFET, and the second MISFET
The gate of T is connected to the drain of the fourth MISFET, and the gate of the third MISFET is the first MISFET.
Of the third MISFET, the gate of the fourth MISFET is connected to the source of the second MISFET, and
Using the ET and the fourth MISFET as loads, the third MI
Outputs are obtained at the drain of the SFET and the drain of the fourth MISFET.

[0015]

The circuit disclosed in the first semiconductor integrated circuit of the present invention is a transistor load circuit used as a load of an amplifier.

One of the first and second transistors of the first and second conductivity types connected to the common power source (referred to as the first transistor) is output by common drain (or collector) connection. The terminal is the source (or emitter). The second transistor has a common source (emitter) connection and the output terminal is a drain (or collector). Since the control terminal and the output terminal of the first transistor are connected to the output terminal and the control terminal of the second transistor, respectively, the voltage V _{CO1 of the} control terminal with respect to the output terminal of the first transistor is It is equal to the voltage V _OC2 at the output terminal with respect to the control terminal of the transistor. Therefore, when the potential of the first power supply is VDD, the potential of the output terminal of the second transistor is VDD + (the potential of the control terminal with respect to the potential of the common terminal of the second transistor) + V _CO1
become. In a connection in which the control terminal and the output terminal of the second transistor are short-circuited (hereinafter referred to as resistance connection), the potential of the output terminal of the second transistor is VDD + (the potential of the control terminal with respect to the common terminal of the second transistor). _Therefore , when the second transistor provided with the connection of the present invention is used as a load transistor, the output operating voltage is V _CO1
Only rises. Therefore, even if the power supply voltage is VDD-V _CO1 , the semiconductor integrated circuit of the present invention can operate at the same operating voltage as the conventional semiconductor integrated circuit having the resistance-connected transistor load.

The circuit disclosed in the second semiconductor integrated circuit of the present invention is a transistor load circuit used as a load of a differential amplifier. In this case, the transistor load circuit of the first semiconductor integrated circuit (hereinafter referred to as the first invention) is provided for each gain transistor forming the input differential pair. First and third MISFETs of the present invention
Are load circuits corresponding to the first and second transistors of the first invention, and the second and fourth MISFETs are load circuits corresponding to the first and second transistors of the first invention, respectively. The operation of each load circuit is the same as that of the transistor load circuit of the first invention.

[0018]

Embodiments of the present invention will now be described with reference to the drawings. 1 is a circuit diagram of a current mirror circuit according to a first embodiment of the present invention. The NMOSFET M104 has a source grounded and constitutes a current source for setting the current value of the current mirror circuit, and has a gate bias voltage VB11 at its gate.
Is given. The source of the PMOSFET M103 is connected to the positive power supply VDD and the drain thereof is connected to the drain of M104. The drain of the NMOSFET M101 is VDD, the source thereof is the gate of M103, and the gates thereof are M104 and M10.
3 is connected to the common connection terminal of the drain. NMOS
The FET M102 is a current source for forming an N-channel source follower together with M101, and is connected between the source of M101 and the ground, and the gate thereof is connected to VB11. M105 is a PMOSFET, the source is connected to VDD, the gate is connected to the gate of M103 and the common connection point of M101 and M102, and the output current I11 is generated at the drain.

It will be described below that the circuit of FIG. 1 constitutes a current mirror circuit. PMOSFET M103 and M
Since the gates of 105 are commonly connected, M103 must operate in the saturation region for this circuit to operate as a current mirror circuit. The condition is (source-drain voltage of M103) ≧ (source-gate voltage of M103) − | V _TP │∴ (source-gate voltage of M103) − (source-drain voltage of M103) ≦ | V _TP | ∴ (gate-source voltage of M101) ≦ | V _TP | (9). On the other hand, as is clear from the condition for the M101 to be in the ON state (gate-source voltage) ≧ V _TN ,
It is possible to reduce the (gate-source voltage) to V _TN while maintaining the ON state of M101. Therefore, M1
By adjusting the size of 02 to adjust the drain current of M102, that is, the drain current of M101,
When the gate-source voltage of 101 is reduced to V _TN , the equation (9) becomes V _TN ≦ | V _TP | (10). Here, V _TN and V _TP are NMOSFE, respectively.
It is the threshold voltage of T, PMOSFET. Formula (10)
From the NMOSFET threshold voltage V _TN is PMOSF
It can be seen that if the absolute value of the threshold voltage of ET is less than or equal to | V _TP |, the circuit of FIG. 1 operates normally as a current mirror circuit. Strictly speaking, a weak inversion current flows in the MOSFET even if it is below the threshold voltage.
It is also possible to bias the gate-source voltage of 101 to a voltage lower than V _TN , and it is sufficiently possible to operate the circuit of FIG. 1 as a current mirror circuit by a normal CMOS process.

The current mirror circuit of FIG. 1 and a conventional current mirror.
Compared with the current circuit, in the conventional current mirror circuit
Is the gate of the transistor corresponding to M103 in FIG.
And the drain is connected. Therefore, that tran
The drain potential of the transistor is VDD + V_SG(V_SGIs the source
The gate voltage becomes <0). On the other hand, in the circuit of FIG.
Is the potential V of the drain with respect to the gate of M103_D3-V
_G3(V_D3, V_G3Is the ground potential, M1
(Representing the drain potential and gate potential of 03) is M10
The potential V of the gate with respect to the source of 1_G1-V_S1(V_G1, V
_S1Is the gate of M101 to the ground potential
Potential, which represents the source potential). Of M101
From ON condition to V_G1-V_S1≧ V_TN> 0. But
V _D3-V_G3≧ V_TN> 0. As a result,
The voltage between the source and drain of M103 of V_SG3 To
And drain potential V_D3The following equation holds for.

V _D3 = VDD + V _SG3 + (V _D3 −V _G3 ) ≧ VDD + V _SG3 + V _TN (11) Therefore, the drain of the transistor corresponding to M103 in the conventional current mirror circuit in which the gate and drain of M103 are connected. As compared with the potential VDD + V _SG , the drain potential of M103 in FIG. 1 becomes higher by at least V _TN .
Therefore, the minimum operating power supply voltage VDD _L can be lowered by V _TN .

FIG. 2 is a second embodiment of the present invention in which the current mirror circuit of FIG. 1 is reconfigured by the bipolar technique. B
101, B102, B104 are NPN bipolar transistors, and B103, B105 are PNP bipolar transistors. This embodiment also operates almost in the same way as the circuit of FIG. Unlike the case of the MOSFET technology, the base-collector junction of B103 is forward-biased, so that the diffusion capacitance is significantly increased and the operation speed is significantly reduced. However, there is no problem in terms of DC.

FIG. 3 is a circuit diagram of a bandgap reference voltage circuit according to the third embodiment of the present invention. NMOSFET M
301, M302, PMOSFET M303, M30
5, M307, NMOSFET M304, M306
Constitutes a current mirror circuit to which the present invention is applied, like the circuit of FIG. M302 is a current source that constitutes a source follower circuit together with M301, and VB31 is M3.
02 gate bias voltage. PMOSFET M
308 is a current source that constitutes a source follower circuit together with PMOSFET M309, and VB32 is M30.
8 gate bias voltage. Diode D301,
D302 and D303 are both junction diodes, the diode D301 is connected in the forward direction between the source of M304 and the ground terminal via the resistor 301, and the diode D302 is connected in the forward direction between the source of M306 and the ground terminal. And the diode D303 is connected to the resistor R302.
Is connected in the forward direction between the drain of M307 and the ground terminal. The connection between M306 and M309 is similar to the connection between M303 and M301, the gate of M306 is connected to the source of M309, and the drain of M306 is connected to the gate of M309. Similar to the conventional example of FIG. 14, D301 has a junction area n (> 1) times that of D302, and D303 has the same junction area as D301. Further, the resistor R302 is designed to have a resistance value m (> 1) times that of R301. In addition, M303, M305,
M307 has the same size, and M304 and M306 have the same size. The output voltage VO3 is within the operating power supply voltage range as shown in FIG.
Match 4 However, the operating power supply voltage VDD is
Similar to the circuit of, the condition for M304 to operate in the saturation region is given by the following equation.

[0024] VDD ≧ (the source-drain voltage of M303) + [(gate-source voltage of _{M304) -V TN] + V R301} + V F1 (12) Therefore, VDD in the case of equality of formula (12) Take the lowest value. Furthermore, in order to reduce the operating power supply voltage as much as possible, the gate-source voltage of M301 is | V _TP |
If the current value of the current source M302 is adjusted so that
The minimum value of the source-drain voltage for the 303 to operate in a saturated state is 0V. Also, the current value of the current source M308 is adjusted to set the gate-source voltage of M304 to V _TN.
Can be Therefore, Equation (12) becomes _{VDD ≧ 0 + 0 + V R301} + V F1 ∴ VDD ≧ V R301 + V F1 (13). Similarly, the following equation is obtained from the condition for M305 to operate in the saturation region.

VDD ≧ V _F2 (14) Compared with the conventional example of FIG. 14 (see equations (7) and (8)), in the circuit of the present invention, the power supply voltage VDD is changed by | V _TP | or V _TN. Can be lowered.

FIG. 4 is a circuit diagram of a differential amplifier according to the fourth embodiment of the present invention. In this embodiment, the NMOSFET
Circuit part consisting of M401, M402, PMOSFET M403 and NMOSFET M408, M40
9, the circuit portion consisting of PMOSFET M405 is the NMOSFET M101, M102, PM of FIG. 1, respectively.
It has the same configuration as the circuit portion including the OSFET M103. The NMOSFETs M404 and M406 form an input differential pair, the NMOSFET M407 is a current source, and the gate is connected to the bias voltage VB41. VB4
Reference numeral 2 is a gate bias voltage for the current sources M402 and M409. The circuit of FIG. 4 has inputs VI1, VI as a whole.
2. A differential amplifier having outputs VO41 and VO42 is configured, and the differential amplifier is functionally identical to the differential amplifier shown in FIG. 7 and has similar voltage gain and output amplitude characteristics. . On the other hand, with respect to the minimum operating voltage, it is possible to shift the gate-drain voltage of M403 and M405 in FIG. 4 by the maximum | V _TP |, so that it can be set to the same value as in the conventional example of FIG. However, for that purpose, V _TN ≈ | V _TP | is established, and M401 and M408 are set.
It is necessary to make the gate-source voltage of V _TN approximately equal to V _TN , but this may cause a reduction in high speed. The reason is that when the gate-source voltage is lowered, the transconductance of M401 and M408 becomes smaller, and as a result, M401 and M402 and M408 and M40 become smaller.
This is because the band of the source follower circuit composed of 9 becomes low. Since the voltage gain of the source follower circuit is almost 1x, if it has the same transconductance as other parts, it can generally operate at a higher speed in a wider band than other parts, but as in the present case, the transconductance is extremely high. If it is too small, the operating speed of the entire circuit will decrease. If so, lower the threshold voltage only M401, M408 source follower _{transistors, V TN (M401) = V} TN (M408) <| V TP | with a, and increases the current value of the M402, M409 M40
It is possible to increase the transconductance by increasing the gate-source voltage of M1 and M408, and prevent a decrease in the operating speed of the entire circuit. Where V _{TN (M401)} ,
V _{TN (} M408 ₎ is the threshold value of M401 and M408, respectively. As described above, the differential amplifier circuit of FIG.
It has the advantages of both the high speed of the conventional example and the low voltage operability of the conventional example of FIG. Further, even when the level shift stage is required as in the conventional example of FIG. 10, the circuit of FIG. 4 already has this function. If level shifting is not necessary, VO43 and VO44 shown in FIG. 4 may be output.

FIG. 5 is a block diagram of a ring oscillator type voltage controlled oscillator (VCO) according to a fifth embodiment of the present invention.
The voltage controlled oscillator of this embodiment is the differential amplifier OSC of FIG.
Are cascade-connected in a ring shape. PM
The OSFET M501 is an input transistor, the source is connected to the power supply VDD, and the control voltage VC is applied to the gate. The NMOSFET M502 is a load transistor whose gate and drain are connected. The output of M501 is the current source transistor M407 of the differential amplifier OSC.
Is applied to the gate bias input VB41 and the gate bias input VB42 of the current source transistors M402 and M409. The final stage outputs VO51 and VO52 of the cascaded differential amplifiers are the input V of the first stage differential amplifier.
These are input to I1 and VI2, respectively, and a ring-shaped connection is formed. The voltage-controlled oscillator needs to obtain an oscillation output in a wide range of frequencies by changing the control voltage VC. However, in this embodiment, when the control voltage VC changes and the circuit current changes, the current of M407 is changed. Since the increasing / decreasing direction of the load MOSFET and the increasing / decreasing direction of the current that can flow through the load MOSFETs M403 and M405 coincide with each other, the oscillation frequency can be controlled by the control voltage VC without a large change in the operating power supply voltage. Of course, VB41 and V in FIG.
Further stabilization can be achieved by controlling B42 separately.

Next, FIG. 6 is a circuit diagram of a differential amplifier circuit according to a sixth embodiment of the present invention. In this embodiment, an automatic adjustment circuit for the operating point of the source follower stage is added so that the circuit of FIG. 4 operates stably even when there is a large manufacturing variation in the threshold value of the MOSFET. Automatic adjustment circuit is NMOSFET M703 and NMOSFET M
704 connected in series, PMOSFET M705 and NM
Series connection with OSFET M706, PMOSFET
It is constituted by a series connection of M701 and NMOSFET M702, and an operational amplifier OP. M705
The connection between M 703 and M 703 is similar to the connection between M 405 and M 408, the gate of M 703 is connected to the drain of M 705 and the gate of M 705 is connected to the source of M 703. The size of M703 is designed the same as that of M401 and M408, and the size of M704 is M402 and M40.
Designed the same as 9. Therefore, M408, M
The source follower composed of 409 has the same configuration as the circuit composed of M703 and M704. Furthermore, M702, M7
06 is designed to have the same size as M407. Therefore, for the same gate bias voltage VB41, M
The current flowing through each of 705 and M701 is M403 or M40 when the two differential inputs VI1 and VI2 are equal.
5 times the current flowing through 5. On the other hand, M701, M70
The (gate width) / (gate length) ratio of 5 is designed to be twice the ratio of M403 (= the ratio of M405). Therefore, the gate voltage of M705 with respect to the same gate bias voltage VB41, that is, the potential of the node 702 with respect to VDD is the gate voltage of M405 when VI1 = VI2 holds, that is, the output V with respect to VDD.
It becomes equal to the potential of O42. Similarly, the potential of the gate of M701, that is, the potential of the node 701 is VI1 and VI2.
The potential VO41 of the gate of M403 when they are equal
Is equal to Therefore, the two inputs of the operational amplifier OP become equal to the outputs VO41 and VO42 of the differential amplifier when VI1 and VI2 are equal. Operational amplifier OP
The two inputs should be equal if there is no manufacturing variation in the thresholds of the transistors that make up the differential amplifier. However, due to manufacturing variations,
The node 701 and the node 702 do not have the same potential. The operational amplifier OP includes current sources M402, M409 in the source follower stage so that the potentials of the nodes 701, 702 are equal.
The current value of M704 is controlled. In this way, FIG.
The gate bias voltages of the load MOSFETs M403 and M405 in the circuit of FIG.
It is possible to achieve a low voltage while completely matching the gate bias voltage of 405 and maintaining the voltage gain and high speed.

[0029]

As described above, according to the present invention, the output terminal of the first transistor forming the load of the semiconductor integrated circuit is the control terminal of the second transistor having the conductivity type opposite to that of the first transistor. The output terminal of the second transistor is connected to the control terminal of the first transistor, and the second transistor is connected to the output terminal of the second transistor and the control voltage at a current value that produces a predetermined voltage. The current driving has the effect of reducing the operating power supply voltage without losing the high speed and versatility of the operation of the semiconductor integrated circuit.

[Brief description of drawings]

FIG. 1 is a current mirror circuit according to a first embodiment of the present invention.

FIG. 2 is a second embodiment of the present invention in which the current mirror circuit of FIG. 1 is constructed by bipolar technology.

FIG. 3 is a bandgap reference voltage circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of a differential amplifier according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram of a ring oscillator type voltage controlled oscillator according to a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram of a differential amplifier circuit according to a sixth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a first example of a conventional high-speed differential amplifier.

FIG. 8 is a circuit diagram of a differential amplifier cascade-connected in a second example of a conventional differential amplifier.

FIG. 9 is a circuit diagram showing a third example of a conventional differential amplifier.

FIG. 10 is a circuit diagram showing a fourth example of a conventional differential amplifier.

FIG. 11 is a circuit diagram showing a fifth example of a conventional differential amplifier.

FIG. 12 is a circuit diagram showing a sixth example of a conventional differential amplifier.

13 is a circuit diagram in which the differential amplifier of FIG. 12 is reconfigured by MOSFET technology.

FIG. 14 is a circuit diagram of a conventional bandgap reference voltage circuit.

[Explanation of symbols]

VB11 gate bias voltage (base bias voltage) I11 current output M101 to M105 MOSFET B101 to B105 bipolar transistor VB31, VB32 gate bias voltage VO3 output M301 to M309 MOSFET R301, R302 resistance D301, D302, D303 junction diode VB41, VB42 gate bias voltage VI1, VI2 Differential input VO41, VO42 Differential output VO43, VO44 Differential output OSC Differential amplifier VC control voltage M501, M502 MOSFET OP operational amplifier 701, 702 Nodes M701-M706 MOSFET

Claims (7)

[Claims] 1. A first power supply, which has first and second transistors of opposite conductivity type each having one end connected to a first power supply and which is not connected to the first power supply of the first transistor. One end and a control terminal of the second transistor are connected, and one end of the second transistor that is not connected to the first power supply is connected to a control terminal of the first transistor, respectively. Semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the first transistor is a first first conductivity type MISFET and the second transistor is a first second conductivity type MISFET. 3. The absolute value of the threshold voltage of the first first conductivity type MISFET and the absolute value of the threshold voltage of the first second conductivity type MISFET are different from each other. Semiconductor integrated circuit. 4. The semiconductor integrated circuit according to claim 2, wherein a terminal connected to a control terminal of the first second conductivity type MISFET of the first first conductivity type MISFET is a first current source. Connected to the first second conductivity type MI
A second second conductivity type MISF having a terminal connected to a control terminal of the first first conductivity type MISFET of the SFET is connected to a second current source and one end of which is connected to the first power source.
ET, the gate of the second second conductivity type MISFET is connected to the gate of the first second conductivity type MISFET, and the output current is equal to the second second conductivity type MISFET.
A semiconductor integrated circuit characterized by being obtained from one end of the. 5. The absolute value of the threshold voltage of the first first conductivity type MISFET and the first and second second conductivity type MISFs.
5. The semiconductor integrated circuit according to claim 4, wherein the absolute value of the threshold voltage of ET is different. 6. A first and second first conductivity type MISFE.
T drain and third and fourth second conductivity type MISFE
The source of T is connected to a first power supply, and the first MI
The gate of the SFET is connected to the drain of the third MISFET, the gate of the second MISFET is connected to the drain of the fourth MISFET, and the third MFET is connected.
The gate of the ISFET is connected to the source of the first MISFET, the gate of the fourth MISFET is connected to the source of the second MISFET, and the third MISFET is connected.
With the SFET and the fourth MISFET as loads, the drain of the third MISFET and the fourth MISF
A semiconductor integrated circuit characterized in that an output is obtained at the drain of ET. 7. The semiconductor integrated circuit according to claim 6, wherein the first and second first conductivity type MISFETs are provided.
7. The semiconductor integrated circuit according to claim 6, wherein the absolute value of the threshold voltage of is smaller than the absolute value of the threshold voltage of the third and fourth second conductivity type MISFETs.