JP2698342B2 - Clamp circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clamp circuit used on the input side of a buffer circuit composed of, for example, an FET. SUMMARY OF THE INVENTION The present invention relates to the above-described clamped element by setting the clamp voltage of the FET so that the value of the channel potential of the FET forming the clamped element becomes a constant value which is not influenced by the manufacturing conditions of the FET. The clamp circuit prevents instability of the circuit operation due to fluctuation of Vth (threshold voltage) of the FET at a later stage. [Prior Art] For example, a clamp circuit as shown in FIG. 5 has been proposed. Signal source formed of the signal V _in in FIG. 51 is connected to one end of the clamp capacitor (52), the other end of the capacitor (52) is connected to the inverting input of the differential amplifier (53). A DC voltage source (54) for forming a clamp voltage is connected to the non-inverting input of the amplifier (53). The output of this differential amplifier (53) is a diode-structured FET (5
5) is connected to the other end of the capacitor (52). Further, the other end of the capacitor (52) is connected to the gate of the source follower FET (56) constituting the buffer circuit, and the output terminal (57) is led out of the source of the FET (56). In addition, (58) is a power supply terminal of the power supply _VDD , and (59) is an FET constituting a constant current source. In this circuit, when the potential at the other end of the capacitor (52) becomes lower than the potential of the voltage source (54), the output potential of the differential amplifier (53) increases, the diode (55) conducts, and the The potential at the other end is increased. As a result, the lowest value (bottom) of the signal is clamped to a desired set potential, and, for example, sync tip clamping of the video signal is performed. By the way, in this circuit, when the element constituting the buffer circuit is a so-called bipolar transistor,
Regardless of the process used, the value of the forward drop voltage V _BE between the base and the emitter is almost constant. On the other hand, when an FET is used as shown in the figure, the gate voltage (threshold voltage) V _th required to cause strong inversion in the FET
Is extremely large, and ±
It allows about 0.2V. That is, V _th is a flat band voltage V
_The energy band bending (2φ _FP : φ _EP is the Fermi potential of the substrate), which is a necessary condition for strong inversion, is added to _FB , and charge is further added to the depletion region. K _S is a semiconductor dielectric constant, epsilon ₀ is the vacuum dielectric constant, q is the elementary charge, N _A that is required to produce the impurity density) of the acceptor Voltage C _O is the sum of the oxide film capacity per unit area). Where V _FB is Here, φ _MS is the work relation difference between metal and semiconductor Q _SS is the interface charge density per unit area ρ is the space charge density x ₀ is the oxide film thickness. Therefore, in the general process, with varying amounts of Q _SS by ion implantation or the like V _FB
To control the value of V _th . But actually Q
Due to the variation in _SS, a variation of about ± 0.2 V was generated as the value of _Vth . When the variation of V _th is large, the gate
If the source-to-source potential difference V _GS is kept constant, it is extremely difficult to keep the FET potential constant.As a result, the drain current _ID fluctuates. There is a drawback that the bias current of the amplifier fluctuates and the characteristics such as the frequency characteristics fluctuate greatly. That relative equation (1), and the gate voltage V _G,
Relationship between the interface potential φ _S of when you are depleted It is expressed as Accordingly, when an arbitrary voltage is applied to the gate, the variation Δφ _S of the interface potential from the interface potential at V _th is given by the following equation. By the way, in the case of a normal MOS process, the cause of the fluctuation of V _th is that at least one of V _FB , φ _FP , N _A , and _{CO in} the equation (1) fluctuates. Therefore if the gate voltage V _G constant, the variation varying such V _th occurs,
In order to satisfy the equation (4), the interface potential Δφ _S at the time of depletion must be changed. If This means that the gate voltage V _G is constant, the interface potential when depleted by the V _th varies means that varies. Considering the saturation region first, in the saturation region of the FET, the current equation is, for example, “Physics and Tec by ASGrove”.
From Chapter 11 of "hnology of Semiconductor Devices", given by: Where W is the channel width L is the channel length μn is the electron mobility V _{D sat} is the drain voltage when the saturation region starts
V _D where V _{D sat} is expressed as V _{D sat} = φ _S −2φ _FP (6), and the above-mentioned expressions (3) and (6) are substituted into expression (5) to obtain the drain current _ID . Expressed using potential, Becomes Therefore, if the change is interfacial potential phi _S when depleted, the drain current I _D is changed. Next, considering the linear region, the current expression in the linear region is obtained by replacing V _{D sat} with the drain voltage V _D in Expression (5) from the above document. Then, by substituting the above equation (3) into this equation, and expressing the drain current _ID using the potential, Next, if the interface potential phi _S changes when depleted as with the saturation region, the drain current I _D is changed. Furthermore, when the drain voltage V _D in the linear region is very small, i.e. considering the time of V _D «2Fai _FP, current type at this time is given by the following equation from the above literature. Then, when the above equation (3) is substituted into this equation, Expressed as, if interfacial potential phi _S changes when depleted in this equation, the drain current I _D is changed. Therefore, when such a FET is used as a buffer circuit or an inverting amplifier in the subsequent stage to form a clamp circuit,
Due to the fluctuation of the drain current _ID of the FET, the linearity and frequency characteristics of the circuit fluctuate, and it becomes impossible to obtain stable characteristics. In particular, in the case of a circuit whose current value is determined by the clamp potential, such as an inverting amplifier circuit shown by (60) and (61) in FIG. 4, if V _th of the FET (60) varies, The value of the current flowing in the circuit is undefined and becomes unstable, resulting in unstable power consumption, which is not preferable in circuit design. [Problems to be Solved by the Invention] For example, when a FET constituting a buffer circuit is provided at the previous stage of a circuit using an FET as a circuit element and a clamp circuit is formed by this FET, in the conventional method, the V _{Since the} channel potential fluctuates due to the fluctuation of _th , there is a problem that the circuit operation is not stabilized. [Means for Solving the Problems] In order to solve the above problems, the present invention provides a clap circuit including the following means. That is, the clamped element is provided corresponding to the clamped element whose channel potential can be controlled by the gate voltage applied to the gate, and is formed by the same process as the clamped element and having the same channel length. A detection element for approximately detecting a channel potential of the element, and a comparison type operation for comparing a potential corresponding to a channel potential of the clamped element taken out from the detection element with a set voltage corresponding to a clamp potential. An amplifier circuit, wherein an output voltage of the comparison-type operational amplifier circuit is fed back to a gate of the detection element so that a potential corresponding to the channel potential is equal to the set voltage, and corresponds to the channel potential. Comparison type when the potential to be set and the set voltage are equal By clamping the gate voltage applied to the clamped element by using the output voltage of the operational amplifier circuit, a variation in characteristics due to manufacturing conditions of the clamped element is compensated for. provide. [Operation] According to this circuit, the clamp voltage for removing the fluctuation of the potential of the element at the subsequent stage is supplied, so that the current value of the element becomes stable, and the circuit characteristics such as the frequency characteristics can be stabilized. . [Embodiment] In FIG. 1, (1) is a voltage / potential conversion circuit, and a potential corresponding to the potential from this circuit (1) is supplied to a comparison type operational amplifier circuit (2). The set voltage from the voltage source (3) is supplied to the comparison type operational amplifier circuit (2). The output voltage of the comparison type operational amplifier circuit (2) is supplied to the conversion circuit (1). The output of the voltage / potential conversion circuit (1) supplies a potential representing the channel potential of the FET with respect to the input voltage at that time, and the voltage source (3) supplies a set voltage for providing a reference value of the channel potential. Therefore, the comparison type operational amplifier circuit (2) compares the two and, if there is a difference, feeds back the difference to the circuit (1) as a correction value. When the difference disappears, there is no change in the voltage of the input to the circuit (1), and the point is stabilized at that point. Therefore, the output voltage of the comparison type operational amplifier circuit (2) at that time is a voltage for keeping the channel potential constant. This output voltage is supplied to, for example, the non-inverting input of the differential amplifier (53), so that the
The current flowing through the FET (56) is stabilized, and fluctuations in circuit characteristics and the like are reduced. FIG. 2 shows an example of a specific circuit. In the figure, the voltage / potential conversion circuit (1) is constituted by an FET (10), the drain of which is connected to a power supply _VDD , the source is grounded through an FET (11) constituting a current source, and The source of (11) is a P-type impedance conversion one side of the comparison type operational amplifier circuit (2).
Connected to the gate of FET (20). The voltage source (3) is formed by providing resistors (30) and (31) such as polysilicon between the power supply _VDD and the ground and dividing the resistors. Here, the absolute value of the resistance value of the polysilicon changes, but the resistance division ratio hardly changes, so that an extremely stable set voltage can be obtained. The middle point of connection between the resistors (30) and (31) is connected to the gate of the other P-type FET (21) for impedance conversion which constitutes the comparison type operational amplifier circuit (2). Further, the drains of the FETs (20) and (21) are grounded, and the sources are respectively connected to the power supply _VDD through the constant current source FETs (22) and (23). P-type FET that is differentially connected
(24) Connect to the gates of (25). This FET
The sources of (24) and (25) are connected to the power supply V _DD through a constant current source FET (26), and the drains are grounded through load current sources (27) and (28) in a current mirror configuration.
The drain of the FET (24) is connected to the gate of the FET (10). The connection line to the gate of the FET (10) is connected to the non-inverting input of the differential amplifier (53). Here, the configuration of the FETs (10) and (11) is as shown in FIG. 3A, and when the structure is as shown in the middle part of the figure, the potential becomes as shown in the lower part of the figure. Thus V _in potential formed against (white portion)
_Vout having the same potential as that of _Vout can be obtained. In addition, FET (11)
The allowed to discharge a small current from the V _out, for the purpose of preventing the V _out than the potential of V _in the influence of noise or the like is high, essentially without as shown in Figure B May be. Alternatively, a resistor (12) having a high resistance value may be connected as shown in FIG. That is, in the above-mentioned circuit, the FET (10) is designed so that an extremely small current flows. FET in this state
Channel can be considered to be just after the depletion state has just changed to the strong inversion state. On the other hand, FET at this time
It can be considered that the source is simply in a reverse bias state with respect to the substrate. As described in Chapter 10 of the above-mentioned document, the source voltage V _S is V _S = φ _S −2φ _FP. 11) Although here phi _FP is somewhat varies depending on the conditions of the process, is much larger towards the V _FB to influence the variation of the V _th, in practice variations of phi _FP is negligible. Thus the potential phi _S and the detection voltage in the circuit described above is in the proportional function, it is possible to detect a voltage corresponding to the potential. The relational expression between the interface potential and the gate voltage when the surface is depleted is It is expressed as Wherein variations in V _FB, N _A, C _O in a normal process are many, when constant Therefore V _G phi _S fluctuates. Therefore, to cancel changing the gate voltage V _G by a clamp circuit to change due to V _FB or the like in the above circuit is connected to the gate of the FET, can be kept constant phi _S. Considering, for example, the saturation region, the relational expression between the potential and the current is expressed by the above-mentioned expression (7). Comparing this expression with expression (5) using the gate voltage, the maximum expression of these expressions is obtained. The difference is that the current formula using potential is V
_{The FB} term is not included. This is the same for the linear region. Therefore, V _FB can be expressed by the equation expressing the current using the potential.
The fact that there is no term means that even if V _th fluctuates, the FET current does not change if the surface potential at the time of depletion is kept constant. Therefore, in the above-described circuit, by setting the voltage for making the potential constant as the reference voltage of the clamp, the current flowing through the FET (56) at the clamp potential can be made constant, and the circuit characteristics and the like can be stabilized. In addition, FET (10)
And (56) are formed in the same process and have at least the same channel length L. By removing the fluctuation of the potential of the element, the drain current can be stabilized, and the frequency characteristics and linearity of the circuit can be stabilized. FIG. 4 shows an example in which the post-stage circuit is applied to an inverting amplifier circuit. The other end of a clamp capacitor (52) is connected to the gate of an inverting amplifier FET (60). Also in this circuit, the potential of the FET (60) at the clamp potential is stabilized, and linearity, frequency characteristics, and the like can be stabilized. This circuit is not limited to the bottom clamp, and the same operation and effect can be obtained by applying it to another type of clamp circuit. This circuit also has the effect of stabilizing the circuit current in a circuit configuration in which a current flows by the clamp voltage. [Effects of the Invention] According to the present invention, since a clamp voltage for removing a fluctuation in the potential of a subsequent element is supplied, the current value of the element is stabilized, and the circuit characteristics such as frequency characteristics are stabilized. Is now available.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of one example of the present invention, FIGS. 2 and 3 are diagrams for explaining the same, FIG. 4 is a block diagram of another example, and FIG. FIG. 3 is a diagram for explaining the technique of FIG. (1) is a voltage / potential conversion circuit, (2) is a comparison type operational amplifier circuit, (3) is a voltage generation circuit, (53) is a differential amplifier, and (56) is an FET.

Claims (1)

(57) [Claims] The device is provided corresponding to a device to be clamped whose channel potential can be controlled by a gate voltage applied to the gate, and is formed by the same process as the device to be clamped and has the same channel length. A detection element for approximately detecting a channel potential, and a comparison-type operational amplifier circuit for comparing a potential corresponding to a channel potential of the clamped element extracted from the detection element with a set voltage corresponding to a clamp potential. The output voltage of the comparison type operational amplifier circuit is fed back to the gate of the element for detection so that the potential corresponding to the channel potential and the set voltage are equal,
The gate voltage applied to the clamped element is clamped by using the output voltage of the comparison type operational amplifier circuit when the potential corresponding to the channel potential becomes equal to the set voltage. A clamp circuit in which variations in characteristics due to manufacturing conditions of a clamp element have been compensated.