JP2953432B2 - Clamp voltage generation method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clamp circuit used on the input side of a buffer circuit composed of, for example, an FET, and more particularly to a clamp voltage generation method. According to the present invention, the potential is approximated, and the clamp voltage is corrected so that the value becomes constant, thereby making it possible to eliminate fluctuations in _Vth of a _subsequent FET. [0003] For example, a clamp circuit as shown in FIG. 5 has been proposed. Signal source 51 which is formed of the signal V _in is connected to one end of the clamp capacitor 52 in FIG., The other end of the capacitor 52 is connected to the inverting input of the differential amplifier 53. A DC voltage source 54 for forming a clamp voltage is connected to the non-inverting input of the amplifier 53. The output of the differential amplifier 53 is connected to the other end of the capacitor 52 through the FET 55 having a diode configuration. The other end of the capacitor 52 is connected to the gate of a source follower FET 56 constituting a buffer circuit, and an output terminal 57 is derived from the source of the FET 56. Reference numeral 58 denotes a power supply terminal of the power supply _VDD , and reference numeral 59 denotes an FET constituting a constant current source. In this circuit, when the potential at the other end of the capacitor 52 becomes lower than the potential of the voltage source 54, the differential amplifier 5
3, the potential of the other end of the capacitor 52 is increased. As a result, the lowest value (bottom) of the signal is clamped to a desired set potential, and, for example, sync tip clamping of the video signal is performed. In this circuit, when the element constituting the buffer circuit is a so-called bipolar transistor, the value of the forward drop voltage V _BE between the base and the emitter is substantially constant regardless of the process used. . On the other hand, when an FET is used as shown in the figure, the variation of the gate voltage (threshold voltage) _Vth required to cause strong inversion in the FET is extremely large, and a general C-MOS process is used. And about ± 0.2 V is allowed. [0008] [0009] Where V _FB is: Is represented by Therefore, in the general process, with varying amounts of Q _SS by ion implantation or the like V
The value of V _th is controlled by changing _FB . However, in practice, the variation of Q _SS causes a variation of about ± 0.2 V in the value of _Vth . When the variation of V _th is large,
With the gate-source potential difference V _GS kept constant, F
It is extremely difficult to keep the potential of ET constant, and as a result, the drain current _ID fluctuates. For example, the current value when a constant current source is used and the bias current of an inverting amplifier are fluctuated. However, there is a drawback that characteristics such as the above-mentioned characteristics fluctuate greatly. Namely relative expression 1 described above, the gate voltage V _G, the relational expression between the interface potential phi _S when depleted, the [0013] Equation 3] It is expressed as Therefore, when an arbitrary voltage is applied to the gate, the variation Δφ _S of the interface potential from the interface potential at V _th is given by the following equation. [0014] By the way, in the case of a normal MOS process, V _th
Is caused by a change in at least one of V _FB , φ _FP , N _A , and C _{0 in equation} (1). Therefore if the gate voltage V _G constant, the variation varying such V _th occurs, In order to establish the equation (4) is the interface potential [Delta] [phi _S when depleted is forced to change You won't get it. [0016] This means that if the gate voltage V _G is constant, which means that the interface potential when depleted by the V _th varies varies. Therefore, considering the saturation region, the current equation in the saturation region of the FET can be expressed by, for example, the reference “ASGrove, Ph.
From Chapter 11 of "ysics and Technology of Semiconductor Devices", it is given by: Here, W is the channel width L, the channel length μn is the electron mobility V _{D sat, the} electron mobility V _{D sat} is the drain voltage V _{D at the} start of the saturation region, where V _{D sat} is: V _{D sat} = φ _S − expressed as 2 [phi _FP, equation (5) to the number of above 3, expressed using the potential of the drain current I _D by substituting equation (6), [0020] equation 7] Becomes Therefore, if the interface potential φ _S at the time of depletion changes, the drain current _ID changes. Next, considering the linear region, the current expression in the linear region is obtained by replacing V _{D sat} with the drain voltage V _D in Expression 5 from the above-mentioned document. Then, by substituting the above equation (3) into this equation, and expressing the drain current _ID using a potential, the following equation is obtained. Next, if the interface potential phi _S changes when depleted as with the saturation region, the drain current I _D is changed. Further, in the linear region, the drain voltage V _D
Is very small, that is, when V _D ≪2φ _FP , the current equation at this time can be considered by the following equation from the above-mentioned literature. [Equation 9] Then, when the above equation (3) is substituted into this equation, the following equation is obtained. In this equation, if the interface potential φ _S at the time of depletion changes, the drain current _ID changes. Therefore, when such a FET is used as a buffer circuit or an inverting amplifier in a subsequent stage to constitute a clamp circuit, the linearity and frequency characteristics of the circuit fluctuate due to the fluctuation of the drain current _ID of the FET, and the circuit becomes stable. Characteristics cannot be obtained. In particular, in the case of a circuit in which the current value is determined by the clamp potential, V
_The current value changes due to the fluctuation of _th, the current value of the circuit becomes unstable, and the power consumption becomes unstable, which is not preferable in circuit design. [0027] For example, in a clamp circuit using an FET for an element at the subsequent stage, the fluctuation of _Vth of the element is large, and the channel potential fluctuates due to this, so that the circuit operation is not stabilized. There was a point. [0028] In order to solve the above problems, the present invention provides a clamp voltage generation circuit having the following means. That is, FETs constituting the buffer circuit
A method of generating a clamp voltage to be supplied to the gate of a (field effect transistor), the method comprising: estimating a channel potential of an FET constituting the buffer circuit by using another FET formed by the same process as the FET. The voltage corresponding to the channel potential of
ET is detected from the source, the detected voltage is compared with a predetermined set voltage, the difference voltage is fed back to the gate of the another FET, and the another FET when the difference voltage becomes zero A method for generating a clamp voltage, wherein a voltage applied to the gate of the buffer circuit is a clamp voltage applied to the gate of the FET constituting the buffer circuit. According to this circuit, the clamp voltage for removing the fluctuation of the potential of the subsequent element is supplied.
The current value of the element becomes stable, and circuit characteristics such as frequency characteristics can be stabilized. FIG. 1 shows a voltage / potential conversion circuit 1, which supplies a potential corresponding to the potential from the circuit 1 to a comparison circuit 2. The set voltage from the voltage source 3 is supplied to the comparison circuit 2. The output voltage of the comparison circuit 2 is supplied to the conversion circuit 1. Further, in this circuit, feedback control is performed so that the potential according to the potential from the circuit 1 becomes equal to the set voltage from the voltage source 3. Thereby, the output voltage of the comparison circuit 2 becomes a voltage for correcting the potential to a constant value. The output voltage is, for example, the differential amplifier 5
By supplying the current to the non-inverting input 3, the current flowing through the FET 56 at the clamp potential is stabilized, and fluctuations in circuit characteristics and the like are reduced. FIG. 2 shows an example of a concrete circuit. In the figure, the voltage / potential conversion circuit 1 is constituted by an FET 10, the drain of which is connected to a power supply V _DD ,
The source is grounded through the FET 11 constituting the current source, and the source of the FET 11 is connected to the gate of one P-type FET 20 for impedance conversion constituting the comparison circuit 2. The voltage source 3 is formed by providing resistors 30 and 31 of polysilicon or the like between the power supply V _DD and the ground and dividing the resistors. Here, since the absolute value of the resistance value of the polysilicon changes, but the resistance division ratio hardly changes, an extremely stable set voltage can be obtained. The midpoint of connection between the resistors 30 and 31 is connected to the gate of the other P-type FET 21 for impedance conversion which constitutes the comparison circuit 2. The drains of the FETs 20 and 21 are grounded, and the sources are FETs 22 and 23 for a constant current source, respectively.
Is connected to the power supply V _DD through, of differentially connected P-type these sources constitute a comparator circuit 2 FET2
4, 25, respectively. This FET2
Sources 4 and 25 are connected to a power supply V _DD through a constant current source FET 26, drains are grounded through current mirror load current sources 27 and 28, and
The drain of 24 is connected to the gate of FET10. The connection line to the gate of the FET 10 is connected to the non-inverting input of the differential amplifier 53. Here, the configuration of the FETs 10 and 11 is as shown in FIG. 3A, and when the structure is as shown in the middle part of the figure, the potential becomes as shown in the lower part of the figure. Therefore it is possible to obtain V _out of _the same potential as V _in potential formed against (white portion). The FET 11 discharges a very small current from _Vout ,
This is for preventing V _out from becoming higher than the potential of V _in due to the influence of noise or the like. Essentially, it may not be provided as shown in FIG. Alternatively, a resistor 12 having a high resistance value may be connected as shown in FIG. That is, in the above-described circuit, the FET 10
Is designed so that an extremely small current flows. In this state, it can be considered that the channel of the FET has just changed from the depleted state to the strong inversion state. On the other hand, it can be considered that the source of the FET at this time is simply in a reverse bias state with respect to the substrate.
As described in the section, the source voltage V _S is expressed as follows: V _S = φ _S −2φ _FP Here, although there is some variation in φ _FP depending on the process conditions, V _FB has a much larger effect on the variation in V _th , and the variation in φ _FP can be ignored in practice. Therefore, in the circuit described above, the potential φ
_S and the detection voltage are in a proportional function, and a voltage corresponding to the potential can be detected. The relational expression between the interface potential and the gate voltage when the surface is depleted is as follows: It is expressed as Here, in a normal process, V _FB , N _A ,
Variation of C ₀ is large and when the constant Therefore V _G phi _S fluctuates. Therefore a change due to V _FB or the like in the above circuit to cancel by connecting V _G, phi
_S can be constant. Considering, for example, the saturation region, the relational expression between the potential and the current is represented by the above-mentioned equation (7). Comparing this equation with equation (5) using the gate voltage,
The biggest difference between the two equations is that the current equation using the potential does not include the term of V _FB . This is the same for the linear region. Therefore, the fact that there is no V _FB term in the equation expressing the current using the potential means that even if V _th fluctuates, if the surface potential at the time of depletion is kept constant, the current of the FET changes. Will not do. Therefore, in the above-described circuit, by setting the voltage for making the potential constant as the reference voltage of the clamp, the current flowing through the FET 56 at the clamp potential can be made constant, and the circuit characteristics and the like can be stabilized. The FETs 10 and 56 are formed by the same process and have at least the same channel length L. By thus removing the fluctuation of the potential of the element, the drain current can be stabilized, and the frequency characteristics and linearity of the circuit can be stabilized. FIG. 4 shows an example in which the subsequent circuit is applied to an inverting amplifier circuit. The other end of the clamp capacitor 52 is connected to the gate of an inverting amplifier FET 60. Also in this circuit, the potential of the FET 60 at the clamp potential is stabilized, and linearity, frequency characteristics, and the like can be stabilized. This circuit is not limited to the bottom clamp.
Similar effects can be obtained by applying the present invention to other types of clamp circuits. This circuit also has the effect of stabilizing the circuit current in a circuit configuration in which a current flows by the clamp voltage. According to the present invention, since a clamp voltage for removing the fluctuation of the potential of the element at the subsequent stage is supplied, the current value of the element becomes stable, and the circuit characteristics such as the frequency characteristic become stable. You can now.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram of an example of the present invention. FIG. 2 is a diagram for explaining this. FIG. 3 is a diagram for explaining this. FIG. 4 is a configuration diagram of another example. FIG. 5 is a diagram for explaining a conventional technique. [Description of Signs] 1 voltage / potential conversion circuit, 2 ‥‥ comparison circuit,
3 ‥‥ voltage generation circuit, 53 ‥‥ differential amplifier, 56 ‥‥ F
ET

Claims (1)

(57) [Claims] A clamp voltage generating method for generating a clamp voltage to be supplied to a gate of an FET (field effect transistor) constituting a buffer circuit, the method comprising the same process as the FET for estimating a channel potential of the FET constituting the buffer circuit. Detecting a voltage corresponding to the channel potential of another FET formed from the source of the FET, comparing the detected voltage with a predetermined set voltage, and feeding back the difference voltage to the gate of the another FET. The voltage applied to the gate of the another FET when the differential voltage becomes zero is determined by the FET constituting the buffer circuit.
Clamp voltage generation method as a clamp voltage to be applied to the gate of FIG.