JP4543193B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a reference voltage source configured on an integrated circuit using a semiconductor element that flows a diffusion current. More particularly, the present invention relates to a reference voltage source that is stable against fluctuations in power supply voltage, a PTAT reference voltage source that generates a voltage proportional to absolute temperature, and the use of this type of reference voltage source.

  A Proportional To Absolute Temperature (PTAT) reference voltage source that is proportional to absolute temperature is an important analog circuit that is required when a temperature sensor or a band gap reference voltage source is realized on an integrated circuit. By the way, as a PTAT reference voltage source, there is Patent Document 1 as a semiconductor device using a MOSFET that operates in a weak inversion state. Patent Document 1 shows a PTAT reference voltage source in which MOSFETs operated in a saturated state are connected by connecting a gate terminal and a drain terminal of a MOSFET operating in a weak inversion region to be diode-connected. In the PTAT reference voltage source of Patent Document 1, the PTAT reference voltage is proportional to a constant determined by the absolute temperature and the shape of the MOSFET, and exhibits a characteristic inversely proportional to the slope coefficient n in the exponential operation state.

  However, with the recent demand for lowering the power supply voltage of analog circuits, a PTAT reference voltage source driven by a low power supply voltage, in which the reference voltage is not affected by the manufacturing parameters of the integrated circuit, is required. In the diode-connected MOSFET in which the gate terminal and the drain terminal are connected as shown in Patent Document 1, the gate voltage also changes as the drain voltage changes, so that the operating state of the MOSFET changes depending on the drain voltage. In particular, in a low threshold MOSFET in a recent integrated circuit, the setting range of the drain voltage is remarkably limited. In addition, the slope coefficient n in the exponential operation state is a parameter that varies depending on the manufacturing parameters of the integrated circuit and the operation state of the MOSFET, and degrades the characteristics of the reference voltage and the reliability of the set voltage at the time of design.

Japanese Published Patent Publication No. 55-57920

  The driving range of MOSFETs is further narrowed due to a decrease in threshold voltage in recent miniaturization processes, and it operates from a low power supply voltage of 0.5 V or less under a general-purpose process and generates a stable voltage against fluctuations in power supply voltage. There is no PTAT reference voltage source to perform. For this reason, an on-chip PTAT circuit that can be driven by a weak and unstable power source such as a solar cell cannot be realized. In addition, when a current source is required in series as an external circuit, the minimum operating power supply voltage of the circuit is further increased. Further, the deterioration due to the variation of the slope coefficient n in the exponential operation state becomes a factor of reducing the reliability of the set voltage of the reference voltage source.

  Therefore, in the present invention, a reference voltage that can be driven with a low power supply voltage and is stable with respect to fluctuations in the power supply voltage is generated, and the temperature coefficient of the reference voltage is less affected by parameter fluctuations in the manufacturing process. An object of the present invention is to provide a semiconductor device for generating a reference voltage that can be accurately designed on an integrated circuit according to the shape of a semiconductor element that operates with a diffusion current.

A semiconductor device comprising a first lateral bipolar transistor and a second lateral bipolar transistor, wherein a collector terminal of the first lateral bipolar transistor and an emitter terminal of the second lateral bipolar transistor are connected, and the first A terminal between the collector terminal of one lateral bipolar transistor and the emitter terminal of the second lateral bipolar transistor is an output terminal, the emitter terminal of the first lateral bipolar transistor is a reference potential, and the second lateral bipolar transistor is A predetermined supply voltage is applied to the collector terminal of the first lateral bipolar transistor, the base terminal of the first lateral bipolar transistor and the base terminal of the second lateral bipolar transistor are connected, and the first lateral bipolar transistor is connected. Between the base terminal of the first lateral bipolar transistor and the base terminal of the second lateral bipolar transistor is a first base terminal, and the first lateral bipolar transistor and the second lateral bipolar transistor are lateral bipolar transistors having the same structure. And the first base terminal is applied with a voltage in a range where the emitter side pn junction of the first lateral bipolar transistor is slightly forward biased to an operation region reversely biased, When the first and second lateral bipolar transistors are npn lateral bipolar transistors, a positive voltage is applied to the supply voltage with respect to the reference potential, and the supply voltage includes the first and second supply voltages. The lateral bipolar transistor is pnp lateral bipolar transistor If, relative to the reference potential, it can be achieved by being applied a negative voltage.

  According to the semiconductor device and the driving method thereof of the present invention, the proportionality coefficient can be designed accurately, and a voltage that is proportional to the absolute temperature and insensitive to fluctuations in the power supply voltage can be generated on the integrated circuit. Since a fine semiconductor element is operated in a region modeled by a diffusion current, the minimum operating power supply voltage can be operated with a very low power supply voltage of about 0.2 V (output voltage +0.1 V), Power consumption is extremely small and the design area is extremely small. In addition, since the output voltage proportional to the temperature is determined by the ratio of the diffusion currents obtained by a plurality of semiconductor elements having different shape ratios, characteristics that do not depend on parameter variations in the manufacturing process are realized. Therefore, it is possible to realize a PTAT circuit that can be integrated on-chip that can be driven by a weak power source such as a solar battery, and to an application circuit and a bias voltage circuit that are mounted on a general-purpose integrated circuit and perform temperature detection on-chip. The effect is that it can be widely applied.

FIG. 1A is a circuit configuration diagram using an NMOSFET according to the present invention. FIG. 1B is a circuit configuration diagram using a PMOSFET according to the present invention. FIG. 2A is a circuit configuration diagram when the semiconductor device according to the first embodiment of the present invention shown in FIG. 1A is configured using lateral bipolar transistors. FIG. 2B is a circuit configuration diagram when the semiconductor device according to the first embodiment of the present invention shown in FIG. 1B is configured using lateral bipolar transistors. FIG. 3A is a schematic structural cross-sectional view of FIG. 1A. FIG. 3B is a schematic structural cross-sectional view of FIG. 1B. FIG. 3C is a schematic cross-sectional view of the structure when FIG. 1A is manufactured by an SOI process. FIG. 3D is a schematic top view when FIG. 1A is manufactured by an SOI process. FIG. 3E is a schematic cross-sectional view of the structure when FIG. 1B is manufactured by an SOI process. FIG. 3F is a schematic structural cross-sectional view of the case where FIG. 2A is manufactured by a SOI process using a lateral bipolar transistor. FIG. 3G is a schematic top view when FIG. 2A is manufactured by a SOI process using a lateral bipolar transistor. FIG. 3H is a schematic cross-sectional view of the structure when FIG. 2B is manufactured by a SOI process using a lateral bipolar transistor. FIG. 4 is a conceptual diagram showing an operation region of the semiconductor device according to the first embodiment of the present invention. FIG. 5A is an example of a circuit used for measurement when a DC voltage source is connected to a semiconductor device having an NMOSFET structure according to the first embodiment of the present invention corresponding to FIG. 1A. FIG. 5B is an example of a circuit used for measurement when a DC voltage source is connected to a semiconductor device having a PMOSFET structure according to the first embodiment of the present invention corresponding to FIG. 1B. 5A is a diagram showing a measurement result of an output potential difference VO-VS with respect to a potential difference VD-VS when the absolute temperature T is used as a parameter in the measurement circuit of the semiconductor device having the NMOSFET configuration according to the first embodiment of the present invention corresponding to FIG. 5A. is there. FIG. 5B is a diagram showing a measurement result of a consumption current ID with respect to a potential difference VD−VS when an absolute temperature T is used as a parameter in the measurement circuit of the semiconductor device having the NMOSFET configuration according to the first example of the present invention corresponding to FIG. 5A. FIG. 5B is a diagram illustrating theoretical characteristics and measurement results of an output potential difference VO−VS with respect to an absolute temperature T in the measurement circuit of the semiconductor device having the NMOSFET configuration according to the first embodiment of the present invention corresponding to FIG. 5A. FIG. 9A is a circuit configuration example when VC = VB = VS in the NMOSFET semiconductor device according to the first embodiment of the present invention corresponding to FIG. 1A. FIG. 9B is a circuit configuration example when VC = VB = VS in the semiconductor device having the PMOSFET configuration according to the first embodiment of the present invention corresponding to FIG. 1B. FIG. 9C is a circuit configuration example in the case of VC = VO and VB = VS in the NMOSFET semiconductor device according to the first embodiment of the present invention corresponding to FIG. 1A. FIG. 9D is a circuit configuration example when VC = VO and VB = VS in the semiconductor device having the PMOSFET configuration of the first embodiment of the present invention corresponding to FIG. 1B. It is a figure which shows the theoretical characteristic and measurement result of output potential difference VO-VS with respect to absolute temperature T in the circuit structural example of the semiconductor device of the NMOSFET structure of 1st Example of this invention corresponding to FIG. 9A. FIG. 11A is a circuit configuration example for realizing a large positive temperature coefficient by cascading the semiconductor devices of the NMOSFET configuration according to the first embodiment of the present invention corresponding to FIG. 1A. FIG. 11B is a circuit configuration example for realizing a large negative temperature coefficient by cascading the semiconductor devices having the PMOSFET configuration according to the first embodiment of the present invention corresponding to FIG. 1B.

  A semiconductor device and a driving method thereof according to an embodiment of the present invention will be described. The present invention operates two source-side MOSFETs and sink-side MOSFETs provided with the same structure, the same gate bias condition, and the same substrate bias condition connected in series in an operation region modeled by a diffusion current, and By biasing the gate terminal of the source side MOSFET without diode connection, a PTAT reference voltage source that can operate from a minute voltage to a wide power supply voltage range and is insensitive to fluctuations in the power supply voltage has been created.

  Specifically, two source-side MOSFETs and sink-side MOSFETs having the same structure are connected in series with the source terminal of the source-side MOSFET and the drain terminal of the sink-side MOSFET, and the gate terminals of the two MOSFETs connected in series are shared. In addition to the connection, substrate terminals of two MOSFETs connected in series are connected in common. The gate terminals connected in common in the two MOSFETs connected in series are configured to apply a potential independently of the drain terminal of the source-side MOSFET. Even if the drain terminal voltage of the MOSFET on the source side fluctuates, the operating region of the two MOSFETs is determined by the voltage between the gate terminal and the substrate terminal in the MOSFET, so the operating region is not limited to the threshold voltage of the MOSFET, Operation in an operation region based on the diffusion current model can be performed under a wide range of driving power supply voltages. The bias condition of the gate terminal in the two MOSFETs connected in series is that the surface of the channel region immediately below the gate region of the MOSFET is biased within a voltage range that allows the diffusion current to flow from the flat band state to the operation region where no inversion layer occurs. To do. When the clock in the general-purpose CMOS circuit is input to the gate terminals of the two MOSFETs connected in series, the driving state of the present invention is achieved when the clock voltage satisfies the bias condition described above. The bias condition of the substrate terminal in the two MOSFETs connected in series is within a voltage range for biasing the pn junction connected to the source terminal of the sink-side MOSFET from a weak forward bias to a reverse bias (including zero bias). Set. Furthermore, by adjusting the bias voltage of the substrate terminal, it is possible to adjust the current consumption of the semiconductor device and to control the operation speed of the semiconductor device. In the model formula of a MOSFET operating in the operating region based on the diffusion current model, the drain current characteristic of the MOSFET is an index determined by the voltages at the four terminals of the gate terminal, the source terminal, the drain terminal, and the substrate terminal without using the threshold voltage. It is expressed by a combination of characteristics. By analyzing the semiconductor device of the present invention and its driving method by applying a diffusion current model, the potential of the connection point between the drain terminal of the sink side MOSFET and the source terminal of the source side MOSFET is based on the source voltage of the sink side MOSFET. It is theoretically derived that the output voltage is proportional to the absolute temperature. Furthermore, the proportionality coefficient of the output voltage to the absolute temperature is k / q × ln (m + 1) when the channel shape ratio of the source side MOSFET to the channel shape ratio of the sink side MOSFET is m times. Here, k is a Boltzmann constant, and q is an elementary electric quantity. The proportional coefficient of the output voltage to the absolute temperature does not include the various parameters in the manufacturing process and the slope coefficient n in the exponential operation state, and is determined by the physical constant and the channel shape of the MOSFET. In addition, it is possible to design accurately by the channel shape of the MOSFET. Further, the reference voltage source of the present invention is a connection point between the drain terminal of the sink side MOSFET and the source terminal of the source side MOSFET with respect to the fluctuation of the voltage of the drain terminal of the source side MOSFET with respect to the source terminal of the sink side MOSFET. Therefore, the power supply voltage fluctuation rejection ratio is high.

  BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1A is a circuit diagram of a PTAT reference voltage source of the present invention configured by using an NMOSFET in an operating state in which an inversion layer is not formed as a semiconductor element for passing a diffusion current. A source-side NMOSFET (Mn2) and a sink-side NMOSFET (Mn1) having the same structure manufactured by setting the design parameters other than the channel shape ratio of the MOSFET and the manufacturing process parameters to be equal, the source terminal of Mn2, and the drain terminal of Mn1 The gate terminals of the two MOSFETs connected in series are connected in common, and the substrate terminals of the two MOSFETs connected in series are connected in common. When the n-type impurity semiconductor constituting the source terminal of Mn2 and the n-type impurity semiconductor region constituting the drain terminal of Mn1 have the same impurity concentration, that is, have the same process parameters, the source terminal of Mn2 and Mn1 The n-type impurity semiconductor region can be formed by sharing the drain terminal of each other. The gate terminals connected in common in the two MOSFETs connected in series are configured to give a potential independently of the drain terminal of Mn2. The channel shape ratios of the Mn1 and Mn2 MOSFETs are designed so that Wn1 / Ln1 = mn1 for Mn1 and Wn2 / Ln2 = mn2 for Mn2 by giving a channel width W and a channel length L, respectively. Adjust so that the ratio of mn2 is m. Further, by designing the channel lengths Ln1 and Ln2 of Mn1 and Mn2 to be the same, nonlinear elements related to the channel length can be reduced. Further, when m is an integer, m-shaped MOSFETs having the same shape as Mn1 are connected in parallel, and the Mn2 MOSFET is designed with m MOSFETs connected in parallel, thereby processing the channel shape in the manufacturing process. It is possible to determine m accurately by reducing the influence of errors.

  FIG. 3A is a schematic structural cross-sectional view when the PTAT reference voltage source shown in FIG. 1A is configured using MOSFETs. The n-type high-concentration semiconductor region 2 connected to the output terminal 22 is shown as one n-type high-concentration semiconductor region 2 for convenience, but is divided into two n-type high-concentration semiconductor regions having the same concentration. It can also be configured. FIG. 3B is a schematic structural cross-sectional view when the PTAT reference voltage source shown in FIG. 1B is configured by using a MOSFET. The p-type high-concentration semiconductor region 12 connected to the output terminal 22 is shown as an example constituted by one p-type high-concentration semiconductor region 12 for convenience, but is divided into two p-type high-concentration semiconductor regions of the same concentration. It can also be configured. FIG. 3C is a schematic cross-sectional view of the structure when the PTAT reference voltage source shown in FIG. 1A is configured on an SOI substrate using a MOSFET. FIG. 3D is a schematic top view of FIG. 3C. FIG. 3E is a schematic structural cross-sectional view when the PTAT reference voltage source shown in FIG. 1B is configured on an SOI substrate using a MOSFET.

  A lateral bipolar transistor is known as a semiconductor element through which a diffusion current flows, like a MOSFET that does not form an inversion layer. FIG. 1A shows the MOSFET source terminal corresponding to the emitter terminal of the lateral bipolar transistor, the MOSFET drain terminal corresponding to the collector terminal of the lateral bipolar transistor, and the MOSFET substrate terminal corresponding to the base terminal of the lateral bipolar transistor. The semiconductor device can constitute a PTAT reference voltage source that operates according to the same theory of operation and generates the same output voltage in a circuit that uses a lateral bipolar transistor as a semiconductor element as shown in FIG. 2A. In this case, it does not have a gate terminal. Similarly, the semiconductor device shown in FIG. 1B can constitute a PTAT reference voltage source that operates with the same theory of operation and generates the same output voltage in a circuit that uses a lateral bipolar transistor as a semiconductor element as shown in FIG. 2B. FIG. 3F is a schematic structural cross-sectional view when the PTAT reference voltage source shown in FIG. 1A is configured on an SOI substrate using a lateral bipolar transistor. In the case where a lateral bipolar transistor is used instead of the MOSFET for passing the diffusion current, the gate region 14 of the sink side semiconductor element, the gate region 15 of the source side semiconductor element, and the gate terminal 24 are not provided. FIG. 3G is a schematic top view of FIG. 3F. FIG. 3H is a schematic cross-sectional view of a structure in which the PTAT reference voltage source shown in FIG. 1A is configured on an SOI substrate using a lateral bipolar transistor. Similar to FIG. 3F, when a lateral bipolar transistor is used instead of a MOSFET for passing a diffusion current, the gate region 14 of the sink-side semiconductor element, the gate region 15 of the source-side semiconductor element, and the gate terminal 24 are not provided.

  Here, to the gate terminals (VC) of Mn1 and Mn2, a voltage in a range where the channel region immediately below the gate region of the MOSFETs of Mn1 and Mn2 satisfies the operation region where the inversion layer is not formed from the flat band state is applied. The substrate terminal (VB) of Mn1 and Mn2 has a substrate terminal in the voltage range (including zero bias) in which the source side pn junction of Mn1 is slightly operated in the forward-biased operation region. Apply voltage. A potential difference VD-VS is applied between the source terminal (VS) of Mn1 and the drain terminal (VD) of Mn2 in a direction in which VD becomes positive with respect to VS. The potential difference of VD with respect to VS is given by about 0.1 V or more than the potential difference VO−VS of the output terminal (VO) connected to the drain terminal of Mn1 with reference to VS. As a result, the potential difference VO−VS of the output terminal connected to the drain terminal of Mn1 with respect to VS is proportional to the absolute temperature and becomes VO−VS = kT / q × ln (m + 1). Here, k is a Boltzmann constant, T is an absolute temperature, and q is an elementary charge.

Next, the operating characteristics of the PTAT circuit of the present invention will be described using a diffusion current model representing the drain current characteristics of a MOSFET in which an inversion layer is not formed. When a single four-terminal MOSFET operates in the weak inversion region, the drain current is modeled as a diffusion current due to carrier injection from the source end pn junction and the drain end pn junction in the region near the gate, and the voltages VG of the four terminals are Using VB, VS, VD,
ID = I0 (EXP (q. (R (VG-VB)-(VS-VB)) / kT)
-EXP (q. (R (VG-VB)-(VD-VB)) / kT)) (1) Here, r is a deterioration factor of the gate voltage that represents the rate at which the surface potential of the channel region of the MOSFET changes with respect to the voltage applied to the gate region. It has a value of about 9. I0 is expressed as A · q · Dn · np0 / L, A is an effective junction cross-sectional area of two pn junction side regions in contact with the MOSFET channel region, Dn is an electron diffusion coefficient, and np0 is an NMOSFET channel The electron carrier density, L, of the p-type substrate constituting the region is the length from the source end pn junction to the drain end pn junction in the channel region, and is shorter than the electron diffusion length. The variation factor due to the substrate effect of the MOSFET in the drain current equation shown in the existing model of the MOSFET operating in the weak inversion region is based on the drain current in the MOSFET (4) and the voltage at the four terminals as the substrate potential. Are defined using the three pairs of terminal voltages VG-VB, VS-VB, and VD-VB, and are modeled without using a threshold voltage. The drain current of Mn1 can be expressed using equation (1).
In1 = mn1 · I0 · EXP (q · (rVC + (1−r) VB) / kT)
(EXP (−q · VS / kT) −EXP (−q · VO / kT)), (2) The drain current of Mn2 can be expressed using equation (1).
In2 = mn2 · I0 · EXP (q · (rVC + (1−r) VB) / kT)
(EXP (−q · VO / kT) −EXP (−q · VD / kT)), (3). In equation (3), when the second term is sufficiently small relative to the first term, equation (3) is
In2 = mn2 · I0 · EXP (q · (rVC + (1−r) VB) / kT)
EXP (−q · VO / kT), rewritten as (4) Here, if the current flowing out from the output terminal is sufficiently small,
In1 = In2, (5) The term of I0 · EXP (q · (rVC + (1−r) VB) / kT) in the equations (2) and (4) is obtained by using the gate voltage VC and the substrate voltage VB input to Mn1 and Mn2 in common. Giving the same structure by matching the parameters in the manufacturing process of Mn1 and Mn2 so as to have the same value. From Formula (2), Formula (4), and Formula (5),
(M + 1) EXP (−q (VO−VS) / kT) = 1 + EXP (−q (VD−VS) / kT), (6)
It becomes. Here, m represents the ratio of mn2 to mn1. When the second term is sufficiently smaller than the first term on the right side of Equation (6),
VO-VS = kT / q · ln (m + 1), The positive PTAT characteristic of (7) is derived. The temperature coefficient for the absolute temperature T is accurately determined by the physical constants k, q and the ratio m of the channel shape ratio of Mn2 to Mn1.
In Equation (3), a condition for the second term to be sufficiently smaller than the first term is considered. The relative error ε of the second term relative to the first term is
ε = EXP (−q (VD−VO) / kT), (8) When the relative error of the second term with respect to the first term is sufficiently small and can be ignored, εneg is expressed as εneg, and εneg is expressed using a function system similar to Equation (8).
εneg = EXP (−q · Vneg / kT) (9) Here, Vneg is a converted voltage value of the error voltage that gives the maximum error εneg in equation (9). In order for the relative error of the second term to the first term to be sufficiently small and negligible,
ε ≦ εneg, (10) may be satisfied. For example, if εneg = 0.02, Vneg≈0.1 V (≈4 · kT / q) at T = 300K. From Equations (8), (9), and (10), the range of VD that Equation (3) can approximate to Equation (4) is
VD ≧ VO + Vneg, (11) Similarly, the range of VD that equation (6) can approximate to equation (7) is
ε = EXP (−q (VD−VS) / kT), (12) and using equations (9) and (10),
VD ≧ VS + Vneg, (13). Here, since VO is larger than VS, the condition of the equation (13) is included in the condition of the equation (11). Therefore, in order to obtain an approximation for deriving the equation (7), the voltage of VD is expressed by the equation (11). ).

Next, consider the operating area of the proposed circuit. Since the MOSFET operates in the weak inversion region, the gate voltage VC-VB based on the substrate voltage VB of the two MOSFETs is
VC−VB ≦ Vtn, (14) must be satisfied. Here, Vtn is a voltage at which an inversion layer is formed in the channel region of the NMOSFET. In addition, in order that the drain current of the MOSFET in which the MOSFET operates in the weak inversion region can be controlled by the gate voltage VC-VB based on the substrate voltage VB,
VC−VB ≧ Vfn, (15) must be satisfied. Here, Vfn is a voltage at which the channel region of the NMOSFET becomes a flat band state. Moreover, it is necessary to satisfy Expression (11) as an approximate condition for satisfying Expression (7). FIG. 4 shows an operation region of Mn2 with respect to the relationship between the drain voltage VD-VS of Mn2 based on the source terminal voltage VS of Mn1 and the output voltage VO-VS based on the source terminal voltage VS of Mn1. The characteristic of the output voltage VO-VS with reference to the source terminal voltage VS of Mn1 is shown by a solid line. The PTAT voltage Vpm at a certain absolute temperature increases to VpmH as the temperature increases, and decreases to VpmL as the temperature decreases. The minimum potential difference VD−VS (referred to as VDmin) required to operate the PTAT circuit of the present invention is obtained as VDmin ≧ VpmH + Vneg using the PTAT voltage VpmH at a high temperature from the equation (11). When a MOSFET having a sufficiently long channel length is used, a PTAT voltage that does not depend on the power supply voltage can be generated for a voltage VD that is equal to or higher than VDmin. As shown in equations (2) and (4), the current consumption can be controlled independently of the relationship of equation (7) by VC and VB, and a stable PTAT voltage can be obtained.

  Even when a lateral bipolar transistor is used as a semiconductor device for passing a diffusion current, the PTAT characteristic of Expression (7) can be obtained in the same manner because it operates according to the same principle as that of the case where the MOSFET is configured to pass a diffusion current. The operating condition may satisfy Expression (11) in the same manner as in the case where the operating condition is configured using a MOSFET that allows a diffusion current to flow.

  As a measurement circuit of the PTAT circuit shown in FIG. 1A, a description will be given of a measurement result in the case where a DC power source as shown in FIG. 5A is connected to the PTAT circuit shown in FIG. 1A prototyped by a 0.18 μm-well CMOS process. In the PTAT circuit of FIG. 5A, when VS = 0V, VB = 0V, VC = 0.2V, m = 10 (Wn1 / Ln1 = 3 μm / 10 μm, Wn2 / Ln2 = 30 μm / 10 μm), the source of Mn1 FIG. 6 shows the relationship between the drain voltage VD-VS of Mn2 based on the terminal voltage VS and the output voltage VO-VS based on the source terminal voltage VS of Mn1. Using the absolute temperature T as a parameter, the absolute temperature was measured from 278K to 400K. A voltage that satisfies the conditions of the equations (14) and (15) is applied to the VC. The PTAT voltage Vpm moves in parallel at substantially equal intervals with respect to the change in absolute temperature. The PTAT voltage VpmH at T = 400K is 0.088V. The minimum potential difference VDmin required to operate the PTAT reference voltage source is VDmin = 0.188V. When the drive voltage VD-VS is in the range of 0.2V to 1.8V, an average constant output voltage is obtained regardless of VD-VS, and when VD-VS fluctuates by 1V at T = 300K, the output voltage VO -VS has only a slight fluctuation of 0.3 mV, and the power supply voltage fluctuation elimination ratio obtained from this value is -70 dB. A bias voltage circuit that can operate over a wide power supply voltage range from a minute power supply voltage and is insensitive to fluctuations in the power supply voltage on an integrated circuit is realized. FIG. 7 shows current consumption ID with respect to VD-VS in the measurement circuit of the PTAT circuit shown in FIG. 5A. When the absolute temperature T changes from 278 K to 400 K, the current consumption changes from 100 pA to 8 nA, and the device operates with a low current consumption. In the PTAT circuit of FIG. 5A, when VS = 0V, VB = 0V, VC = 0.2V, VD = 0.5V, m = 50, 10, 1 are given, the absolute temperature and the source terminal voltage VS of Mn1 are The relationship of the reference output voltage VO-VS is shown in FIG. The measured values when the ratio m of the channel shape ratio of Mn2 to Mn1 is set to m = 50, m = 10, and m = 1 are indicated by ■, ▲, and ●, respectively. The calculated values corresponding to the equation (7) when the ratio m of the channel shape of Mn2 to Mn1 is m = 50, m = 10, and m = 1 are indicated by a broken line, a solid line, and a dotted line, respectively. The circles indicate the measurement results when VB is changed to VB = 0.2V. The calculated value when T = 300K (room temperature) is VO-VS = 102 mV when m = 50, VO-VS = 62 mV when m = 10, and VO-VS = 18 mV when m = 1. The measurement result agrees well with the calculation result, the output voltage is proportional to the absolute temperature T, and the semiconductor device of the present invention operates accurately as a PTAT reference voltage source.

As a modification of the above example, a circuit diagram of a PTAT reference voltage source configured using a PMOSFET is shown in FIG. 1B. By performing the same analysis as the PTAT circuit using NMOSFET,
VO−VS = −kT / q · ln (m + 1), (16), and a negative PTAT characteristic is derived. In the configuration using the PMOSFET, a potential difference VD−VS is applied between the source terminal (VS) of Mn1 and the drain terminal (VD) of Mn2 in a direction in which VD becomes negative with respect to VS. At this time, the conditions for the expression (16) to be satisfied are as follows.
VD ≦ VO−Vneg, (17).

Next, consider the operating region. Since the MOSFET operates in the weak inversion region, the gate voltage VC-VB based on the substrate voltage VB of the two MOSFETs is
VC−VB ≧ Vtp, (18) must be satisfied. Here, Vtp (Vtp <0) is a voltage at which an inversion layer is formed in the channel region of the PMOSFET. In addition, in order that the drain current of the MOSFET operating in the weak inversion region can be controlled by the gate voltage VC-VB based on the substrate voltage VB,
VC−VB ≦ Vfp, (19) must be satisfied. Here, Vfp is a voltage at which the channel region of the NMOSFET becomes a flat band state. Moreover, it is necessary to satisfy Expression (17) as an approximate condition for satisfying Expression (16). FIG. 5B shows an example of DC voltage connection in a circuit having a PMOSFET configuration corresponding to FIG. 5A.

  Even when a lateral bipolar transistor is used as a semiconductor device for passing a diffusion current, the PTAT characteristic of the equation (16) can be obtained in the same manner because it operates according to the same principle as that of a case where a MOSFET for passing a diffusion current is used. The operating condition may satisfy Expression (17) similarly to the case where the MOSFET is configured to flow a diffusion current.

  As an example of a driving method using the semiconductor device, a PTAT circuit having an NMOSFET structure that can be driven by only one external bias power supply by connecting VC and VS and connecting VB and VS is shown in FIG. 9A. . The PTAT voltage shown in equation (7) is generated. The operating condition is determined only by equation (11). With respect to the PTAT circuit of FIG. 9A, when VD = 0.5 V, VS = 0.0 V, m = 1 (Wn1 / Ln1 = 3 μm / 10 μm, Wn2 / Ln2 = 3 μm / 10 μm), absolute temperatures T and Mn1 The relationship of the output voltage VO-VS with reference to the source terminal voltage VS is shown in FIG. The measured values when the ratio m of the channel shape ratio of Mn2 to Mn1 is set to m = 1 are indicated by marks. In addition, a solid line represents a calculated value corresponding to Equation (7) when the ratio m of the channel shape ratio of Mn2 to Mn1 is m = 1. The measurement result agrees well with the calculation result, and the output voltage is proportional to the absolute temperature T.

As an example of another driving method, FIG. 9B shows a PTAT circuit having a PMOSFET structure that can be driven by only one external bias power source by connecting VC and VS and connecting VB and VS. The PTAT voltage shown in equation (16) is generated. The operating condition is determined only by equation (17). As an example of another driving method, FIG. 9C shows a PTAT circuit having an NMOSFET structure that can be driven by only one external bias power source by connecting VC and VO and connecting VB and VS. The PTAT voltage shown in equation (7) is generated. The operating conditions are as follows:
VO−VS ≦ Vtn, determined by (20). As an example of a driving method in the modification of the above example, FIG. 9D shows a PTAT circuit having a PMOSFET structure that can be driven by only one external bias power source by connecting VC and VO and connecting VB and VS. The PTAT voltage shown in equation (16) is generated. The operating conditions are as follows:
VO−VS ≧ Vtp, determined by (21). These examples have the advantage that the PTAT voltage can be generated with a single power source.

As another modification, VD, VC, and VB of N PTAT circuits are connected in common, and the output terminal VOk of the kth stage PTAT circuit from k = 1 to k = N−1 is connected to the (k + 1) th stage. A PTAT circuit having an NMOSFET configuration in which N-stage PTAT circuits are connected in cascade by connecting to the source terminal VS (k + 1) of the PTAT circuit, the first-stage source terminal VS1 is VS, and the N-stage output is VON is shown in FIG. Shown in m1 to m2N represent channel shape ratios of MOSFETs corresponding to Mn1 to Mn2N, respectively. By performing the same analysis, for example, m2 = m4 = ... m2 (N-1) -1 = m-1, m2N = m + 1, m1 = m3 = ... m2N-1 = 1, m >> 1 / m if you did this,
VON−VS = N · kT / q · ln (m + 1), (22) This is an effective configuration for realizing a large temperature coefficient multiplied by N. The operating conditions are
VD ≧ VON + Vneg, (23) VD, VC and VB of N PTAT circuits are connected in common, and the output terminal VOk of the kth stage PTAT circuit from k = 1 to k = N−1 is set to VS (k + 1) of the k + 1 stage PTAT circuit. FIG. 11B shows a PTAT circuit having a PMOSFET configuration in which N-stage PTAT circuits are connected in cascade, the first-stage source terminal VS1 is VS, and the N-stage output is VON. m1 to m2N represent channel shape ratios of MOSFETs corresponding to Mp1 to Mp2N, respectively. By performing the same analysis, for example, m2 = m4 = ... m2 (N-1) -1 = m-1, m2N = m + 1, m1 = m3 = ... m2N-1 = 1, m >> 1 / m if you did this,
VON−VS = −N · kT / q · ln (m + 1), (23) This is an effective configuration for realizing a large temperature coefficient multiplied by N. The operating conditions are
VD ≦ VON−Vneg, (24).

  As described above, according to the present invention, the proportionality coefficient can be designed accurately and proportional to the absolute temperature, and a voltage insensitive to fluctuations in the power supply voltage can be generated on the integrated circuit. Since a fine MOSFET is operated in a region modeled by diffusion current, the minimum operating power supply voltage can be operated at a very low power supply voltage of about 0.2V, and the power consumption is extremely small, and the design area Is extremely small. In addition, since the output voltage proportional to the temperature is determined by the ratio of diffusion currents obtained by a plurality of MOSFETs having different shape ratios, characteristics that do not depend on variations in parameters in the manufacturing process are realized. Therefore, a PTAT circuit that can be integrated on-chip that can be driven by a weak and unstable power source such as a solar cell can be realized, and a wide range of application circuits and bias voltage circuits that are mounted on general-purpose integrated circuits and perform temperature detection on-chip. Adaptable. Furthermore, the PTAT voltage source of the present invention can be widely used in applications for obtaining a reference voltage source independent of temperature by combining with a circuit having different temperature dependency.

  In the present invention, a voltage that can be driven with a low power supply voltage and is stable with respect to fluctuations in the power supply voltage is generated, and the temperature coefficient of the voltage is less affected by parameter fluctuations in the manufacturing process. Therefore, it can be used as a semiconductor device for generating a PTAT voltage that can be accurately designed on an integrated circuit. The PTAT reference voltage source is used as an indispensable circuit for constituting an integrated reference voltage generating circuit, an integrated temperature detector, etc. capable of driving a low power supply voltage under the recent miniaturized CMOS process. . In addition, the semiconductor device of the present invention can be widely used as a minute bias voltage circuit that is insensitive to fluctuations in power supply voltage on an integrated circuit.

DESCRIPTION OF SYMBOLS 1 .... n-type high concentration semiconductor region 2 .... n-type high concentration semiconductor region 3 .... n-type high concentration semiconductor region 6 .... p-type high concentration semiconductor region 7 .... p-type high concentration semiconductor region 8 .... Semiconductor region 9... P-type semiconductor region 11... P-type high concentration semiconductor region 12... P-type high concentration semiconductor region 13... P-type high concentration semiconductor region 14. Side semiconductor element gate region 16 ... n-type high concentration semiconductor region 17 ... n-type high concentration semiconductor region 18 ... n-type semiconductor region 19 ... n-type semiconductor region 21 ... sink-side semiconductor element source terminal 22 ... Output terminal 23 ... Source side semiconductor element drain terminal 24 ... Gate terminal 25 ... Insulating film 26 ... Insulating layer 27 ... Substrate terminal 28 ... Insulating layer 29 ... Insulating layer

Claims (4)

In a semiconductor device including a first lateral bipolar transistor and a second lateral bipolar transistor ,
Connects the emitter terminal of said second lateral bipolar transistor and the collector terminal of said first lateral bipolar transistor,
The terminals of the emitter terminal of said second lateral bipolar transistor and the collector terminal of said first lateral bipolar transistor and an output terminal,
The emitter terminal of said first lateral bipolar transistor and a reference potential,
Wherein the collector terminal of the second lateral bipolar transistor by applying a predetermined supply voltage, connects the base terminal of the base terminal and the second lateral bipolar transistor of said first lateral bipolar transistor,
The terminals of the base terminal of the base terminal and the second lateral bipolar transistor of said first lateral bipolar transistor as a first base terminal,
From said first lateral bipolar transistor and said second lateral bipolar transistor is a lateral bipolar transistor of the same structure,
The first base terminal is applied with a voltage in a range where the emitter side pn junction of the first lateral bipolar transistor becomes a slightly forward biased operation region to a reverse biased operation region;
When the first and second lateral bipolar transistors are npn lateral bipolar transistors , a positive voltage is applied to the supply voltage with respect to the reference potential.
The semiconductor device according to claim 1, wherein, when the first and second lateral bipolar transistors are pnp lateral bipolar transistors , a negative voltage is applied to the reference potential as the supply voltage. In claim 1,
When the first and second lateral bipolar transistors are npn lateral bipolar transistors , the supply voltage is larger than the output voltage of the output terminal by a predetermined value,
In the case where the first and second lateral bipolar transistors are pnp lateral bipolar transistors , the supply voltage is smaller than the output voltage of the output terminal by a predetermined value. In claim 1 or 2,
The semiconductor device is used as a PTAT voltage generation circuit or a bias voltage generation circuit. In a semiconductor device including a first lateral bipolar transistor and a second lateral bipolar transistor ,
Connects the emitter terminal of said second lateral bipolar transistor and the collector terminal of said first lateral bipolar transistor,
N semiconductor devices each including a base terminal of the first lateral bipolar transistor and a base terminal of the second lateral bipolar transistor are connected (N is an integer of 2 or more)
connecting the collector terminals of the second lateral bipolar transistors of the semiconductor device from k = 1 (k is a natural number) to k = N, respectively, and applying a predetermined supply voltage;
connecting base terminals of the first lateral bipolar transistors of the semiconductor device from k = 1 to k = N, respectively, and applying a predetermined voltage;
Semiconductor k = 1 from the said second lateral bipolar transistor and the collector terminal of the first lateral bipolar transistor of the semiconductor device up to k = N-1 between the emitter terminal and the terminal from the k = 2 to k = N connected to the emitter terminal of the first lateral bipolar transistor devices,
k = the first output terminal between the terminal and the emitter terminal of the collector terminal second lateral bipolar transistor of the lateral bipolar transistor of the semiconductor device of the N,
From said first lateral bipolar transistor and said second lateral bipolar transistor is a lateral bipolar transistor of the same structure,
The first base terminal is applied with a voltage in a range where the emitter side pn junction of the first lateral bipolar transistor becomes a slightly forward-biased operation region to a reverse-biased operation region,
When the first and second lateral bipolar transistors are npn lateral bipolar transistors , a positive voltage is applied to the supply voltage with respect to the reference potential.
The semiconductor device according to claim 1, wherein, when the first and second lateral bipolar transistors are pnp lateral bipolar transistors , a negative voltage is applied to the reference potential as the supply voltage.

Images