KR100401526B1 - Logic circuit for preventing hot carrier effect - Google Patents

Abstract

PURPOSE: A logic circuit for preventing a hot carrier effect is provided to prevent the deterioration of MOS transistors by generating the hot carrier effect only at a transfer gate. CONSTITUTION: A logic circuit for preventing a hot carrier effect includes a plurality of first conductive type MOS transistors(P21,P22), a plurality of second conductive type MOS transistors(N21,N22). The first conductive type MOS transistors(P21,P22) are connected in parallel between a power supply terminal and a ground terminal. The second conductive type MOS transistors(N21,N22) are serially connected to the first conductive type MOS transistors(P21,P22). A transfer gate(T21) is serially connected between an output node and the second conductive type MOS transistor neighboring to the output node.

Description

Logic Circuitry Prevents Hot Carrier Effects

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to logic gate circuits, and more particularly, to logic gate circuits that can prevent deterioration of circuit characteristics due to hot carrier effects.

In general, as the size of the morph transistor becomes smaller, the internal electric field strength increases, and energy is applied to the carrier of the channel in the depletion layer near the drain to accelerate the carrier. If the energy applied to the carrier is greater than the potentials of the silicon and the gate oxide film, the accelerated carrier is trapped in the gate oxide film, or the gate oxide film is tunneled to form a gate current. This phenomenon is called a hot carrier effect, and this hot carrier effect lowers the driving ability of the device, thereby lowering the characteristics of the circuit. This hot carrier effect is more severe degradation of the characteristics of the N MOS transistor by the electrons of the P and N morph transistors, and when the N MOS transistors are connected in series, the drain is connected to the power supply voltage terminal or the output terminal is severe.

1 is a logic circuit diagram of a typical two-input NAND gate.

The logic of the NAND gate is connected in series with N MOS transistors N11 and N12 in which P MOS transistors P11 and P12 connected in parallel between the power supply voltage Vdd and ground are connected in series. The NAND gate has a first input 111 at a gate of a P MOS transistor P11 and an N MOS transistor N11, and a second input at a gate of a P MOS transistor P12 and an N MOS transistor N12. I12) is input to output O11 from the output node 10.

In the NAND gate, when both the first and second inputs I11 and I12 are 'high', the N-node transistors N11 and N12 connected in series are all turned on, so that the NAND gate is turned on at the output node 10. The output O11 in the 'low' state is output. In addition, the NAND gate is 'turned on' when any one or both of the first and second inputs I11 and I12 are 'low', and either or both of the N must transistors N11 and N12 connected in series are turned on. 'So, the output (O11) of the' high 'state is output from the output node (10).

When the NAND gate described above is applied with the first and second inputs I11 and I12 having a 'high' state to the gates of the N MOS transistors N11 and N12, the N MOS transistor N12 connected to ground is N. Since the MOS transistor N11 is 'turned on' after being 'turned on', deterioration of device characteristics due to the hot carrier effect is reduced.

However, the NAND gate described above has a problem in that the N-MOS transistor having a drain connected to the output node has a deeper depletion region than the N-MOS transistor connected to ground, so that the hot carrier effect is increased, thereby degrading the characteristics of the circuit.

Accordingly, an object of the present invention is to provide a logic gate circuit capable of preventing the characteristics of the circuit from being degraded by the hot carrier effect.

The logic circuit for preventing the hot carrier effect according to the present invention for achieving the above object is the same number of first plurality of transistors and the first conductivity type MOS transistors connected in parallel between the power supply voltage terminal and ground. The second conductive type MOS transistors connected in series are connected in series, and the plurality of input signals are respectively input to the gates of the paired first and second MOS transistors to output one output at an output node. A transmission gate is connected in series between the output node and the second conductive type MOS transistor adjacent to the output node of the second conductive type MOS transistor.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Although the present invention will be described with an two-input NAND gate as an embodiment, it should be understood that the present invention is not limited to this embodiment and can be applied to other embodiments, that is, other logic gate circuits such as noah gates without changing the gist. .

2 is a logic circuit diagram of a two input NAND gate capable of preventing hot carrier effects according to an embodiment of the present invention.

The logic of the NAND gate includes a transmission gate T21 and N MOS transistors N21 and N22 connected in series with P-MOS transistors P21 and P22 connected in parallel between a power supply voltage Vdd and ground. Leads to. The NAND gate has a first input I21 input to the gates of the P MOS transistor P21 and the N MOS transistor N21, and a second input to the gates of the P MOS transistor P22 and the N MOS transistor N22. I22) is input and the output O21 is output from the output node 20. In addition, between the output node 20 and the N MOS transistor N21, a first input I21 is directly input to the N gate and a transfer gate T21 connected to the P gate through the inverter I21 is connected. .

The NAND gate is " turned on " in addition to the N MOS transistors N21 and N22 connected in series when both the first and second inputs I21 and I22 are 'high'. Therefore, the output (O21) of the 'low' state is output from the output node 20. At this time, the transfer gate T21 and the N MOS transistors N21 and N22 are 'turned on' at the same time. Therefore, the depletion region of the N gate of the transfer gate T21 is deeply formed to increase the hot carrier effect. The transfer gate T21 passes only electrons, so that deterioration of device characteristics results in operating characteristics of a logic circuit. Has nothing to do with However, in order to reduce the influence of hot electrons, the transfer gate T21 preferably has a large W / C, that is, a ratio of channel width / capacitance, so that the width of the channel should be larger than the capacitance.

Therefore, the present invention has the advantage that the hot carrier effect is generated only in the transmission gate to prevent deterioration of the MOS transistors to prevent degradation of circuit characteristics.

1 is a logic circuit diagram of a typical two-input NAND gate

2 is a logic circuit diagram of a two input NAND gate capable of preventing hot carrier effects according to an embodiment of the present invention.

Claims (3)

The plurality of first conductive MOS transistors connected in parallel between a power supply voltage terminal and ground and the second conductive MOS transistors connected in series with the same number as the first conductive MOS transistors are connected in series. In a logic gate for inputting the input signal to the gate of the first and second morph transistors of the pair of the two output transistors, respectively, in the output node, A logic circuit for preventing a hot carrier effect in which a transmission gate is connected in series between the output node and a second conductive type MOS transistor adjacent to an output node among the second conductive type MOS transistors. The method of claim 1, And the transfer gate prevents a hot carrier effect in which an input applied to a gate of the adjacent second conductivity type MOS transistor is directly input to a first gate and an input of the second gate is inverted by an inverter. The method of claim 1, And a logic circuit for preventing a hot carrier effect, wherein the first conductivity type is P type and the second conductivity type is N type.