JPH05191243A - Signal transmission circuit and signal transmission control system - Google Patents

Abstract

PURPOSE:To attain the long service life by suppressing production of a hot carrier due to a short channel of a MOS transistor(TR) being a component of a signal transmission circuit in which plural transfer gates are connected in series. CONSTITUTION:A pM0S transistor(TR) Qp1 and an nMOS TR Qn2 are connected in series between input output nodes n1, n3, and the series connection of an nMOS TRQn1 and a pMOS TRQp2 is connected in parallel with the series connection of the TRs Qp1, Qn2. A 1st stage transfer gate TG1 is formed with the TRs Qp1, Qn1 and a 2nd stage transfer gate TG2 is formed with the TRs Qn2, Qp2. A transfer gate TG3 is formed between a node n21 between the TRs Qp1, Qn2 and a node n22 between the TRs Qn1, Qp2. The gate TG3 is turned on after the four TRs Qp1, Qn2 and Qn1, Qp2 are all turned on.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit technique and a technique particularly effective when applied to a MOS integrated circuit having a transfer gate. For example, a signal transmission circuit having a plurality of transfer gates connected in series. Related to useful technology.

[0002]

2. Description of the Related Art As an example of a transfer gate for signal transmission in a MOS integrated circuit, a pair of p-channel M
A CMOS transfer gate is known in which an OS transistor and an n-channel MOS transistor are connected so that their channels are parallel to each other ("LS Issued in 1984".
I Handbook, The Institute of Electronics and Communication Engineers "(Ohmsha) 145
Page Figure 1.34). The transfer gates having such a configuration are connected in series as shown in FIG. 5 (an example of two stages), and a plurality of control signals φ1, φ2, etc. are input to this gate terminal to turn on / off the gate. In some cases, signal transmission / cutoff is controlled.

Furthermore, the delay time at the time of signal transmission of the transfer gate itself having the above structure, that is, the delay time generated when the charges pass through the gate electrode of the MOS transistor forming the transfer gate is positively utilized to obtain a desired delay. It has also been proposed to connect multiple transfer gates in series to form a device.

[0004]

The hot carrier phenomenon is known as one of the factors that shorten the life of the MOS transistor forming the transfer gate or deteriorate the characteristics. It is known that this hot carrier phenomenon is more likely to occur as the channel length of the transistor becomes shorter, and increases as the operating speed of the transistor becomes faster. Therefore, when the transfer gate is used in a recent LSI designed for high integration and high speed, a hot carrier phenomenon is likely to occur in the transistor and the life of the transfer gate tends to be shortened.

As a factor for promoting the shortening of the life of the MOS transistor due to this hot carrier, the MOS
A high voltage is applied between the source and the drain of the transistor, and the potential difference VG between the gate and the source is an intermediate potential. That is, the life (τ) of the element becomes longer in proportion to the reciprocal (1 / Vds) of the potential difference Vds between the source and the drain, and the potential difference VG between the gate and the source becomes the VG.
It is known that the value becomes remarkably short when it is an intermediate potential in the range in which V can fluctuate (for example, between VG1 and VG2 in the graph shown in FIG. 6). Therefore, in order to ensure a long life of the MOS transistor, it is necessary to avoid an operating state in which at least the above conditions are simultaneously satisfied.

However, when a plurality of transfer gates each including a MOS transistor are connected in series as described above (see FIG. 5), the transfer gate that finally transitions to the conductive state, that is, the on state, transitions to the on state. When that is done, that is, when the voltage VG applied to the gate terminal of the MOS transistor is gradually increased in order to transit to the ON state, the transistor always satisfies the above conditions. More specifically, as shown in the column [1] of Table 1, the power supply potential (Vdd) is temporarily applied to the input / output node n31 and the input / output node n33 is grounded to the GND level (0V). Then, first, considering the case where the transfer gate TG1 on the side of the input / output node n31 is turned on, the potential difference between both ends (between n31 and n32) of the transfer gate TG1 is 0 V, so that the voltage of the intermediate node n32 is The power supply voltage value Vdd remains unchanged. At this time, regarding the transfer gate TG2 on the input / output node n33 side, the two transistors Qp32, Qn32
When the gate voltage VG of the transistor Qp32 gradually increases, the voltage Vdd is applied to both ends of each of the transistors Qp32 and Qn32.

[Table 1]

Thus, the gate voltage VG of the transistor is
If the power supply voltage Vdd is applied to both ends of the MOS transistor when the voltage rises, both of the above conditions are satisfied when VG becomes the intermediate potential (VG1 to VG2), and the MOS transistors Qp32 and Qn32 are satisfied. Hot carriers are generated in the gate electrode of, and the life of the transfer gate as a whole is shortened.

On the contrary, as shown in column [2] of Table 1, the transfer gate TG1 is operated in a state where Vdd is applied to the input / output node n33 and the input / output node n31 is grounded to the GND level (0V). When turned on, the voltage of the intermediate nodes n32, n32 becomes 0V. From this state, the MOS transistors Qp32, Q of the transfer gate TG2
When VG of n32 becomes an intermediate potential (VG1 to VG2), the voltage Vdd is applied to both ends of the transistors Qp32, Qn32, so that the above conditions are satisfied at the same time, and the transistors Qn32, Qp32 deteriorate faster,
The life of the transfer gate as a whole is shortened and its reliability is reduced. If the transfer gate TG2 is turned on first, a similar phenomenon occurs on the transfer gate TG2 side, and in this case as well, the life of the transfer gate is shortened.

The present invention has been made in view of the above circumstances. In a signal transfer circuit formed by connecting a plurality of transfer gates in series, the MOS transistor forming the transfer gates has a short channel. Even if there is, the LS has achieved high operating speed and high integration without shortening the life of the transfer gate.
An object of the present invention is to provide a highly reliable signal transfer circuit applicable to I. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, in the signal transmission circuit of the present invention, a plurality of transistors including an n-type MOS transistor and a p-type MOS transistor are connected in series between two input / output nodes to form a first transistor row. Second transistor consisting of the same number of transistors connected in series as
Is formed in parallel with the first transistor array between the input / output nodes, and a plurality of transistors of the first transistor array and the same number of transistors of the second transistor array are provided. An intermediate node, which has a conductivity type different from each other and has a one-to-one correspondence and which connects the transistors of the first transistor row, and an intermediate node of the second transistor row, which corresponds to the intermediate node, are connected via a transfer gate. ..

[0011]

The MOS transistor forming the first transistor row forms a transfer gate in cooperation with the corresponding transistor on the second transistor row side, and the transfer gates are connected in multiple stages in series. A signal transfer circuit is formed. In the multi-stage transfer gates connected in series that constitute this signal transfer circuit, when the gate voltage of the transfer gate that is turned on last rises, at least one of the other transfer gates that are already turned on. Therefore, since there is a transistor that generates a potential difference corresponding to the threshold voltage, the voltage value applied across the transistor that constitutes the transfer gate that is turned on last is equal to the threshold voltage. As a result, the generation of hot carriers in the MOS transistor is suppressed.

[0012]

Embodiments of the present invention will be described below with reference to the accompanying drawings. (First Embodiment) FIG. 1 is a circuit diagram showing the configuration of a signal transmission circuit 100 according to the first embodiment of the present invention. As shown in FIG. 1, the signal transfer circuit 100 includes a first transistor row (MOS transistors Qp1 and Qn2) formed between the input / output nodes n1 and n3 and a second transistor row (parallel to the first transistor row). MOS transistors Qn1, Qp2),
The transfer gate TG3 is arranged between the first intermediate node n21 and the second intermediate node n22. The transistor Qp1 on the first column side and the transistor Qn1 of the different conductivity type on the second column side opposite thereto form the first-stage transfer gate TG1 of the CMOS structure, while the transistor Qn2 on the first column side is formed. And a transistor Qp2 of a different conductivity type on the second column side facing the CMO
The second-stage transfer gate TG2 having the S structure is formed. And the two M's of the first transfer gate TG1
Control pulse φ1, and its inverted output (hereinafter referred to as “φ1′φ2 ′ ...”) φ to the gate terminal of the OS transistor φ
1'is the two MOs of the second transfer gate TG2
The control pulse φ2 and its inverted output φ2 ′ are input to the gate terminal of the S transistor, respectively.

Further, the transfer gate TG3 has the first and second intermediate nodes n21,
n22 is short-circuited so that these two nodes (n21, n22) have the same potential. This transfer gate TG3
Is two MOS transistors (pM
OS transistor Qp3, nMOS transistor Qn
The control pulse .phi.3 and its inverted output .phi.3 'are input to the gate terminals of these transistors, and the on / off control thereof is performed.

Next, the actual operation of the signal transmission circuit 100 having the circuit configuration shown in FIG. 1, especially the transfer gate which is turned on later (the transfer gate TG of the second stage in the illustrated example).
2) will be described with reference to a timing chart shown in FIG.

Now, temporarily, each transfer gate TG1, T
Control pulses φ1 ′, φ2 ′, which are input to G2 and TG3,
Consider a case where φ3 ′ changes at the timing shown in FIG. At this time, if Vdd (V) is applied to the input / output node n1 and the node n3 is grounded, the voltages Vn21, Vn22, Vn3 of the nodes n21, n22, n3 in FIG.
The value changes as shown in.

Specifically, the power supply voltage Vd is applied to the input node n1.
When d is applied (Vn1 = Vdd) and the output node n3 is grounded to the GND level (Vn3 = 0V), the time when the pulse φ1 'rises (time t1 in FIG. 2).
Then, the voltage value Vn21 of the node n21 changes to Vdd, and the voltage value Vn22 of the node n22 changes to Vdd-VTHn.

Thus, (n1 is Vdd [V], n3 is 0 [V]
In addition, the voltage value of n22 becomes Vdd-VTHn when the transfer gate TG1 is already turned on (state shown in the upper column [1] of Table 2) for the following reason. That is, it is not required that a large potential difference be generated between the source and the drain under the condition that the current flows through the transistor Qp1 forming the transfer gate TG1 in the first stage,
With respect to the nMOS transistor Qn1, it is necessary that the potential difference between the gate and the drain be equal to or higher than the threshold voltage VTHn in order for the transistor Qn1 to actually turn on and the current to flow therethrough ( In other words, between the source and drain of the transistor Qn1 (n1
(Between n21 and n21) VTHn is required). Thus, at the time point when φ2 'rises (time point t2 in FIG. 2), the potential of the intermediate node n22 becomes Vdd-VTHn, and the transfer gate TG2 that is turned on later has the gate of the pMOS transistor Qp2. When the voltage VG is gradually increased and turned on, the transistor Qp
The potential difference between both ends (between n22 and n3) of 2 is reduced by VTHn to become Vdd-VTHn (between t1 and t2 in FIG. 2).

[Table 2]

Further, each transfer gate TG1, TG
2, when each control pulse is input to TG3 at the same timing, when the input / output node n1 is grounded to the GND level and the power supply voltage Vdd is applied to the node n3, each node n21, n22, n1 voltage Vn21, Vn22,
The value of Vn1 changes as shown in FIG. That is, when the pulse φ1 'rises (time t1'), the voltage value Vn21 of the node n21 becomes VTHp, and the voltage value Vn of the node n22 becomes VTHp.
n22 changes to 0V. This is this state (n1 is 0
[V] and n3 are Vdd [V], and the transfer gate TG1 of the first stage is already turned on; in the state shown in the lower column [2] of Table 2), the transistors Qn1 and Qn
Although it is not required that a potential difference be generated between the source and the drain as a condition for the current to flow through p1, the transistor Qp
Regarding No. 1, it is necessary for the potential difference between the gate and the source to be equal to or higher than the threshold voltage VTHp in order for the transistor Qp1 to be actually turned on and for the current to flow there. For example, the voltage difference between the source and drain (between n1 and n21) of the transistor Qp1 requires VTHp). Therefore, in this case, the voltage of the intermediate node n21 is V
Transfer gate TG that becomes THp and is turned on later
When the gate voltage VG of the second transistor Qn2 is gradually increased and turned on, the potential difference between both ends (between n3 and n21) of the transistor Qn2 decreases by VTHp on the GND side, and Vdd- VTHp (Fig. 3
T1'-t2 ').

As described above, the transfer gate transistor (transistor Qp) that is turned on later is selected from the four transistors forming the signal transmission circuit 100.
2, Qn2), the probability that the power supply voltage Vdd is applied to which of the input / output nodes n1 and n3 of the signal transmission circuit is 1/2, and the potential difference between the source and drain when the gate voltage rises, respectively. Can be lowered.

In this way, the gate voltage rises and the MOS
When the transistor is turned on, the voltage applied between the source and drain of the transistor is VTHn or VTHp.
If it is lowered only, the following action and effects are produced.
That is, as described above, the degree of deterioration due to hot carriers exponentially increases with respect to the potential difference Vds generated between the source and the drain. The gate voltage VG is at an intermediate potential (VG
1 to VG2), the potential difference between the source and drain is decreased by VTH (= VTHn, VTHp) when the gate VG is gradually increased as described above. In comparison with the transfer gate having the above structure (FIG. 5), the life can be extended practically enough.

The above-described operation for reducing hot carriers (the transfer gate TG3 is turned off) is turned on later in the signal transmission circuit 100 (2).
(Stage) It is necessary only until the transfer gate is actually turned on. Therefore, after the transfer gate TG2 of the second stage is turned on, the transfer gate TG3
Is turned on to bring the intermediate nodes n21 and n22 into a short-circuited state (after time t3 in FIG. 2 and after time t3 ′ in FIG. 3). This is because if the intermediate nodes n21 and n22 remain separated, node n3
2 fluctuates, that is, in the example of FIG. 2, Vdd is applied to the source terminals of the transistors Qn1 and Qn2, and the threshold voltage (VTHn) output decreases, and in the example of FIG. 3, the transistors Qp1 and Qp2. 2 is grounded, and the threshold voltage (VTHp) output decreases (between t2 and t3 in FIG. 2 and t2 'to t3' in FIG. 3). Therefore, it is possible to prevent the final output from decreasing by VTH by short-circuiting between the nodes n21 and n22.
The on timing of the transfer gate TG3 (the rising timing of the inverted output φ3 ′) is the same as the signal transmission circuit 10
The gate voltage of the transistors Qp2 and Qn2 of the transfer gate TG2 of the second stage of 0 is sufficiently raised to turn it on,
It is assumed to be after the time when the off state is confirmed (the time when hot carriers are no longer generated).

Control pulses for the signal transmission circuit 100 (pulse φ1, inverted output φ1 ', pulse φ2, inverted output φ
In 2 '), the generation timing is changed according to the operation control content of a circuit (for example, a flip-flop circuit) to which the circuit 100 is applied. On the other hand, the control pulse of the transfer gate TG3 (φ3, inverted output φ
3 ') is irrelevant to the operation of the applied circuit, and its fall / rise timing is, for example, on condition that both the transfer gates TG1 and TG2 of the first and second stages are turned on. After the two pulse signals of the inverted output φ1 'and the inverted output φ2' are both turned on and both transistors are turned on, or after both are turned on, a predetermined time has elapsed. At that time, the timing may be appropriately set so that the transfer gate TG3 is turned on.

In the above description of the operation, the case in which the transfer gate TG1 in the first stage is turned on and then the transfer gate TG2 in the second stage is turned on has been described. Conversely, the transfer gate TG2 in the second stage is turned on first. Similarly, when turned on, the hot carriers of the transistor forming the first-stage transfer gate TG1 can be reduced.

(Second Embodiment) FIG. 4 is a circuit diagram showing a structure of a signal transmission circuit 200 according to a second embodiment of the present invention. As shown in FIG. 4, the signal transmission control means 200 includes a first transistor array (MOS transistors Qp11, Qn12, Qp1) formed between input / output nodes n11, n14.
3) and a second transistor array (MOS transistors Qn11, Qp12, Qn1) connected in parallel with this.
3), the first intermediate node n121 and the second intermediate node n122
And a transfer gate TG25 arranged between the third intermediate node n131 and the fourth intermediate node n132.

The transistor Qp11 on the first column side and the transistor Qn1 of a different conductivity type on the second column side opposite to the transistor Qp11.
1 and the transfer gate TG of the first stage of the CMOS structure
21 is formed, and the transistor Qn12 on the first column side and the transistor Qn of a different conductivity type on the second column side opposite to the transistor Qn12.
The second stage transfer gate TG2 of the CMOS structure is formed with p12, and the transistor Qp on the first column side is further formed.
A transfer gate TG23 of the third stage of the CMOS structure is formed by 13 and the transistor Qn13 of the different conductivity type on the side of the second column facing the same. The control pulse φ11 and its inverted output φ1 are applied to the gate terminals of the two MOS transistors of the first transfer gate TG21, respectively.
1'is the two M's of the second transfer gate TG22.
Control pulse φ1 to each gate terminal of the OS transistor
The control pulse φ13 and its inverted output φ13 ′ are input to the gate terminals of the two MOS transistors of the third transfer gate TG23.

The transfer gates TG24, TG25 arranged between the respective intermediate nodes are converted into the ON state so as to have the first and second intermediate nodes n121, n122 and the third and fourth intermediate nodes n131, n132. Are short-circuited to make the two nodes have the same potential. These two transfer gates TG24, TG25 are each composed of two MOS transistors connected in parallel, and the gate terminals of these transistors have a control pulse φ14 and its inverted output φ14 ′, a control pulse φ15 and its inverted output φ1.
5'is input to control ON / OFF of each.

The signal transmission control means 2 configured as described above
00, the power supply voltage Vdd is temporarily applied to the node n11 side, and the transfer gates T of the first and second stages are transferred.
When both G21 and 22 are turned on, the transistor Qn12 causes a potential difference corresponding to VTH in the upper array (first column), while the transistor Qn11 corresponds to VTH in the lower array (second column). Is generated, the voltage applied to both ends of the two transistors Qp13 and Qn13 forming the transfer gate TG23 of the last stage (third stage) that is finally turned on is V.
These two transistors Qp13, Q are lowered by TH.
Generation of hot carriers is suppressed by n13.

On the contrary, when the power supply voltage Vdd is applied to the node n14 side and the transfer gates in the first and second stages are both turned on, the transistor Qp11 is connected to VTH in the upper array (first column). On the other hand, in the lower array (second column), the transistor Q
Since p12 causes a potential difference corresponding to VTH,
Also in this case, the last stage (3rd stage) that is finally turned on
The generation of hot carriers is suppressed by the two transistors Qp13 and Qn13 that form the transfer gate TG23.

As described above, the three MOS transistors are connected in series, and the MOS transistors connected in series are connected to each other of different conductivity types. The power supply voltage Vdd is applied to the input / output nodes n11 and n14 of the transistors of the gates (TG21 and TG22) of each stage, that is, Qp11 and Qn12 and Qn11 and Qp12 of FIG.
Regardless of which is applied to the
The nMOS transistor to which dd [V] is applied and the pMOS transistor whose drain terminal is 0 [V] must be 1
Since there are individual transfer gates that turn on last
In G23, the potential difference between the source and drain is Vdd-VTH
Therefore, the influence of hot carriers can be suppressed.

Furthermore, as described above, the 3 included in one column
Two MOS transistors (eg Qp11 in the first column,
Qn12 and Qp13) must include p-type and n-type transistors, the power supply voltage V generated when all the transistors of the same conductivity type form a line.
It is possible to prevent the substrate bias of the MOS transistor located on the dd side from dropping or the current feedback from occurring due to the MOS transistor located on the ground side (0 V side), and prevent the performance of the entire signal transmission circuit from deteriorating.

In the above description of the operation, the case where the transfer gate TG23 of the third stage is turned on lastly has been illustrated, but the above-mentioned effects are obtained first by the transfer gates TG22, 23 of the second and third stages. When the transfer gate TG21 of the first stage is turned on last while it is turned on, or when the transfer gates of the first and third stages are turned on first, the transfer gate TG21 of the second stage is finally turned on. Even when the transfer gate TG22 is turned on, the same operation and effect can be obtained.

As described above, in the signal transmission circuit of the above-mentioned embodiment, the plurality of transistors including the n-type MOS transistor and the p-type MOS transistor are connected in series between the input / output nodes to form the first transistor. A column is formed, and a second transistor column composed of the same number of transistors connected in series is formed between the input / output nodes in parallel with the first transistor column, and A plurality of transistors and the same number of transistors in the second transistor row correspond to each other in different conductivity types one to one, and an intermediate node connecting the transistors in the first transistor row and a corresponding intermediate node. The intermediate node of the second transistor array is connected via the transfer gate, and the first node
Each of the transistors forming the transistor array of 1 forms a transfer gate in cooperation with the corresponding transistor of the second transistor array, and as a whole, a signal transfer circuit in which the transfer gates are connected in multiple stages in series is formed. To be done. The multi-stage series transfer gate that constitutes this signal transfer circuit is at least one of the plurality of other transfer gates that are already turned on when the transfer gate that is turned on last is turned on,
There is at least one transistor that generates a potential difference corresponding to the threshold voltage, and the voltage value applied across the transistor of the transfer gate that is turned on last is decreased by the threshold voltage, The MOS
Generation of hot carriers in the transistor is suppressed.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in each of the above embodiments, the signal transmission circuit 100 in which the first and second transistor rows connected in parallel with each other are formed by connecting two transistors in series, respectively, and the first and second transistor rows are formed. Although the signal transmission circuit 200 formed by connecting three transistors in series has been exemplified, each of the transistor rows forming the signal transmission circuit is also formed by connecting four or more transistors in series. The invention can be applied.

[0034]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. It is possible to suppress the shortening of the life of a signal transmission circuit formed by a MOS transistor having a short channel due to the shortening of the channel and to operate the signal transmission circuit at a high speed.
A highly reliable configuration applicable to SI and the like can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a signal transmission circuit 100 according to a first embodiment.

FIG. 2 is a signal transmission circuit 10 in which Vdd is applied to a node n1.
6 is a timing chart showing the generation timing of a control pulse input to the 0 gate terminal and the voltage at each node.

FIG. 3 is a timing chart showing a voltage change state at each node of the signal transmission circuit 100 in which the node n1 is grounded and is at the GND level.

FIG. 4 is a circuit diagram showing a configuration of a signal transmission circuit 200 according to a second embodiment.

FIG. 5 is a circuit diagram showing a configuration of a conventional signal transmission circuit 300 in which transfer gates are connected in two stages in series.

FIG. 6 is a graph showing the relationship between the value of the gate voltage VG and the logarithmic value of the life τ of the MOS transistor.

[Explanation of symbols]

 100 signal transmission circuit Tg1, Tg2, TG3 transfer gate Qp1 to Qp3 pMOS transistor Qn1 to Qn3 nMOS transistor φ1 to φ3, φ1 'to φ3' control pulse VTHp, VTHn threshold voltage

Claims (3)

[Claims] 1. A plurality of transistors including an n-type MOS transistor and a p-type MOS transistor are connected in series between two input / output nodes to form a first transistor row, and the same number of the transistors are connected in series. A second transistor string composed of connected transistors is formed in parallel with the first transistor string between the input / output nodes, and a plurality of transistors of the first transistor string and the same number of second transistors are formed. The transfer gates of the intermediate node connecting the transistors of the first transistor row and the corresponding intermediate node of the second transistor row corresponding to each other in one-to-one correspondence with the transistors of the other transistor row. A signal transmission circuit characterized by being connected via. 2. The transfer gate connected between the intermediate nodes facing each other is composed of an n-type MOS transistor and a p-type MOS transistor connected in parallel.
The signal transfer circuit according to claim 1, wherein the signal transfer circuit is a MOS type transfer gate. 3. The transfer gate connected between the intermediate nodes according to claim 1 or 2, wherein the transfer gate is turned on after all the transistors forming the first and second transistor rows are turned on. And signal transmission control method.