KR19980086530A - Level converter, output circuit and input / output circuit - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a level converter which is operated stably even when there is a time difference between the input timings of a plurality of power supply voltages in a semiconductor device operating with a plurality of power supply voltages.

The level converter includes a level converter 101 having an input buffer circuit 100 and an output holding circuit 102. The input buffer circuit 100 outputs the pair of buffer signals X1 and X2 to the level converter 101 by the binary input signal A having an amplitude based on the low voltage power supply. The level converting unit 101 converts the binary input signal A into a binary output signal Y having an amplitude by a high voltage power supply based on the buffer signals X1 and X2 and outputs it. The output holding circuit 102 outputs the binary output signal Y by the potential difference between the buffer signals X1 and X2 when the buffer signals X1 and X2 become in an indefinite state.

Description

Level converter, output circuit and input / output circuit

The present invention relates to a level converter for use in a semiconductor device operating with a plurality of power supply voltages.

In recent years, in order to achieve low power consumption, semiconductor devices have been provided with circuits operating at different power supply voltages, and supplying power supply voltages to each circuit as necessary. A level converter is used as an interface between circuits having different power supply voltages, and high reliability is required for its operation.

10 shows an output portion of a semiconductor device operating with two kinds of power supply voltages. The signal A output from the internal circuit 50 operating at a power supply voltage of 3v is inputted to the level converter 51 and inverted by the inverter 52 and inputted to the level converter 51 as a signal A bar. Therefore, the signals A and A are signals whose one side is ground GND and the other 3v.

When the signal A and the inverted signal A bar are input to the level converter 51, the signal A is converted into a signal B whose amplitude becomes 5v from the ground level and output. The signal B is buffered by the CMOS inverter 53 which operates at a power supply voltage of 5v composed of the P-channel MOS transistor Tr1 and the N-channel MOS transistor Tr2 and is output from the output terminal 54.

11 shows a conventional level converter 51. A power supply voltage of 5v is supplied to the sources of the P-channel MOS transistors Tr3 and Tr5. The drain of the transistor Tr3 is connected to the drain of the N-channel MOS transistor Tr4, and the drain of the transistor Tr5 is connected to the drain of the N-channel MOS transistor Tr6. Sources of the transistors Tr4 and Tr6 are connected to ground GND.

The drains of the transistors Tr3 and Tr4, i.e., the node N1, are connected to the gates of the transistors Tr5, and the drains of the transistors Tr5 and Tr6, i.e., the nodes N2, are gates of the transistors Tr3. Is connected to. The node N2 is connected to the gate of the CMOS inverter 55 which operates at a power supply voltage of 5v constituted by the P-channel MOS transistor Tr7 and the N-channel MOS transistor Tr8.

The signal A is input to the gate of the transistor Tr6, and the signal A bar is input to the gate of the transistor Tr4. The signal B is then output from the drain of the CMOS inverter 55. In addition, the transistors Tr4 and Tr6 have a larger current driving capability than the transistors Tr3 and Tr5.

In the level converter 51 configured as described above, when the signal A becomes the H level 3v and the signal A bar becomes the L level (ground level), the transistor Tr6 is turned on and the transistor Tr4 is turned off. The transistor Tr3 is turned on and the transistor Tr5 is turned off. At this time, the node N2 is at the L level (ground level), and the signal B of the H level 5v is output from the CMOS inverter 55.

When signal A becomes L level (ground level) and signal A bar becomes H level 3v, transistor Tr6 is turned off and transistor Tr4 is turned on. The transistor Tr5 is turned on and the transistor Tr3 is turned off. At this time, the node N2 is at the H level 5v, and the signal B at the L level (ground level) is output from the CMOS inverter 55.

Therefore, the level converter 51 converts the signals A and A bars whose amplitude is 3v from the ground level into signals B whose amplitudes are 5v from the ground level and outputs them.

However, in a semiconductor device operating with a plurality of power supply voltages, when a power supply voltage of a plurality of voltage values is supplied into a circuit, the power supply device generally generates a low voltage from a high voltage. It is supplied first.

When a power supply voltage of 3v and a power supply voltage of 5v are supplied into the circuit, for example, as shown in Fig. 12, a power supply voltage of 3v is supplied after several microseconds (microseconds) after the 5v power supply voltage is supplied. During a few microseconds when the power supply voltage of 5v is supplied and the power supply voltage of 3v is not supplied, all signals in the circuit operating at the power supply voltage of 3v can be regarded as being in the L level.

When the signal A and the signal A bar, which are signals from a circuit operating at a power supply voltage of 3v, are both at L level, a state in which a power supply voltage of 5v is supplied to the level converter 51 occurs.

In this case, since the power supply voltage of 5v is supplied to the drains of the transistors Tr3 and Tr5 while the transistors Tr4 and Tr6 are turned off together, the nodes N1 and N2 may become intermediate potentials.

Therefore, there is a problem that the input of the CMOS inverter 55 becomes an intermediate potential, the transistors Tr7 and Tr8 are turned on together, and a through current flows from the power supply to the ground GND.

The output signal B of the level converter 51 also becomes an intermediate potential, and the transistors Tr1 and Tr2 are turned on together so that a through current flows from the power supply to the ground GND. As the transistors Tr1 and Tr2, transistors having a large load driving capability are used. Therefore, the through current flowing through the transistors Tr1 and Tr2 becomes a very large current value of several tens to several hundred milliamps. Therefore, there is a problem that power consumption increases. It may also cause malfunction due to latch-up.

SUMMARY OF THE INVENTION An object of the present invention is to provide a level converter which operates stably even when there is a time difference in the timing of inputting a plurality of power supply voltages in a semiconductor device operating in a plurality of power supply voltages.

1 is an explanatory view of the principle of the present invention.

Fig. 2 is a circuit diagram showing a level converter of the first embodiment.

Fig. 3 is a circuit diagram showing the level converter (initial value 1) of the second embodiment.

Fig. 4 is a circuit diagram showing a level converter (initial value 0) of another example of the second embodiment.

Fig. 5 is a circuit diagram showing a level converter (initial value 0) of the third embodiment.

Fig. 6 is a circuit diagram showing a level converter (initial value 1) of another example of the third embodiment.

Fig. 7 is a circuit diagram showing a pullup resistor control output circuit of a fourth embodiment.

Fig. 8 is a circuit diagram showing an input / output circuit of the fifth embodiment.

Fig. 9 is a circuit diagram showing another example of the input / output circuit of the fifth embodiment.

10 is a circuit diagram showing an output unit.

11 is a circuit diagram showing a conventional level converter.

Fig. 12 is a waveform diagram showing a difference of input time of a power supply voltage.

1 is an explanatory view of the principle of the invention described in claim 1. In other words, the level converter includes a level converter 101 having an input buffer circuit 100 and an output holding circuit 102. The input buffer circuit 100 outputs the pair of buffer signals X1 and X2 to the level converter 101 by the binary input signal A having an amplitude based on the low voltage power supply. The level converting unit 101 converts the binary input signal A into a binary output signal Y having an amplitude by a high voltage power supply based on the buffer signals X1 and X2 and outputs it. The output holding circuit 102 outputs the binary output signal Y by the potential difference between the buffer signals X1 and X2 when the buffer signals X1 and X2 become negative.

In the level converter according to claim 1, in the level converter according to claim 1, the output holding circuit and the level converting section are configured such that an input terminal and an output terminal of the first and second CMOS inverters operating with a high voltage power supply are connected to each other.

In the input buffer circuit, a first input transistor is connected in series between the output terminal of the first CMOS inverter and the low potential side power supply, and the second buffer is connected between the output terminal and the low potential side power supply of the second CMOS inverter. The input transistors are connected in series, and the buffer signal is output by turning on either one of the first and second input transistors based on the binary input signal.

The output holding circuit is provided with an initial value setting circuit for setting an initial value of the binary output signal when the high voltage power is turned on.

In the initial value setting circuit, the output terminal of either of the first and second CMOS inverters is connected to either the high potential power source or the full potential source power supply via a capacitance.

6. The initial value setting circuit according to claim 5, wherein the initial value setting circuit comprises: an initial value setting transistor interposed between an output terminal of any one of the first and second CMOS inverters, and either one of a high potential side power supply and a low potential side power supply; And a reset signal output circuit for turning on the initial value setting transistor for a predetermined time in response to the power supply.

The initial value setting circuit of claim 6, wherein the threshold voltages of the first and second CMOS inverters are different from each other.

The initial value setting circuit of claim 7, wherein the initial value setting circuit comprises the first and second CMOS inverters having different values of the capacitance and the threshold voltage.

In Claim 8, based on the binary output signal of the level converter as described in any one of Claims 1-7, the output circuit which drives an output buffer circuit is made into the summary.

In the ninth aspect of the present invention, there is provided an output circuit for opening and closing a pull-up control transistor connected to a high potential power supply via a resistance based on the binary output signal of the level converter according to any one of claims 3 to 7.

The output mode for outputting the output signal from the output buffer circuit and the output signal of the output buffer circuit in an indeterminate state based on the binary output signal of the level converter according to any one of claims 3 to 7. The input / output circuit in which the input mode is switched is made into a summary.

According to the invention of claim 1, the output holding circuit 102 outputs the binary output signal Y based on the potential difference between the buffer signals X1 and X2 when the buffer signals X1 and X2 become in an indeterminate state. Therefore, the circuit operates normally even when the buffer signals X1 and X2 become negative.

According to the invention of claim 2, the binary output signal is output from the first and second CMOS inverters by turning on either one of the first and second input transistors based on the binary input signal. The first and second CMOS inverters operate to enlarge the potential difference when there is a small potential difference in the output terminal. Therefore, when the buffer signal becomes in an indeterminate state, one of the output terminals is H level, and the other is L. It becomes a level. Therefore, the binary output signal is surely output.

According to the invention of claim 3, the initial value setting circuit sets the initial value of the binary output signal at the time of high voltage power supply. Therefore, when the high voltage power supply is turned on, the binary output signal of the set initial value is output from the output holding circuit.

According to the invention of claim 4, the capacitance connected to the high potential power source acts to raise the potential of the connected output terminal when the high voltage power source is turned on. The capacitance connected to the low potential side power supply acts to lower the potential of the connected output terminal when the high voltage power supply is turned on. Therefore, the initial value of the binary output signal output when the high voltage power is turned on while the buffer signal is in an indeterminate state is determined to either of the binary output signals.

According to the invention of claim 5, the reset signal output circuit outputs the reset signal for a predetermined time when the high voltage power supply is turned on. The initial value setting transistor connected to the high potential power supply is turned on based on the reset signal when the high voltage power supply is turned on, thereby acting to raise the potential of the CMOS inverter output terminal. The initial value setting transistor connected to the low potential side power supply is turned on based on the reset signal when the high voltage power supply is turned on, thereby acting in such a manner as to lower the potential of the output terminal of the CMOS inverter. Therefore, the initial value of the binary output signal output when the high voltage power is turned on while the buffer signal is in an indeterminate state is determined to either of the binary output signals.

According to the invention of claim 6, when the high voltage power is supplied to the CMOS inverter having the low threshold voltage and the CMOS inverter having the high threshold voltage, the CMOS inverter having the low threshold voltage first outputs the H level, so that the buffer signal is undefined. In the state, the initial value of the binary output signal outputted when the high voltage power supply is turned on is determined as one of the binary output signals.

According to the invention of claim 7, when a high voltage power source is applied to a CMOS inverter having a low threshold voltage and a CMOS inverter having a high threshold voltage, the CMOS inverter having a low threshold voltage first outputs an H level. In addition, the initial value is reliably determined.

According to the invention of claim 8, since the output buffer circuit is driven based on the binary output signal of the level converter according to any one of claims 1 to 7, the output circuit operates normally.

According to the invention of claim 9, since the pull-up control transistor connected to the high potential side power supply via a resistor opens and closes based on the binary output signal of the level converter according to any one of claims 3 to 7, a buffer signal. Is set to the initial state of the pull-up when the high-voltage power is turned on in the negative state.

According to the invention of claim 10, the output mode of the output mode and the output buffer circuit outputting the output signal from the output buffer circuit based on the binary output signal of the level converter according to any one of claims 3 to 7. Since the input mode to be in a negative state is switched, the initial state of the mode when the high voltage power is turned on is set.

EXAMPLE

(First embodiment)

2 shows a first embodiment of a level converter incorporating the present invention.

The output terminal of the first CMOS inverter 2 composed of the P-channel MOS transistor Tr11 and the N-channel MOS transistor Tr12 is the second CMOS composed of the P-channel MOS transistor Tr13 and the N-channel MOS transistor Tr14. It is connected to the input terminal of the inverter 3. The output terminal of the second CMOS inverter 3 is connected to the input terminal of the first CMOS inverter 2. In this embodiment, the first and second CMOS inverters 2 and 3 constitute an output holding circuit and a level converter.

The output terminal of the first CMOS inverter 2 is connected to the drain of the first input transistor Tr15 composed of the N-channel MOS transistors, and the output terminal of the second CMOS inverter 3 has a second input composed of the N-channel MOS transistors. It is connected to the drain of the transistor Tr16. Sources of the first and second input transistors Tr15 and Tr16 are connected to ground GND. In this embodiment, the first and second input transistors Tr15 and Tr16 form an input buffer circuit.

The output terminal of the second CMOS inverter 3, that is, the node N3, is connected to the input terminal of the second CMOS inverter 4 composed of the P-channel MOS transistor Tr17 and the N-channel MOS transistor Tr18. . In the present embodiment, the first to third CMOS inverters 2, 3, and 4 are supplied with 5v of high voltage power. The current driving capability of the transistors Tr15 and Tr16 is set to be larger than the current driving capability of the transistors Tr11 and Tr13.

An input signal A, which is a binary input signal, is input to the gate of the transistor Tr16, and an inverted signal A bar of the input signal A is input to the gate of the transistor Tr15. The input signals A and A are output from an internal circuit operating with a power supply of 3v which is a low voltage power supply, and their amplitude is in the range from ground level to 3v.

In the level converter 1 configured as described above, when the input signal A becomes H level 3v and the input signal A bar becomes L level (ground level), the transistor Tr16 is turned on and the transistor Tr15 is turned off. In this case, the transistor Tr11 is turned on and the transistor Tr12 is turned off, and the transistor Tr14 is turned on and the transistor Tr13 is turned off. At this time, the node N3 is at an L level (ground level), and an L level (ground level) as a binary output signal is input to the third CMOS inverter 4, and the H level 5v is input from the third CMOS inverter 4. Is output.

When the input signal A becomes L level (ground level) and the input signal A bar becomes H level 3v, the transistor Tr16 is turned off and the transistor Tr15 is turned on. In this case, the transistor Tr13 is turned on and the transistor Tr14 is turned off, and the transistor Tr12 is turned on and the transistor Tr11 is turned off. At this time, the node N3 is at the H level 5v, and the H level 5v as a binary output signal is input to the third CMOS inverter 4, and the L level (ground level) is input from the third CMOS inverter 4. Output signal B is outputted.

Therefore, in this level converter 1, the input signals A and A whose amplitude is 3v from the ground level are converted into the output signal B whose amplitude is 5v from the ground level.

If 5v of power is supplied before power supply of 3v at the time of supplying power to the semiconductor device with the level converter 1, the input signals A and A are both L level, but the level converter 1 is 5v. Power is supplied.

In this case, the transistors Tr15 and Tr16 are turned off together, but by supplying 5v of power to the level converter 1, the first and second CMOS inverters 2 and 3 have a slight potential difference to their output terminal voltages. If is present, the potential difference is increased so that the output terminal voltage becomes H level on one side and L level on the other. Therefore, the node N3 becomes either the L level (ground level) or the H level 5v, and either output signal from the third CMOS inverter 4 is either the H level 5v or the L level (ground level). B is output.

Next, the characteristic effects in the first embodiment as described above are described below.

(1) In the level converter 1 of the present embodiment, when the power supply voltage of 5v is input when the input signals A and A are both at the L level, the output holding circuit composed of the first and second CMOS inverters 2 and 3 is provided. Thus, the node N3 is either at the L level (ground level) or at the H level 5v. Therefore, in the level converter 1, no through current flows from the power supply to the ground GND, and the output signal B does not become an intermediate potential. As a result, normal operation of the circuit is ensured while lowering the power consumption of the semiconductor device.

(2nd Example)

3 shows a second embodiment. In the level converter 10 of the second embodiment, the first and second capacitors C1 and C2 are added to the level converter 1 of the first embodiment, and the same components as in the first embodiment are denoted by the same reference numerals. The description is omitted.

The output terminal of the first CMOS inverter 2, that is, the node N4, is connected to a power supply of 5v through the first capacitor C1. The node N3 is connected to the ground GND through the second capacitor C2. In this embodiment, the first and second capacitors C1 and C2 connected in this way constitute an initial value setting circuit.

In the level converter 10 configured as described above, in the same operation as the level converter 1 of the first embodiment, the input signal A whose amplitude is 3v from the ground level is converted into the output signal B whose amplitude is 5v from the ground level. do.

If 5v of power is supplied prior to supply of 3v at the time of supplying power to the semiconductor device with the level converter 10, the input signals A and A are both L level, but the level converter 10 has 5v of power. Power is supplied.

When the transistors Tr15 and Tr16 are turned off together, when the power supply voltage of 5v is input to the level converter 10, the first and second capacitors C1 and C2 cause a coupling phenomenon. This coupling phenomenon works by raising the level of the node N4 toward the H level and by pulling the level of the node N3 toward the L level.

By operating the first and second CMOS inverters 2 and 3 in this state, the node N3 becomes L level (ground level) and the output signal of the H level 5v from the third CMOS inverter 4. B is output. That is, the initial value of the level converter 10 when the power is turned on and the transistors Tr15 and Tr16 are turned off together becomes one.

The characteristic effects in the second embodiment as described above are described below.

(1) In the level converter 10 of the present embodiment, when the power supply voltage of 5v is input when the input signals A and A are both at the L level, in addition to the same operation as in the first embodiment, the first and the first Due to the coupling phenomenon caused by the two capacitors C1 and C2, the signal held in the holding circuit becomes a constant value, and the output signal B becomes the H level 5v. Therefore, in addition to the effect of the first embodiment, the initial value of the level converter 10 when the transistors Tr15 and Tr16 are both turned off can be set to one. As a result, the circuit operation of the next stage can be reliably controlled.

The second embodiment may be modified as follows.

As shown in Fig. 4, the node N4 may be connected to the ground GND via the first capacitor C1, and the node N3 may be connected to the power supply of 5v via the second capacitor C2.

In the level converter 15 connected in this manner, the signal held in the holding circuit becomes a constant value similarly to the level converter 10 of the second embodiment, and the output signal B becomes L level (ground level). Therefore, in addition to the effects of the first embodiment, the initial value of the level converter 15 at the time of power supply can be set to zero. As a result, the circuit operation of the next stage can be reliably controlled.

(Third Embodiment)

5 shows a third embodiment. In the level converter 20 of this third embodiment, the initial value setting transistor Tr20 and reset signal output circuit 21 constituted of N-channel MOS transistors are added to the level converter 1 of the first embodiment. The same components as those in the first embodiment will be denoted by the same reference numerals and description thereof will be omitted.

The output terminal of the first CMOS inverter 2, that is, the node N4, is connected to the drain of the N-channel MOS transistor tr20. The source of the transistor Tr20 is connected to ground GND. The gate of the transistor Tr20 is connected to the reset signal output circuit 21. In this embodiment, the transistor Tr20 and the reset signal output circuit 21 connected in this way constitute an initial value setting circuit.

The reset signal output circuit 21 is a circuit which operates at a power supply voltage of 5v and outputs, as a reset signal, a pulse signal that becomes H level for a predetermined time when the power is turned on. In addition, the pulse width of the reset signal is set at a time sufficient to ensure that the potential of the node N4 is lower than the node N3 at a low level based on the on operation of the transistor Tr20 after the power is turned on.

In the level converter 20 configured as described above, in the same operation as the level converter 1 of the first embodiment, the input signal A whose amplitude is 3v from the ground level is converted into the output signal B whose amplitude is 5v from the ground level. do.

If 5v of power is supplied prior to supply of 3v of the power supply to the semiconductor device with the level converter 20, the input signals A and A are both L level, but the level converter 20 has 5v of power. Power is supplied.

When the transistors Tr15 and Tr16 are turned off together, when a power supply voltage of 5v is applied to the level converter 20, a reset signal is output from the reset signal output circuit 21, and the transistor Tr20 is supplied. Comes on. The node N4 then becomes lower than the node N3.

By operating the first and second CMOS inverters 2 and 3 in this state, the node N4 becomes the L level (ground level), the node N3 becomes the H level 5v, and the third CMOS inverter 4 ) Outputs an output signal B of L level (ground level). That is, the initial value of the level converter 20 when the power is turned on and the transistors Tr15 and Tr16 are turned off together is zero.

The characteristic effects in the third embodiment as described above are described below.

(1) In the level converter 20 of the present embodiment, when the power supply voltage of 5v is input when the input signals A and A are both at the L level, the transistor Tr20 is turned on so that the node N4 is turned on by the node N3. Since it is pulled down further, the node N4 becomes L level (ground level), the node N3 becomes H level 5v by the operation of the holding circuit, and the output signal B becomes L level (ground level).

Therefore, in addition to the effects of the first embodiment, the initial value of the level converter 20 when the transistors Tr15 and Tr16 are both turned off can be zero. As a result, the circuit operation of the next stage can be reliably controlled.

(2) In the level converter 20 of the present embodiment, the transistors Tr20 and the reset signal output circuit 21 are provided without requiring the first and second capacitors C1 and C2 of the second embodiment. You can set the initial value in one configuration. In addition, since a power-on reset circuit is often built in a general semiconductor device, the reset signal output circuit 21 does not need to be particularly provided. Therefore, the area occupied by the level converter 20 in the layout area of the semiconductor device can be reduced.

The third embodiment may be modified as follows.

As shown in Fig. 6, the drain of the transistor Tr20 may be connected to the node N3.

In the connected level converter 25, since the transistor Tr20 is turned on in the same operation as the level converter 20 of the third embodiment, and the node N3 is pulled down than the node N4, the output signal B is It becomes H level 5v. Therefore, in addition to the effect of the first embodiment, the initial value of the level converter 25 at the time of power supply can be set to one. As a result, the circuit operation of the next stage can be reliably controlled. In addition, the same effects as in the effect (2) of the third embodiment can be obtained.

(Example 4)

Fig. 7 shows a fourth embodiment in which the present invention is embodied as a pull-up resistance control output circuit. Since the output circuit of the pull-up claim control uses the level converter 10 of the second embodiment, the description of the operation of the level converter 10 is omitted.

The control signal P from the internal circuit 50 operating at the power supply voltage of 3v is inputted to the level converter 10 and inverted at the inverter 31 operating at the power supply voltage of 3v and is converted to the level converter 10 as the signal P bar. ) Is entered.

In the level converter 10, signals P and P bars whose amplitude is 3v from the ground level are converted into signals Q having an amplitude of 5v from the ground level.

The signal Q output from the level converter 10 is input to the gate of the pull-up control transistor Tr30 constituted of the P-channel MOS transistor. The source of the transistor Tr30 is connected to the power supply of 5v through the resistor R, and the drain of the transistor Tr30 is connected to the external terminal 32. In this embodiment, the pull-up resistor control output circuit is composed of the level converter 10, the resistor R and the transistor Tr30.

In the pull-up resistor control output circuit configured as described above, when the control signal P becomes L level (ground level) and the signal P bar becomes H level (3v), the signal Q becomes L level (ground level), and the transistor Tr30 is turned on. The output voltage output from the external terminal 32 is 5v.

When the control signal P becomes H level 3v and the signal P bar becomes L level (ground level), the signal Q becomes H level 5v, the transistor Tr30 is turned off, and the external terminal 32 has a high impedance. It becomes a state.

As described above, the initial value of the signal Q when power is supplied to the level converter 10 is the H level 5v. Therefore, the initial state when the external terminal 32 is turned on becomes a high impedance state.

As described above, the characteristic effects in the fourth embodiment are described below.

(1) In the pull-up resistor control output circuit of the present embodiment, when the power supply voltage of 5v is supplied when the input signals P and P bars are both at L level, the level converter 10 outputs the signal Q of the H level 5v. The external terminal 32 is in a high impedance state.

Therefore, the normal operation of the pull-up resistor control output circuit is ensured while enabling the pull-up resistor control output circuit to be controlled by the control signal P whose amplitude is 3v from the ground level. In addition, the initial state of the operation of the pull-up resistor control output circuit when the signals P and P bars are both at the L level can be set to the high impedance state.

(Example 5)

8 shows a fifth embodiment in which the present invention is embodied in an input / output circuit 40. In this input / output circuit 40, since the level converter 10 (initial value 1) of the second embodiment and the level converter 15 (initial value 0) of another example are used, the operation of the level converters 10 and 15 is prevented. The description is omitted.

The input / output control signal C output from the internal circuit is a signal that becomes H level when the terminal 41 is used as the output terminal. The data D output from the internal circuit is output from the terminal 41 when the terminal 41 is used as the output terminal. The amplitude of this signal C. D is 3v from the ground level.

In this input / output circuit 40, the input / output control signal C is input to the NAND circuit 42 and also to the NOR circuit 44 through the inverter 43. The data D is input to the NAND circuit 42 and to the NOR circuit 44.

The output signal E of the NAND circuit 42 is input to the level converter 10, and is inverted by the inverter 45 and input to the level converter 10 as a signal E bar. The output signal F of the NOR circuit 44 is input to the level converter 15 and inverted by the inverter 46 and input to the level converter 15 as a signal F bar. Each of the logic circuits 42 to 46 operates with a 3v power supply.

The signal G output from the level converter 10 is input to the gate of the first input / output transistor Tr40 composed of the P-channel MOS transistor. The source of the transistor Tr40 is connected to a power supply of 5v. The signal H output from the level converter 15 is input to the gate of the second input / output transistor Tr41 composed of the N-channel MOS transistors. The source of the transistor Tr41 is connected to the ground GND.

The drains of the transistors Tr40 and Tr41 are connected to each other to form a node N5, and the node N5 is connected to the terminal 41 and to the internal circuit of the semiconductor device through the input buffer 47. It is.

In the input / output circuit 40 configured as described above, when the input / output control signal C reaches the L level (ground level), the signal E is fixed at the H level 3v, and the signal F is fixed at the L level (ground level).

Then, in the above-described level converters 10 and 15, the signals E and F whose amplitudes are 3v from the ground level are converted into the signals G and H whose amplitudes are 5v from the ground level. Accordingly, the transistors Tr40 and Tr41 are turned off together to enter the input mode. When a signal is input to the terminal 41 in this state, the signal becomes the input signal In through the input buffer 47 and is supplied to the internal circuit.

When the input / output control signal C reaches the H level (3v), the signals E and F become inverted signals of the data D.

Then, in the level converters 10 and 15, the signals E and F whose amplitudes are 3v from the ground level are converted into the signals G and H whose amplitudes are 5v from the ground level. Therefore, when the data D reaches the H level 3v, the transistor Tr40 is turned on and the transistor Tr41 is turned off. When the data D becomes L level (ground level), the transistor Tr40 is turned off and the transistor Tr41 is turned on. In other words, the output mode is turned on in which either of the transistors Tr40 and Tr41 is turned on based on the data D. From the terminal 41, data D whose amplitude is 5v from the ground level is output.

If 5v power is supplied prior to 3v power supply at the time of power supply to the semiconductor device with the level converters 10 and 15, the signal E, E bar, F, F bar are all L level, but the level converter 5v is supplied to 10 and 15.

As described above, the initial value of the signal G when power is supplied to the level converter 10 is H level 5v. The initial value of the signal H at the time of power supply to the level converter 15 is L level (ground level).

Thus, the transistors Tr40 and Tr41 are turned off. As a result, the initial state when the input / output circuit 40 turns on the power becomes an input mode.

The characteristic effects of the fifth embodiment as described above are described below.

(1) In the input / output circuit 40 of this embodiment, a power supply voltage of 5v is supplied when the signals E, E, F, F, and F bars input to the level converters 10 and 15 are all at L level when the power is turned on. Even if it is, the signal G of the H level 5v is output from the level converter 10, and the signal H of the L level (ground level) is output from the level converter 15. Therefore, the transistors Tr40 and Tr41 are reliably turned off so that no unnecessary current flows from the terminal 41, and no through current flows from the power supply to the ground GND. Moreover, no external current flows to ground GND.

The fifth embodiment may be modified as follows.

As shown in Fig. 9, even if the level converters 10 and 15 are changed to the level converter 25 (initial value 1) of another example of the third embodiment and the level converter 20 (initial value 0) of the third embodiment. good. At this time, it is necessary to connect the reset signal output circuit 21 to the level converters 25 and 20.

In this input / output circuit 48, in addition to the effects similar to those of the fifth embodiment, the same effects as those of (2) of the effects of the third embodiment can be obtained.

In addition, you may change each said Example as follows.

In the above first embodiment, the threshold voltages of the first and second CMOS inverters 2 and 3 are set to be the same value, but for example, the threshold voltages of the first CMOS inverter 2 are referred to as the second CMOS inverter ( It may be set higher than the threshold voltage of 3). In this other example, the first and second CMOS inverters 2 and 3 constitute an initial value setting circuit.

In this case, when the power supply voltage of 5v is input when the input signals A and A are both at the L level, the second CMOS inverter 3 first outputs the H level, and the state is maintained. Therefore, the node N3 becomes the H level 5v, and the output signal B of the L level (ground level) is output from the third CMOS inverter 4. The initial value is zero.

The threshold voltage of the second CMOS inverter 3 may be set to a value higher than the threshold voltage of the first CMOS inverter 2. In this case, if the power supply voltage of 5v is input when the input signals A and A are both at the L level, the node N3 is at the L level (ground level), and the H level (5v) is supplied from the third CMOS inverter 4. Output signal B is outputted. In other words, the initial value is 1.

Therefore, the initial value can be set without increasing the number of transistors.

In the level converter 10 of the second embodiment, the threshold voltage of the second CMOS inverter 3 may be set to a value higher than the threshold voltage of the first CMOS inverter 2. In the level converter 15 of another example, the threshold voltage of the first CMOS inverter 2 may be set to a value higher than the threshold voltage of the second CMOS inverter 3. In this other example, the first and second CMOS inverters 2 and 3 and the first and second capacitors C1 and C2 constitute an initial value setting circuit.

This complements the action of the coupling phenomenon of the first and second capacitors C1 and C2, so that the initial value can be reliably set.

In the level converter 10 of the second embodiment, one of the first and second capacitors C1 and C2 may be omitted. For example, even when the first capacitor C1 is omitted, the second capacitor C2 acts to pull down the level of the node N3 toward the L level, so that the node N3 is kept at the L level. do. Further, for example, even when the second capacitor C2 is omitted, the node N3 is brought to the L level because the first capacitor C1 acts to raise the level of the node N4 toward the H level. maintain. Therefore, this initial value is 1. As a result, it is possible to set the initial value 1 by reducing the number of capacitances. In the level converter 15 of another example, one of the first and the first and second capacitors C1 and C2 may be omitted. In this way, the initial value 0 can be set by reducing the number of capacities.

The level converters 1, 10, 15, 20, and 25 of the above embodiments and other examples may be connected to the level converter 51 of FIG. In this way, when an output circuit of the output buffer circuit 53 composed of the level converters 1, 10, 15, 20, 25 and the CMOS inverter is not supplied to the internal circuit 50, a power supply voltage of 3v is not provided. That is, when the power supply voltage of 5v is input when the input signals A and A bars are both at the L level, the output signal B output from the level converters 1, 10, 15, 20, and 25 is L level (ground level) or H. It becomes either of level 5v. Therefore, the transistors Tr1 and Tr2 of the output buffer circuit 53 do not all turn on together, and no through current flows from the power supply to the ground GND. As a result, normal operation of the output circuit is ensured while lowering the power consumption of the semiconductor device. In the case of using the level converters 1, 10, 15, 20, and 25 with initial values set, the initial values of the output circuits are determined, so that the operation of the circuit connected to the output terminal 54 can be reliably controlled. have.

In the fourth embodiment, the level converter 10 is used, but the level converter 25 may be used instead of the level converter 10. In this manner, the same effects as in the fourth embodiment can be obtained. In addition, the area occupied by the level converter 25 in the layout area of the semiconductor device can be reduced.

Alternatively, the level converters 15 and 20 may be used instead of the level converter 10. In this case, when the power supply voltage of 5v is applied when the input signals P and P bars are both at the L level, the external terminal 32 is in a high impedance state. Therefore, the circuit operation of the next stage can be assured.

The power supply of 3v and 5v in each of the above-described embodiments and other examples may be performed with power of different voltage values.

In the level converters 20 and 25 of the third and other examples, the source of the transistor Tr20 is connected to ground GND, but may be connected to a 5v power supply. This reverses the initial value.

As described above, according to the invention described in claim 1, the circuit operates normally even when the buffer signal is in an indeterminate state.

According to the invention of claim 2, the binary output signal is reliably output.

According to the invention of claim 3, when the high voltage power supply is turned on, a binary output signal of an initial value is output from the output holding circuit.

According to the invention of claims 4 to 7, the initial value of the binary output signal to be output when the high voltage power is turned on in the state in which the buffer signal is in an indeterminate state is determined as either of the binary output signals.

According to the invention of claim 8, the output circuit operates normally.

According to the invention of claim 9, the initial state of the pull-up when the high-voltage power supply is turned on while the buffer signal is in an indeterminate state is set.

According to the invention of claim 10, the initial state of the mode when the high voltage power is turned on when the buffer signal is in an indeterminate state is set.

Claims (10)

On the basis of an input buffer circuit into which a binary input signal having an amplitude based on a low voltage power supply is input and a pair of buffer signals output from the input buffer circuit, the binary input signal is a binary value of amplitude based on a high voltage power supply. A level converter having a level converting section for converting and outputting an output signal, wherein the level converting section includes an output holding circuit for outputting the binary output signal according to the potential difference between the buffer signals when the buffer signal is in an indeterminate state. Level converter characterized in that equipped with. 2. The output circuit of claim 1, wherein the output holding circuit and the level converting section are configured by connecting an input terminal and an output terminal of the first and second CMOS inverters operating with a high voltage power supply, and the input buffer circuit outputs the first CMOS inverter. The first input transistor is connected in series between the terminal and the low potential side power supply, and the second input transistor is connected in series between the output terminal of the second CMOS inverter and the low potential side power supply. And the buffer signal is output by turning on either one of the first and second input transistors based on an input signal. The level converter according to claim 1 or 2, wherein the output holding circuit includes an initial value setting circuit for setting an initial value of the binary output signal when a high voltage power is supplied. 4. The level converter according to claim 3, wherein the initial value setting circuit is connected to either one of the high potential side power supply and the full potential side power supply via the capacitance of one of the output terminals of the first and second CMOS inverters. The initial value setting circuit according to claim 3, wherein the initial value setting circuit comprises: an initial value setting transistor interposed between an output terminal of any one of the first and second CMOS inverters, and either one of a high potential side power supply and a low potential side power supply; And a reset signal output circuit for turning on the initial value setting transistor for a predetermined time in response to the application of a high voltage power supply. 4. The level converter according to claim 3, wherein the initial value setting circuit configures threshold voltages of the first and second CMOS inverters to different values. 5. The level converter according to claim 4, wherein the initial value setting circuit comprises the first and second CMOS inverters having different values of the capacitance and the threshold voltage. An output circuit is driven based on the binary output signal of the level converter of the level converter according to any one of claims 1 to 7. An output circuit for opening and closing a pull-up control transistor connected to a high potential power supply via a resistor based on the binary output signal of the level converter according to any one of claims 3 to 7. On the basis of the binary output signal of the level converter of any one of claims 3 to 7, the output mode for outputting the output signal from the output buffer circuit and the input mode for making the output signal of the output buffer circuit in an indefinite state are switched. Input and output circuit, characterized in that.