JP2000013212A - Input circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an input circuit in which a high level of an output signal voltage is set around a power supply voltage of a CMOS inverter when an output signal of the CMOS inverter at an input first stage is at a high level and a through-current is decreased. SOLUTION: The input circuit 300 has a CMOS inverter 20 of an input first stage, a CMOS inverter 30 of a next stage, an input protection circuit 10 and 1st and 2nd voltage application circuits 40, 50. The 1st voltage application circuit 40 applies a 1st power supply voltage Vcc to a source of a P-channel MOS TR 21 when an output signal of the CMOS inverter 20 is at a high level and applies a 1st reference voltage VCCH to the source when the output signal is at a low level. A difference voltage obtained by subtracting an input signal voltage Vih from the 1st reference voltage VCCH when an input signal Si is at a high level is smaller than an absolute value of a threshold voltage of the P-channel MOS TR 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS (Comple
mentary Metal Oxide Semiconductor) relates to an input circuit configured using a logic circuit.

[0002]

2. Description of the Related Art FIG. 1 shows a conventional example of an inverter constituted by a CMOS logic circuit, that is, an input circuit having a CMOS inverter. The input circuit of FIG. 1 includes an input protection circuit 10 and CMOS inverters 20 and 30. The input terminal 1 of the input circuit 100 is connected to the node N10 and the input terminal Ta of the CMOS inverter 20, and the input signal 1 is input to the input terminal 1. P channel MOS transistor and N channel type M of CMOS inverter
The OS transistors are each constituted by an enhancement type field effect transistor.

The input protection circuit 10 has a P-channel transistor 11 and an N-channel transistor 12, and each of the P-channel transistor 11 and the N-channel transistor 12 is constituted by an enhancement field-effect transistor. I have. The source and the gate of the P-channel transistor 11 are connected to the node N11. The nodes N11 and NV have the first power supply voltage Vc
c has been supplied. Each drain of P-channel transistor 11 and N-channel transistor 12 is connected to node N10. The source and the gate of the N-channel transistor 12 are connected to the node N12. The nodes N12 and NG are supplied with the second power supply voltage GND and have a ground potential of 0V. The power supply voltage on the high potential side of the CMOS logic circuit is the first power supply voltage Vcc, and the power supply voltage on the low potential side is the second power supply voltage GND.

[0006] The CMOS inverter 20 has a P-channel transistor 21 and an N-channel transistor 22. The source of the P-channel transistor 21 is connected to the node NV, and the P-channel transistor 2
Each gate of the 1- and N-channel transistors 22 is connected to a node a, and the node a is connected to an input terminal Ta of the CMOS inverter 20. P-channel transistor 21 and N-channel transistor 22
Are connected to the node N20, and the node N20 is connected to the output terminal T20 of the CMOS inverter 20. The source of the N-channel transistor 22 is connected to the node NG. CMOS inverter 3
0 inputs the output signal of the CMOS inverter 20 and outputs an output signal So obtained by inverting the output signal to the output terminal 2.

In general, the voltage level of a signal inside an IC (Integrated Circuit) chip and an external input signal S
i have different voltage levels. For example, a transistor / transistor logic circuit (TTL: Transistor Transistor Lo)
gic) is input to a CMOS logic circuit.
The relationship between the power supply voltage inside the IC chip of the CMOS logic circuit and the input signal voltage is as follows. 0 <Vil <Vih <Vcc Here, the input signal voltage at the high level is represented by Vih, the input signal voltage at the low level is represented by Vil, the first power supply voltage is represented by Vcc, and the second power supply voltage is 0V.

In input circuit 100, Vcc-Vih>
| Vthp |, when the input signal voltage is Vih, the P-channel MOS transistor 21 and the N-channel MO
The S transistor 22 is turned on, and a through current flows. Similarly, when Vil> | Vthn |, when the input signal voltage is Vil, the P-channel MOS transistor 21
And N-channel MOS transistor 22 are turned on, and a through current flows. Here, a P-channel type MO
The threshold voltage of the S transistor is Vthp, and the threshold voltage of the N-channel MOS transistor is Vthn. The standby current flowing when the IC chip is in the standby state has a large ratio of the through current.

The input circuit 200 shown in FIG.
0, a NOR circuit 25, and a CMOS inverter 30. The output signal of the NOR circuit 25 is
Enter 0. The same components as those of the input circuit 100 of FIG. 1 are denoted by the same reference numerals. Node N10 is NOR circuit 2
5 is connected to one input terminal, and the other input terminal of the NOR circuit 25 is supplied with a chip enable (CE) signal CE. The chip enable signal CE is I
When the C chip is in an operable state, it is at a low level,
It is at the high level in the other disabled state.

In the input circuit 200, the NOR operation of the input signal Si from the input terminal 1 and the chip enable signal CE is performed by the NOR circuit 25, so that the through current of the NOR circuit 25 when the IC chip is disabled is reduced. And the standby current can be reduced. However, since the change in the chip enable signal CE has a delay time with respect to the change in the state of the IC chip, the detection time of the input signal Si in the input circuit 200 may be delayed by the delay time. Also, when the IC chip is in an operable state, a through current will continue to flow,
This causes an increase in current consumption and power consumption.

[0009] Japanese Patent Application Laid-Open Nos.
193133 discloses an input circuit having a CMOS inverter. The input circuit of the above publication is configured to supply a single constant voltage to the source of a P-channel MOS transistor of a CMOS inverter at the input first stage.

[0010]

In the input circuit disclosed in the above-mentioned publication, the output signal voltage of the first-stage CMOS inverter when the output signal is high is close to the input signal voltage when the input signal is high. Become. The difference is within the absolute value of the threshold voltage (threshold voltage).

When the input signal Si supplied to the gate is at a high level, the through current of the CMOS inverter at the first input stage can be reduced by satisfying the following conditions. : The difference voltage obtained by subtracting the gate potential from the source potential of the P-channel MOS transistor is the P-channel MOS transistor.
It is smaller than the absolute value of the threshold voltage of the OS transistor.

When the input signal Si supplied to the gate is at a low level, the through current of the CMOS inverter at the input first stage can be reduced by satisfying the following conditions. : The difference voltage obtained by subtracting the source potential from the gate potential of the N-channel MOS transistor is
It is smaller than the absolute value of the threshold voltage of the OS transistor.

A first object of the present invention is to provide a CMO of an input first stage.
The output signal voltage when the output signal of the S inverter is at a high level can be set to about the first power supply voltage,
It is an object of the present invention to provide an input circuit capable of reducing a through current when an output signal of a CMOS inverter at an input first stage is at a low level. A second object of the present invention is to enable the output signal voltage of the first input CMOS inverter to be about the second power supply voltage when the output signal of the first input CMOS inverter is at a low level, and the output signal of the first input CMOS inverter to be high. An object of the present invention is to provide an input circuit capable of reducing a through current at the time of a level.

[0014]

According to a first input circuit of the present invention, there is provided a CMOS inverter comprising a CMOS logic circuit in which a P-channel MOS transistor and an N-channel MOS transistor are connected in a complementary manner; An input circuit having a first voltage supply circuit for supplying one of a first power supply voltage and a first reference voltage to a source of a channel type MOS transistor, wherein an input terminal of the input circuit is the CMOS inverter. The first voltage supply circuit supplies the first power supply voltage to the source when the output signal of the CMOS inverter is at a high level, and the output signal is at a low level. Supplying said first reference voltage to said source,
A difference voltage obtained by subtracting the input signal voltage when the input signal of the MOS inverter is at a high level from the first reference voltage is smaller than an absolute value of a threshold voltage of the P-channel MOS transistor.

In the first input circuit of the present invention, preferably,
The first voltage supply circuit includes a first switch connected between a source of the P-channel MOS transistor and a supply terminal of the first power supply voltage, and a source of the P-channel MOS transistor. Second switch means connected between the first reference voltage supply terminal and the first reference voltage supply terminal, wherein one of the first and second switch means is in an on state and the other is in an off state. Yes, the CMO
When the output signal of the S inverter is at a high level, the first switch is on, and when the output signal is at a low level, the second switch is on.

In the first input circuit according to the present invention, more preferably, a second CMOS inverter constituted by a CMOS logic circuit is connected to an output terminal of the CMOS inverter, and the first switch means is provided. Is connected to the output terminal of the second CMOS inverter, and the control terminal of the second switch means is connected to the CMO
Connected to the output terminal of the S inverter, wherein the first and second switch means are each a P-channel MOS
It is a transistor.

According to a second input circuit of the present invention, a CMOS inverter composed of a CMOS logic circuit in which a P-channel MOS transistor and an N-channel MOS transistor are complementarily connected, and a source of the N-channel MOS transistor And a second voltage supply circuit for supplying one of a second power supply voltage and a second reference voltage to the input circuit.
Connected to an input terminal of an inverter, the second voltage supply circuit supplies the second reference voltage to the source when an output signal of the CMOS inverter is at a high level, and the output signal is at a low level. In this case, the second power supply voltage is supplied to the source, and a difference voltage obtained by subtracting the second reference voltage from the input signal voltage when the input signal of the CMOS inverter is at a low level is the N-channel MOS. It is smaller than the absolute value of the threshold voltage of the transistor.

In the second input circuit of the present invention, preferably,
The second voltage supply circuit includes a third switch connected between a source of the N-channel MOS transistor and a supply terminal of the second power supply voltage, and a source of the N-channel MOS transistor. Fourth switch means connected between the supply terminal of the second reference voltage and the third and fourth switch means, when one of them is on, the other is off. Yes, the CMO
When the output signal of the S inverter is at a low level, the third switch is on, and when the output signal is at a high level, the fourth switch is on.

In the second input circuit of the present invention, more preferably, a second CMOS inverter constituted by a CMOS logic circuit is connected to an output terminal of the CMOS inverter, and the third switch means is provided. Is connected to the output terminal of the second CMOS inverter, and the control terminal of the fourth switch means is connected to the CMO
Connected to the output terminal of the S inverter, wherein the third and fourth switch means are each an N-channel MOS.
It is a transistor.

According to a third input circuit of the present invention, a CMOS inverter constituted by a CMOS logic circuit in which a P-channel MOS transistor and an N-channel MOS transistor are connected complementarily, and a source of the P-channel MOS transistor A first voltage supply circuit for supplying any one of a first power supply voltage and a first reference voltage to the N-channel MOS transistor; An input terminal connected to an input terminal of the CMOS inverter, wherein the input terminal of the input circuit is connected to an input terminal of the CMOS inverter. When the output signal is at a high level, the first power supply voltage is supplied to the source, and when the output signal is at a low level, the first power supply voltage is supplied to the source. Supply voltage to the source, the second voltage supply circuit supplies the second reference voltage to the source when the output signal of the CMOS inverter is at a high level, and the output signal is at a low level. In this case, the second power supply voltage is supplied to the source, and a difference voltage obtained by subtracting the input signal voltage when the input signal of the CMOS inverter is at a high level from the first reference voltage is equal to the P voltage.
The difference voltage obtained by subtracting the second reference voltage from the input signal voltage when the input signal of the CMOS inverter is low level is smaller than the absolute value of the threshold voltage of the channel type MOS transistor, Smaller than the absolute value of the threshold voltage.

In the third input circuit of the present invention, preferably,
The first voltage supply circuit includes a first switch connected between a source of the P-channel MOS transistor and a supply terminal of the first power supply voltage, and a source of the P-channel MOS transistor. Second switch means connected between the first reference voltage supply terminal and the first reference voltage supply terminal, wherein one of the first and second switch means is in an on state and the other is in an off state. Yes, the CMO
When the output signal of the S inverter is at a high level, the first switch means is in an on state. When the output signal is at a low level, the second switch means is in an on state. The circuit is the N-channel type MO
Third switch means connected between the source of the S transistor and the supply terminal of the second power supply voltage, and between the source of the N-channel MOS transistor and the supply terminal of the second reference voltage Connected fourth switch means, wherein one of the third and fourth switch means is in the on state when the other is in the on state, and the third and fourth switch means is in the off state.
When the output signal of the MOS inverter is at a low level, the third switch is on, and when the output signal is at a high level, the fourth switch is on.

In the third input circuit of the present invention, more preferably, a second CMOS inverter constituted by a CMOS logic circuit is connected to an output terminal of the CMOS inverter, and The control terminal is connected to an output terminal of the second CMOS inverter,
The control terminal of the second switch means is connected to the output terminal of the CMOS inverter, the control terminal of the third switch means is connected to the output terminal of the second CMOS inverter, The control terminal of the fourth switch means is connected to the output terminal of the CMOS inverter, the third and fourth switch means are N-channel MOS transistors, respectively, and the first and second switch means Is a P-channel type M
OS transistor.

In the input circuit of the present invention having the first voltage supply circuit, the first voltage supply circuit supplies the first power supply voltage to the P-channel of the CMOS inverter when the output signal of the CMOS inverter is at a high level. It is supplied to the source of the type MOS transistor. When the output signal of the CMOS inverter is at a high level, the P-channel type MOS
The transistor is in an ON state, and the first power supply voltage is applied to the CMOS through the P-channel MOS transistor.
It is supplied to the output terminal of the inverter.

The first voltage supply circuit supplies the first reference voltage to a source of a P-channel MOS transistor of the CMOS inverter when an output signal of the CMOS inverter is at a low level. When the output signal of the CMOS inverter is at a low level, the P-channel MOS transistor is in an off state or a state close to the off state, and the input signal voltage when the input signal of the CMOS inverter is at a high level is referred to as the first reference voltage. The difference voltage subtracted from the voltage is smaller than the absolute value of the threshold voltage of the P-channel MOS transistor, and the drain current can be reduced.

In the input circuit of the present invention having the first and second switch means, when the output signal of the CMOS inverter is at a high level, the first switch means and the P-channel MOS transistor are on. When the output signal of the CMOS inverter is at a high level, the first power supply voltage is applied to the first switch means and the P switch.
It is supplied to the output terminal of the CMOS inverter via a channel type MOS transistor. When the output signal of the CMOS inverter is at a low level, the second switch is in an on state. The difference voltage obtained by subtracting the input signal voltage when the input signal of the CMOS inverter is at a high level from the first reference voltage is the P-channel type MOS transistor.
Since it is smaller than the absolute value of the threshold voltage of the transistor,
The drain current can be reduced.

In the input circuit of the present invention having the second voltage supply circuit, the second voltage supply circuit supplies the second reference voltage when the output signal of the CMOS inverter is at a high level to the N-channel of the CMOS inverter. It is supplied to the source of the type MOS transistor. When the output signal of the CMOS inverter is at a high level, the N-channel MOS
The transistor is off or close to it,
The difference voltage obtained by subtracting the second reference voltage from the input signal voltage when the input signal of the CMOS inverter is at a low level is smaller than the absolute value of the threshold voltage of the N-channel MOS transistor, and the drain voltage is reduced. can do.

The second voltage supply circuit supplies the second power supply voltage to a source of an N-channel MOS transistor of the CMOS inverter when an output signal of the CMOS inverter is at a low level. When the output signal of the CMOS inverter is at a low level, the N-channel MOS transistor is in an on state, and the second power supply voltage is supplied to the C-channel transistor via the N-channel MOS transistor.
It is supplied to the output terminal of the MOS inverter.

In the input circuit of the present invention having the third and fourth switch means, the fourth switch means is on when the output signal of the CMOS inverter is at a high level. Since the difference voltage obtained by subtracting the second reference voltage from the input signal voltage when the input signal of the CMOS inverter is low is smaller than the absolute value of the threshold voltage of the N-channel MOS transistor, The current can be reduced. When the output signal of the CMOS inverter is at a low level, the third switch means and the N-channel type MOS transistor are on. When the output signal of the CMOS inverter is at a low level, the second power supply voltage is supplied to the CM through the third switch means and the N-channel MOS transistor.
It is supplied to the output terminal of the OS inverter.

[0029]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 3 is a circuit diagram illustrating an example of the input circuit according to the present invention.

The input circuit 300 is a P-channel type MO
A CMOS inverter 20 composed of a CMOS logic circuit in which an S transistor 21 and an N-channel MOS transistor 22 are complementarily connected, a first power supply Vcc and a second reference voltage VCCH And a second voltage supply circuit for supplying one of the second power supply GND and the second reference voltage VCCL to the source of the N-channel MOS transistor 22. 50, an input protection circuit 10, and a second CMOS inverter 30. The first voltage supply circuit 40 includes a first switch means SW1 connected between the source of the P-channel MOS transistor 21 and the supply terminal 3 for the first power supply voltage Vcc.
And a second switch means SW2 connected between the source of the P-channel MOS transistor 21 and the supply terminal T2 of the first reference voltage VCCH.

The input terminal 1 of the input circuit 300 is connected to the input terminal Ta of the CMOS inverter 20. When one of the first and second switch means SW1 and SW2 is on, the other is off. When the output signal of the CMOS inverter 20 is at a high level, the first switch means SW1 is on, and when the output signal of the CMOS inverter 20 is at a low level, the second switch means SW1 is turned on.
2 is an ON state. A difference voltage (VCCH-Vih) obtained by subtracting the input signal voltage Vih when the input signal of the CMOS inverter 20 is at a high level from the first reference voltage VCCH.
Is smaller than the absolute value | Vthp | of the threshold voltage Vthp of the P-channel type MOS transistor 21.

The second voltage supply circuit 50 includes third switch means SW3 connected between the source of the N-channel MOS transistor 22 and the supply terminal 4 for the second power supply voltage GND, Type MOS transistor 2
4 and a fourth switch means SW4 connected between the second source and the second reference voltage VCCL supply terminal T4. The third and fourth switch means SW3, SW4
When one of them is on, the other is off. When the output signal of the CMOS inverter 20 is at high level, the fourth switch means SW4 is on, and when the output signal is at low level, The third switch means SW3 is in an on state, and the CMOS inverter 2
The difference voltage (Vil−V) obtained by subtracting the second reference voltage VCCL from the input signal voltage Vil when the input signal of 0 is low level.
VCCL) is the N-channel MOS transistor 2
2 is smaller than the absolute value | Vthn | of the threshold voltage Vthn. Input signal Si from input terminal 1 of input circuit 300
Is, for example, a transistor-transistor logic circuit (TT
L).

The input protection circuit 10 has a P-channel transistor 11 and an N-channel transistor 12. The source and the gate of the P-channel transistor 11 are connected to the node N11. The nodes N11 and NV are supplied with a first power supply voltage Vcc. Each drain of P-channel transistor 11 and N-channel transistor 12 is connected to node N10.
The source and the gate of the N-channel transistor 12 are connected to the node N12. The nodes N12 and NG are supplied with the second power supply voltage GND and have a ground potential of 0V. The first power supply voltage Vc
Even if a signal exceeding the voltage range from c to the second power supply voltage GND is input to the input terminal 1, even if a signal is applied from the level of GND to Vcc
Can be limited to the extent. The power supply voltage on the high potential side of the CMOS logic circuit is the first power supply voltage Vcc, and the power supply voltage on the low potential side is the second power supply voltage GND.
It is.

The source of the P-channel MOS transistor 21 is connected to the node d, and one terminal of the first and second switch means SW1 and SW2 is connected to the node d. The source of the N-channel MOS transistor 22 is connected to the node e, and one terminal of the third and fourth switch means SW3, SW4 is connected to the node e. The other terminal of the switch means SW1 is connected to the node NV, and the other terminal of the switch means SW2 is connected to the supply terminal T2 of the first reference voltage VCCH. The other terminal of the switch means SW3 is connected to the node NG, and the other terminal of the switch means SW4 is connected to the supply terminal T4 of the second reference voltage VCCL.

In CMOS inverter 20, P-channel transistor 21 and N-channel transistor 2
2 are connected to node a, and node a is
It is connected to the input terminal Ta of the S inverter 20. P
Each drain of the channel type transistor 21 and the N-channel type transistor 22 is connected to the node N20, and the node N20 is connected to the output terminal T20 of the CMOS inverter 20.
It is connected to the. The CMOS inverter 30 has a CMO
An output signal of the S inverter 20 is input, and an output signal So obtained by inverting the output signal is output to the output terminal 2.

The first reference voltage VCCH is a value equal to or higher than the input signal voltage Vih when the input signal of the CMOS inverter 20 is at a high level, and is lower than the first power supply voltage Vcc. The second reference voltage VCCL has a value equal to or lower than the input signal voltage Vil when the input signal of the CMOS inverter 20 is at a low level, and is higher than the second power supply voltage GND.

A high-level signal S whose signal voltage is Vih
When i is input to the input terminal 1, the input signal Si passes through the input protection circuit 10 and is supplied to the input terminal Ta of the CMOS inverter 20. By this input signal Si, C
The N-channel MOS transistor 22 of the MOS inverter 20 is turned on, the output signal of the CMOS inverter 20 becomes low level, and the P-channel MOS transistor 21 is turned off or close to it. The second and third switch means SW2 and SW3 are turned on, and the first and fourth switch means SW1 and SW3 are turned on.
SW4 is turned off.

When the input signal of the CMOS inverter 20 is at a high level, the input signal voltage Vih is changed to a first reference voltage VC.
Since the difference voltage (VCCH-Vih) subtracted from CH is smaller than the absolute value | Vthp | of the threshold voltage Vthp of the P-channel MOS transistor 21, the P-channel MO
The S transistor 21 is turned off or in a state close to the off state, the drain current can be reduced, and the through current can be reduced. CMOS inverter 2
0 is low level, the second power supply voltage G
ND is the third switch means SW3 and N-channel type M
CMOS inverter 20 via OS transistor 22
, The output signal voltage of which is about the second power supply voltage GND. CMOS inverter 20
Is inverted by the CMOS inverter 30 and output to the output terminal 2. The terminal voltage VH of the output terminal 2 is equal to the CMO
The voltage is set to about the first power supply voltage Vcc by the S inverter 30. In this way, the input circuit 300 performs signal level conversion.

In the input circuit 300 shown in FIG.
The signal Si of ih is input from the input terminal 1. In the input circuit 300 in FIG. 4, a signal Si having a signal voltage of Vil is input from the input terminal 1, and the input circuit in FIG. 3 and the input circuit in FIG. 4 have the same configuration. When a low-level signal Si having a signal voltage of Vil is input to the input terminal 1, the input signal Si passes through the input protection circuit 10 and is supplied to the input terminal Ta of the CMOS inverter 20. This input signal Si
N-channel MOS of CMOS inverter 20
The transistor 22 is turned off or close to it, the P-channel MOS transistor 21 is turned on, and the output signal of the CMOS inverter 20 goes high. Further, the second and third switch means SW2,
SW3 is turned off, and the first and fourth switch means SW1 and SW4 are turned on.

When the input signal of the CMOS inverter 20 is at a low level, the second reference voltage V
The difference voltage (Vil-VCCL) obtained by subtracting CCL is N
The threshold voltage Vthn of the channel type MOS transistor 22
Is smaller than the absolute value | Vthn |
The OS transistor 22 is in an off state or a state close to the off state, the drain current can be reduced, and the through current can be reduced. When the output signal of the CMOS inverter 20 is at a high level, the first power supply voltage Vcc is supplied to the CMOS inverter 2 via the first switch means SW1 and the P-channel MOS transistor 21.
0 is supplied to the output terminal T20, and its output signal voltage becomes about the first power supply voltage Vcc. CMOS inverter 2
The CMOS inverter 30 inverts the output signal of “0” and outputs the inverted signal to the output terminal 2. The terminal voltage VL of the output terminal 2 is CM
Due to the OS inverter 30, the voltage becomes about the second power supply voltage GND. In this way, the input circuit 300 performs signal level conversion.

FIG. 5 is a circuit diagram showing an example of the input circuit according to the present invention. In the input circuit 500 of FIG. 5, the same components as those of the input circuit 300 of FIG. 3 are denoted by the same reference numerals, and the description of the same components will be omitted. In the input circuit 500, the first switch means SW of the first voltage supply circuit 40
Reference numeral 1 denotes a first P-channel MOS transistor, and the second switch means SW2 includes a second P-channel MOS transistor. The gate of the first P-channel MOS transistor is connected to the node c, and the gate of the second P-channel MOS transistor is connected to the node b. The third switch means SW3 of the second voltage supply circuit 50 is constituted by a first N-channel MOS transistor, and the fourth switch means SW4 is constituted by a second N-channel MOS transistor. The gate of the first N-channel MOS transistor is connected to the node c, and the gate of the second N-channel MOS transistor is connected to the node b. In a P-channel MOS transistor and an N-channel MOS transistor, a gate is a control terminal. The first and second P-channel MOS transistors and the first and second N-channel MOS transistors are respectively enhancement-type MOSFETs (Meta
l Oxide Semiconductor Field Effect Transistor).

The source of the first P-channel MOS transistor constituting the switch means SW1 is connected to the node NV2, and the node NV2 is connected to the node NV to be supplied with the first power supply voltage Vcc. Switch means SW
The source of the first N-channel MOS transistor constituting the third transistor 3 is connected to the node NG2, and the node NG2 is connected to the node NG to be supplied with the second power supply voltage GND. Node b is connected to output terminal T20 of CMOS inverter 20 and node N35. Node c
Are connected to the output terminal T30 of the CMOS inverter 30, the node N30, and the output terminal 2 of the input circuit 500. Inverted signals are supplied to the gate of the first P-channel MOS transistor forming the switch SW1 and the gate of the second P-channel MOS transistor forming the switch SW2. Inverted signals are supplied to the gate of the first N-channel MOS transistor forming the switch SW3 and the gate of the second N-channel MOS transistor forming the switch SW4.

The CMOS inverter 30 has a P-channel MOS transistor 31 and an N-channel MOS transistor 32. The source of the P-channel MOS transistor 31 is connected to the node NV2. P channel type MOS transistor 31 and N channel type M
Each drain of the OS transistor 32 is connected to the node N30. P-channel type MOS transistor 31
And each gate of N-channel MOS transistor 32 is connected to node N35. N-channel type MO
The source of the S transistor 32 is connected to the node NG2.

When an input signal Si having a signal voltage Vih is input to the input terminal 1, the N-channel MOS transistor 22 is turned on regardless of which of the switch means SW3 and SW4 is turned on, and the potential of the node b is turned on. Approaches GND, and the node c approaches Vcc in conjunction therewith. The switch means SW1 and SW4 are turned off, and the switch means SW2 and SW3 are turned on.
In the inverter 20, the source of the P-channel MOS transistor 21 is supplied with the first reference voltage VCCH via the switch SW2, and the source of the N-channel MOS transistor 22 is supplied with the second power supply via the switch SW3. The voltage GND is supplied. At this time, CMOS
P-channel MOS transistor 21 of inverter 20
The difference voltage Vgs obtained by subtracting the gate potential from the source potential becomes about VCCH-Vih, so that the P-channel MOS transistor 21 does not turn on, but turns off or close to it, thereby preventing a through current from flowing. Or the through current can be reduced.
When the potential of the node d is lower than Vih + | Vthp |, it is possible to prevent the drain current of the P-channel MOS transistor 21 from flowing.

In the input circuit 500 shown in FIG.
The signal Si of ih is input from the input terminal 1. In the input circuit 500 of FIG. 6, a signal Si having a signal voltage of Vil is input from the input terminal 1, and the input circuit of FIG. 5 and the input circuit of FIG. 6 have the same configuration. Input signal Si with signal voltage Vil
Is input to the input terminal 1, the switch means SW1, S
Whichever of W2 is in the ON state, the P-channel MOS transistor 21 is in the ON state, and the potential of the node b becomes V
cc, and the node c approaches GND in conjunction therewith. The switch means SW2 and SW3 are turned off, the switch means SW1 and SW4 are turned on, and in the input first stage CMOS inverter 20, the first power supply voltage Vcc is supplied to the source of the P-channel MOS transistor 21 via the switch SW1. The second reference voltage VCCL is supplied to the source of the N-channel MOS transistor 22 via SW4. At this time, the difference voltage | Vgs | obtained by subtracting the source potential from the gate potential of the N-channel MOS transistor 22 of the CMOS inverter 20 is V
It becomes about il-VCCL, and the N-channel MOS transistor 22 does not enter an on state but enters an off state or a state close to an off state, thereby preventing a through current from flowing or reducing the through current. Can be. When the potential of the node e is higher than Vil− | Vthn |,
It is possible to prevent the drain current of the N-channel MOS transistor 22 from flowing.

FIG. 7 is a circuit diagram showing an example of the input circuit according to the present invention. In the input circuit 700 of FIG. 7, the same components as those of the input circuit 500 of FIG. 5 are denoted by the same reference numerals, and the description of the same components will be omitted. The input circuit 700 has a configuration in which first and second reference voltage generation circuits 45 and 55 are provided in the input circuit 500, and the first reference voltage VC
The first reference voltage generation circuit 45 is connected to the supply terminal T2 of the CH, and the supply terminal T4 of the second reference voltage VCCL is connected.
Is connected to a second reference voltage generation circuit 55.

The first reference voltage generating circuit 45 has a diode-connected P-channel type MOS transistor 46, and the diode-connected P-channel type MOS transistor 46.
The S transistor 46 is connected in the forward direction between the source of the second P-channel MOS transistor constituting the switch means SW2 and the supply terminal 3 of the first power supply voltage Vcc. The terminal T1 of the first reference voltage generation circuit 45 is connected to the node NV3, and the node NV3 is connected to the node N3.
V2 and the source of the P-channel MOS transistor 31. The terminal T1 is connected to the source of the P-channel MOS transistor 46, its gate and drain are connected to the node f, and the node f is connected to the supply terminal T2. A diode may be used instead of the P-channel MOS transistor 46, and a plurality of diodes or MOS transistors may be connected in series to configure the first reference voltage generation circuit 45.

The second reference voltage generation circuit 55 has a diode-connected N-channel MOS transistor 56, and the diode-connected N-channel MOS transistor 56.
The S transistor 56 is connected in the forward direction between the source of the second N-channel MOS transistor constituting the switch means SW4 and the supply terminal 4 of the second power supply voltage GND. The terminal T3 of the second reference voltage generation circuit 55 is connected to the node NG3, and the node NG3 is
It is connected to the sources of the G2 and N-channel MOS transistors 32. The terminal T3 is connected to the source of the N-channel MOS transistor 56, its gate and drain are connected to the node g, and the node g is connected to the supply terminal T4. A diode may be used instead of the N-channel MOS transistor 56, and a plurality of diodes or MOS transistors may be connected in series to form the second reference voltage generation circuit 55.

The first and second reference voltage generation circuits 45,
55, a diode or diode-connected MO
The first and second reference voltages VCCH and VCCL are respectively generated using the voltage drop of the S transistor. The first reference voltage generation circuit 45 may use a diode-connected N-channel MOS transistor, and the second reference voltage generation circuit 55 may use a diode-connected P-channel MOS transistor.

The input circuit 800 of FIG. 8 removes the second voltage supply circuit 50 and the second reference voltage generation circuit 55 from the input circuit 700 of FIG. 7, and connects the sources of the N-channel MOS transistors 22 and 32 to each other. The configuration is such that the node NG1 is connected to the node NG1 and the node NG1 is connected to the node NG. CMO
N-channel MOS transistor 2 of S inverter 20
The second source is supplied with the second power supply voltage GND. The input circuit 800 of FIG.
The same components as those described above are denoted by the same reference numerals, and the description of the same components will be omitted. In the input circuit 800, the input signal Si
Is a high-level signal such as TTL, the through current can be reduced. From the input signal voltage Vil when the input signal Si is low, the second power supply voltage GN
When the difference voltage (Vil-GND) from which D is subtracted is smaller than the absolute value | Vthn | of the threshold voltage Vthn of the N-channel MOS transistor 22, the through current when the input signal Si is at a low level is reduced. Can be.

The input circuit 900 of FIG. 9 removes the first voltage supply circuit 40 and the first reference voltage generation circuit 45 from the input circuit 700 of FIG. 7, and connects the respective sources of the P-channel MOS transistors 21 and 31 to each other. The configuration is such that the node NV1 is connected to the node NV1 and the node NV1 is connected to the node NV. CMO
P-channel MOS transistor 2 of S inverter 20
The first power supply voltage Vcc is supplied to one source. In the input circuit 900 of FIG. 9, the input circuit 700 of FIG.
The same components as those described above are denoted by the same reference numerals, and the description of the same components will be omitted. In the input circuit 900, the input signal Si
Is a low-level signal such as TTL, the through current can be reduced. When the input signal Si is at the high level, the input signal voltage Vih is changed to the first power supply voltage Vcc.
Is smaller than the absolute value | Vthp | of the threshold voltage Vthp of the P-channel MOS transistor 21, the through current when the input signal Si is at a high level can be reduced. it can.

FIG. 10 is a time chart for explaining the operation of input circuit 500 and input circuit 700. When the signal Si from the TTL is supplied to the input terminal 1, the signal Si is supplied to the node a of the first-stage CMOS inverter 20 via the input protection circuit 10. The signal voltage at the time of the high level of the signal Si is Vih, and the signal voltage at the time of the low level is Vil. When the potential of the node a is Vil, the P-channel type MOS transistor 21 is on and the node b
Is supplied with a voltage of about the first power supply voltage Vcc, the N-channel MOS transistor 32 is on, and the node c is supplied with the second power supply voltage GND. The switch means SW1 and SW4 are on, and the switch means SW2 and SW3 are off.

When the potential of the node a rises from Vil, the potential of the node b falls, and the switch means SW is connected to the node b.
A voltage of about the second reference voltage VCCL is supplied via the fourth and N-channel MOS transistors 22, the node b becomes low level, and the potential of the node c rises to high level. Then, the switches SW4 and SW1 are turned off, the switches SW2 and SW3 are turned on, and a voltage of about the second power supply voltage GND is supplied to the node b via the switch SW3 and the N-channel MOS transistor 22. Is done. Thus, when the input signal Si is switched to the high level, the node b
Can be supplied with a voltage of about the second power supply voltage GND, and signal level conversion can be performed.

When the potential at the node a is Vih, the N-channel MOS transistor 22 is on and
Is supplied with a voltage of about the second power supply voltage GND, the P-channel MOS transistor 31 is on, and the node c is supplied with the first power supply voltage Vcc. The switch means SW1 and SW4 are off, and the switch means SW2 and SW3 are on.

When the potential at the node a falls from Vih, the potential at the node b rises, and the switching means SW is connected to the node b.
A voltage of about the first reference voltage VCCH is supplied via the second and P-channel MOS transistors 21, the node b goes high, and the potential of the node c goes low to go low. Then, the switches SW1 and SW4 are turned on, the switches SW2 and SW3 are turned off, and a voltage of about the first power supply voltage Vcc is supplied to the node b via the switch SW1 and the P-channel MOS transistor 21. Is done. Thus, when the input signal Si is switched to the low level, the node b
Can be supplied with a voltage of about the first power supply voltage Vcc, and signal level conversion can be performed.

As described above, the input circuit of the present embodiment can amplify a TTL level input signal to a CMOS level signal by the first input CMOS inverter, and reduce the through current of the first input CMOS inverter. It can be reduced in size and has favorable characteristics as an input buffer. Since the through current of the CMOS inverter at the input first stage can be reduced, the standby current of the integrated circuit having this input circuit can be reduced.
Further, the through current during the operation of the integrated circuit can be reduced.

The control terminal of the first P-channel MOS transistor constituting the switch means SW1 is connected to the second CMO
By connecting to the output terminal T30 of the S-inverter 30 and using the output signal of the second CMOS inverter 30 as the control signal of the switch SW1, the switch SW1 is reliably turned on or off. Can be. The control terminal of the first N-channel MOS transistor constituting the switch means SW3 is connected to the output terminal T30 of the second CMOS inverter 30, and the switch means S3
By using the output signal of the second CMOS inverter 30 as the control signal of W3, the switch means SW3 can be surely set to one of the ON state and the OFF state.

The input signal voltage Vil at the low level may be, for example, about 0.2 V, the input signal voltage Vih at the high level may be, for example, about 2.3 V, and the first power supply voltage Vcc may be, for example. It may be about 5V. In addition, the said embodiment is an example of this invention,
The present invention is not limited to the above embodiment.

[0059]

According to the first input circuit of the present invention, when the output signal of the first input CMOS inverter is at a high level, the output signal voltage can be reduced to about the first power supply voltage. Further, the through current when the output signal of the input first-stage CMOS inverter is at a low level can be reduced.

In the second input circuit of the present invention, the output signal voltage when the output signal of the CMOS inverter at the input first stage is at a low level can be set to about the second power supply voltage. Further, it is possible to reduce the through current when the output signal of the first input CMOS inverter is at a high level.

In the third input circuit of the present invention, when the output signal of the input first stage CMOS inverter is at a high level, the output signal voltage can be set to about the first power supply voltage, and the input first stage CMOS inverter When the output signal is low, the output signal voltage can be set to about the second power supply voltage. In addition, the through current when the output signal of the first input CMOS inverter is at a low level can be reduced, and the through current when the output signal of the first input CMOS inverter is at a high level can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of a conventional input circuit.

FIG. 2 is a circuit diagram showing an example of a conventional input circuit.

FIG. 3 is a circuit diagram showing an example of an input circuit according to the present invention.

FIG. 4 is a circuit diagram showing an example of an input circuit according to the present invention.

FIG. 5 is a circuit diagram showing an example of an input circuit according to the present invention.

FIG. 6 is a circuit diagram showing an example of an input circuit according to the present invention.

FIG. 7 is a circuit diagram showing an example of an input circuit according to the present invention.

FIG. 8 is a circuit diagram showing an example of an input circuit according to the present invention.

FIG. 9 is a circuit diagram illustrating an example of an input circuit according to the present invention.

FIG. 10 is a time chart illustrating the operation of the input circuit according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... input terminal, 2 ... output terminal, 3, 4, T1, T3 ... terminal, 10 ... input protection circuit, 11, 21, 46 ... P channel type MOS transistor, 12, 22, 56 ... N channel type MOS transistor, 20 CMOS inverter (first input CMOS inverter), 25 NOR circuit, 30 CMOS inverter (second CMOS inverter), 40 first voltage supply circuit, 45 first reference voltage generation circuit, 50 Second voltage supply circuit, 55 ... second reference voltage generation circuit, 100, 200, 300, 50
0, 700, 800, 900 ... input circuits, a, b, c,
d, e, f, g nodes, CE chip enable signal, GND second power supply voltage, Si input signal, So
Output signal, SW1 to SW4 switch means, T2 supply terminal of first reference voltage VCCL, T4 supply terminal of second reference voltage VCCL, Vcc first power supply voltage, VCC
H: first reference voltage, VCCL: second reference voltage, V
H, VL: terminal voltage of output terminal 2, Vih: input signal Si
Is the input signal voltage when V is high, Vil.
The input signal voltage when i is at a low level.

Claims (23)

[Claims] 1. A CMO in which a P-channel MOS transistor and an N-channel MOS transistor are complementarily connected.
An input circuit comprising: a CMOS inverter configured by an S logic circuit; and a first voltage supply circuit that supplies one of a first power supply voltage and a first reference voltage to a source of the P-channel MOS transistor. Wherein the input terminal of the input circuit is connected to the input terminal of the CMOS inverter, and the first voltage supply circuit changes the first power supply voltage when an output signal of the CMOS inverter is at a high level. Supplying the first reference voltage to the source when the output signal is at a low level; and supplying the input signal voltage when the input signal of the CMOS inverter is at a high level to the first reference voltage. An input circuit in which the difference voltage subtracted from the input voltage is smaller than the absolute value of the threshold voltage of the P-channel MOS transistor. 2. The first reference voltage has a value equal to or higher than the input signal voltage when the input signal of the CMOS inverter is at a high level, and lower than the first power supply voltage. Input circuit. 3. The first voltage supply circuit includes: first switch means connected between a source of the P-channel MOS transistor and a supply terminal of the first power supply voltage; A second switch connected between the source of the MOS transistor and the supply terminal of the first reference voltage, wherein one of the first and second switch is The other is off, the first switch is on when the output signal of the CMOS inverter is high, and the second switch is on when the output signal is low. 2. The input circuit according to claim 1, wherein: 4. An output terminal of the CMOS inverter includes C
A second CMOS inverter constituted by a MOS logic circuit is connected, and a control terminal of the first switch means is connected to the second CM.
An output terminal of the OS inverter; a control terminal of the second switch means is connected to an output terminal of the CMOS inverter; and the first and second switch means are each a P-channel MOS transistor. The input circuit according to claim 3, wherein 5. The input circuit includes a diode or a diode-connected MOS transistor, and the diode is provided between a supply terminal of the first power supply voltage and a supply terminal of the first reference voltage. 2. The input circuit according to claim 1, wherein the MOS transistors connected in a diode connection are connected in a forward direction. 6. An N-channel type M of said CMOS inverter.
A second power supply voltage is supplied to a source of the OS transistor, and a difference voltage obtained by subtracting the second power supply voltage from the input signal voltage when the input signal is at a low level is a difference voltage of the N-channel MOS transistor. 2. The input circuit according to claim 1, wherein the input voltage is smaller than an absolute value of the threshold voltage. 7. The input circuit has an input protection circuit using a P-channel MOS transistor and an N-channel MOS transistor, wherein the input protection circuit includes a gate-source connection of the P-channel MOS transistor. The source of the P-channel MOS transistor is supplied with the first power supply voltage. The drains of the P-channel MOS transistor and the N-channel MOS transistor are input terminals of the input circuit. 7. The input according to claim 6, wherein a gate and a source of the N-channel MOS transistor are connected to each other, and the source of the N-channel MOS transistor is supplied with the second power supply voltage. circuit. 8. The input circuit according to claim 1, wherein the input signal from the input terminal of the input circuit is an output signal of a transistor / transistor logic circuit. 9. A CMO in which a P-channel MOS transistor and an N-channel MOS transistor are complementarily connected.
An input circuit comprising: a CMOS inverter configured by an S logic circuit; and a second voltage supply circuit that supplies one of a second power supply voltage and a second reference voltage to a source of the N-channel MOS transistor. The input terminal of the input circuit is connected to the input terminal of the CMOS inverter, and the second voltage supply circuit supplies the second reference voltage when the output signal of the CMOS inverter is at a high level. Supplying the second power supply voltage to the source when the output signal is at a low level; and supplying the second reference voltage from the input signal voltage when the input signal of the CMOS inverter is at a low level. An input circuit having a difference voltage less than the absolute value of the threshold voltage of the N-channel MOS transistor. 10. The second reference voltage has a value lower than the input signal voltage when the input signal of the CMOS inverter is at a low level and higher than the second power supply voltage. Input circuit. 11. The second voltage supply circuit includes: a third switch connected between a source of the N-channel MOS transistor and a supply terminal of the second power supply voltage; A fourth switch connected between the source of the MOS transistor and the supply terminal of the second reference voltage, wherein the third and fourth switch are connected when one of them is in an on state. The other is off, the third switch is on when the output signal of the CMOS inverter is low, and the fourth switch is on when the output signal is high. The input circuit according to claim 9. 12. A second CMOS inverter constituted by a CMOS logic circuit is connected to an output terminal of said CMOS inverter, and a control terminal of said third switch means is connected to said second CM.
An output terminal of the OS inverter; a control terminal of the fourth switch means is connected to an output terminal of the CMOS inverter; and the third and fourth switch means are N-channel MOS transistors, respectively. The input circuit according to claim 11, wherein 13. The input circuit includes a diode or a MOS transistor connected in a diode connection, wherein the diode is provided between a supply terminal of the second power supply voltage and a supply terminal of the second reference voltage. 10. The input circuit according to claim 9, wherein a MOS transistor connected in a diode connection is connected in a forward direction. 14. A first power supply voltage is supplied to a source of a P-channel MOS transistor of the CMOS inverter, and the input signal voltage when the input signal is at a high level is subtracted from the first power supply voltage. 10. The input circuit according to claim 9, wherein the difference voltage is smaller than an absolute value of a threshold voltage of the P-channel MOS transistor. 15. The input circuit has an input protection circuit using a P-channel type MOS transistor and an N-channel type MOS transistor. In the input protection circuit, between the gate and the source of the P-channel type MOS transistor The source of the P-channel MOS transistor is supplied with the first power supply voltage. The drains of the P-channel MOS transistor and the N-channel MOS transistor are input terminals of the input circuit. 15. The input according to claim 14, wherein a gate and a source of the N-channel MOS transistor are connected, and a source of the N-channel MOS transistor is supplied with the second power supply voltage. circuit. 16. The input circuit according to claim 9, wherein an input signal from an input terminal of said input circuit is an output signal of a transistor / transistor logic circuit. 17. A CM in which a P-channel MOS transistor and an N-channel MOS transistor are complementarily connected.
A CMOS inverter constituted by an OS logic circuit; a first voltage supply circuit for supplying one of a first power supply voltage and a first reference voltage to a source of the P-channel MOS transistor; An input circuit having a second voltage supply circuit for supplying one of a second power supply voltage and a second reference voltage to a source of a MOS transistor, wherein an input terminal of the input circuit is an input terminal of the CMOS inverter. The first voltage supply circuit supplies the first power supply voltage to the source when the output signal of the CMOS inverter is at a high level, and supplies the first power supply voltage to the source when the output signal is at a low level. The second voltage supply circuit supplies the first reference voltage to the source, and the second voltage supply circuit outputs the second reference voltage when an output signal of the CMOS inverter is at a high level. And when the output signal is at a low level, the second power supply voltage is supplied to the source. When the input signal of the CMOS inverter is at a high level, the input signal voltage is supplied to the first The difference voltage subtracted from the reference voltage is smaller than the absolute value of the threshold voltage of the P-channel MOS transistor, and the second reference voltage is subtracted from the input signal voltage when the input signal of the CMOS inverter is at a low level. An input circuit wherein the difference voltage is smaller than an absolute value of a threshold voltage of the N-channel MOS transistor. 18. The first reference voltage has a value equal to or higher than the input signal voltage when the input signal of the CMOS inverter is at a high level and lower than the first power supply voltage; 18. The reference voltage of claim 17 is lower than the input signal voltage when the input signal of the CMOS inverter is at a low level and higher than the second power supply voltage.
Input circuit as described. 19. The first voltage supply circuit, comprising: first switch means connected between a source of the P-channel MOS transistor and a supply terminal of the first power supply voltage; A second switch connected between the source of the MOS transistor and the supply terminal of the first reference voltage, wherein one of the first and second switch is The other is off, the first switch is on when the output signal of the CMOS inverter is high, and the second switch is on when the output signal is low. The second voltage supply circuit includes: third switch means connected between a source of the N-channel MOS transistor and a supply terminal of the second power supply voltage; And a fourth switch connected between the source of the channel type MOS transistor and the supply terminal of the second reference voltage, wherein one of the third and fourth switch is turned on. In the case, the other is in the off state, the third switch means is on when the output signal of the CMOS inverter is low level, and the fourth switch means is on when the output signal is high level. 18. The state of claim 17
Input circuit as described. 20. A second CMOS inverter constituted by a CMOS logic circuit is connected to an output terminal of said CMOS inverter, and a control terminal of said first switch means is connected to said second CM.
The control terminal of the second switch is connected to the output terminal of the OS inverter, the control terminal of the second switch is connected to the output terminal of the CMOS inverter, and the control terminal of the third switch is the second CM.
An output terminal of the OS inverter; a control terminal of the fourth switch means is connected to an output terminal of the CMOS inverter; and the third and fourth switch means are N-channel MOS transistors, respectively. 20. The input circuit according to claim 19, wherein said first and second switch means are each a P-channel MOS transistor. 21. The input circuit includes a diode or a MOS transistor connected in a diode connection. A diode or a MOS transistor is connected between a supply terminal of the first power supply voltage and a supply terminal of the first reference voltage. A diode-connected MOS transistor is connected in the forward direction, and a diode or a diode-connected MOS transistor is connected between the second power supply voltage supply terminal and the second reference voltage supply terminal. The input circuit according to claim 17, wherein the input circuit is connected in a direction. 22. The input circuit has an input protection circuit using a P-channel MOS transistor and an N-channel MOS transistor, wherein the input protection circuit includes a gate-source connection of the P-channel MOS transistor. The source of the P-channel MOS transistor is supplied with the first power supply voltage. The drains of the P-channel MOS transistor and the N-channel MOS transistor are input terminals of the input circuit. 18. The input according to claim 17, wherein a gate and a source of the N-channel MOS transistor are connected to each other, and the second power supply voltage is supplied to a source of the N-channel MOS transistor. circuit. 23. The input circuit according to claim 17, wherein the input signal from the input terminal of the input circuit is an output signal of a transistor / transistor logic circuit.