JP2013118550A - Voltage detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage detection circuit that has a high accuracy threshold voltage in a small circuit area.SOLUTION: A voltage detection circuit 10 comprises: a P channel transistor 11 having a source connected to an application end of a supply voltage VDD to be monitored, a drain connected to an application end of an output signal OUT, a gate connected to an application end of a bias voltage VBP, and an on threshold voltage VonP; an N channel transistor 12 having a source connected to an application end of a ground voltage GND, a drain connected to the application end of the output signal OUT, a gate connected to an application end of a bias voltage VBN, and an on threshold voltage VonN (≠VonP); and a bias voltage generation section 13 for variably controlling the bias voltage VBP in response to the on threshold voltage VonP, and variably controlling the bias voltage VBN in response to the second on threshold voltage VonN.

Description

  The present invention relates to a voltage detection circuit.

  FIG. 13 is a circuit diagram showing a conventional example of a voltage detection circuit. In the voltage detection circuit 100 of this conventional example, the comparator 101 receives the detection voltage VDD ′ (= the divided voltage of the power supply voltage VDD) input from the connection node between the resistor 102 and the resistor 103 and the reference voltage generation unit 104. The output signal OUT is generated by comparing with a predetermined reference voltage VREF. The output signal OUT is at a high level if the detection voltage VDD 'is higher than the reference voltage VREF, and is at a low level if the detection voltage VDD' is lower than the reference voltage VREF.

  As an example of the prior art related to the present invention, in Patent Document 1, for PMOSFET and NMOSFET forming a CMOS inverter, the on-threshold voltage of PMOSFET is smaller than the on-threshold voltage of NMOSFET and the power supply voltage is the threshold voltage. When the power supply voltage is larger than the threshold voltage, the drain current of the NMOSFET is larger than the drain current of the PMOSFET. A power-on reset circuit in which a PMOSFET and an NMOSFET are designed is disclosed.

JP 2002-261595 A

  Since the voltage detection circuit 100 of the conventional example includes the comparator 101 and the reference voltage generation unit 104 as constituent elements, there is a problem that a large number (for example, 100 or more) of transistors are required and the circuit area is large.

  Further, the power-on reset circuit disclosed in Patent Document 1 has a problem that the accuracy of the threshold voltage is low.

  In view of the above problems found by the inventors of the present application, an object of the present invention is to provide a voltage detection circuit having a small circuit area and high threshold voltage accuracy.

  In the voltage detection circuit according to the present invention, the source is connected to the application terminal of the power supply voltage to be monitored, the drain is connected to the application terminal of the output signal, and the gate is connected to the application terminal of the first bias voltage. A first P-channel transistor having a first on-threshold voltage; a source connected to a ground voltage application end, a drain connected to the output signal application end, and a gate a second bias A first N-channel transistor connected to a voltage application end and having a second on-threshold voltage different from the first on-threshold voltage; and variably controlling the first bias voltage according to the first on-threshold voltage; And a bias voltage generator that variably controls the second bias voltage in accordance with the second on-threshold voltage. There is a (first configuration).

  In the voltage detection circuit having the first configuration, when the power supply voltage is lower than the threshold voltage, the drain current flowing through the first N-channel transistor is larger than the drain current flowing through the first P-channel transistor. When the power supply voltage is higher than the threshold voltage, the drain current flowing through the first P-channel transistor may be larger than the drain current flowing through the first N-channel transistor (second configuration).

  Further, in the voltage detection circuit having the second configuration, the bias voltage generation unit decreases the first bias voltage as the first on-threshold voltage is higher, and decreases the first bias voltage as the first on-threshold voltage is lower. The first bias voltage is variably controlled to increase the bias voltage, the second bias voltage is increased as the second on-threshold voltage is higher, and the second bias voltage is increased as the second on-threshold voltage is lower. A configuration (third configuration) for performing variable control of the second bias voltage may be adopted so as to lower the voltage.

  In the voltage detection circuit having the third configuration, the bias voltage generation unit has a source connected to the application terminal of the power supply voltage, and a gate and a drain connected to the gate of the first P-channel transistor. A second P-channel transistor connected to the first P-channel transistor and paired with the first P-channel transistor; a first load connected between a gate of the first P-channel transistor and a ground voltage application terminal; A second N-channel type having a source connected to the application terminal of the ground voltage, a gate and a drain connected to the gate of the first N-channel transistor, and having a pair property with the first N-channel transistor; A transistor; connected between the gate of the first N-channel transistor and the application terminal of the power supply voltage Second load and that; configuration including better to (fourth configuration).

  In the voltage detection circuit having the fourth configuration, the first load may be a third N-channel transistor, and the second load may be a third P-channel transistor (fifth configuration).

  In the voltage detection circuit having the fifth configuration, the power supply voltage is applied to the gate of the third N-channel transistor, and the ground voltage is applied to the gate of the third P-channel transistor. It is preferable to adopt the configuration (sixth configuration).

  The voltage detection circuit having the fifth configuration includes a fourth P-channel transistor having a source connected to the power supply voltage application terminal and a drain connected to the gate of the first P-channel transistor; A fourth N-channel transistor having a source connected to the ground voltage application terminal and a drain connected to a gate of the first N-channel transistor; and the third N-channel transistor and the first N-channel transistor. The 3P-channel transistor, and the fourth P-channel transistor and the fourth N-channel transistor may all be configured to be on / off controlled according to an enable signal (seventh configuration).

  The voltage detection circuit having the seventh configuration may have a configuration (eighth configuration) further including an output logic fixing unit that fixes the logic level of the output signal according to the enable signal.

  According to the present invention, it is possible to provide a voltage detection circuit having a small circuit area and high threshold voltage accuracy.

The figure which shows 1st Embodiment of a voltage detection circuit. The figure which shows the relationship between power supply voltage VDD and the output signal OUT Diagram for explaining the principle of voltage detection operation The figure which shows the relationship between power supply voltage VDD and drain current IDSP and IDSN The figure which shows a mode that the threshold voltage Vth is fluctuate | varied by element dispersion | variation. The figure which shows a mode that the threshold voltage Vth is fluctuate | varied by element dispersion | variation. The figure which shows 2nd Embodiment of a voltage detection circuit. The figure which shows 3rd Embodiment of a voltage detection circuit. The figure which shows the 1st application example of a voltage detection circuit. Time chart for explaining the operation of the first application example The figure which shows the 2nd application example of a voltage detection circuit. Time chart for explaining the operation of the second application example The figure which shows one prior art example of the voltage detection circuit

<First Embodiment>
FIG. 1 is a diagram showing a first embodiment of a voltage detection circuit. The voltage detection circuit 10 according to the first embodiment includes a P-channel MOS (metal oxide semiconductor) field effect transistor 11 and an N-channel MOS field effect transistor 12.

  The source of the transistor 11 is connected to the application end of the power supply voltage VDD to be monitored. The drain of the transistor 11 is connected to the application terminal for the output signal OUT. The gate of the transistor 11 is connected to the application terminal of the bias voltage VBP. The source of the transistor 12 is connected to the application terminal of the ground voltage GND. The drain of the transistor 12 is connected to the application terminal for the output signal OUT. The gate of the transistor 12 is connected to the application terminal for the bias voltage VBN.

  As the bias voltage VBP applied to the gate of the transistor 11, for example, the ground voltage GND is fixedly set. In addition, as the bias voltage VBN applied to the gate of the transistor 11, for example, the power supply voltage VDD is fixedly set.

  The channel length of the transistor 11 is designed to be shorter than the channel length of the transistor 12. On the other hand, the channel width of the transistor 11 is designed to be the same size as the channel width of the transistor 12. By performing such an element design, the on-threshold voltage VonP of the transistor 11 becomes higher than the on-threshold voltage VonN of the transistor 12.

  FIG. 2 is a diagram illustrating the relationship between the power supply voltage VDD and the output signal OUT. As shown in FIG. 2, in the voltage detection circuit 10 according to the first embodiment, when the power supply voltage VDD is lower than the predetermined threshold voltage Vth, the output signal OUT becomes low level, and the power supply voltage VDD becomes lower than the threshold voltage Vth. When it exceeds, the output signal OUT becomes high level. Hereinafter, the principle of such voltage detection operation will be described in detail.

  FIG. 3 is a diagram for explaining the principle of the voltage detection operation. As shown in FIG. 3, it is assumed that the drain current IDSP flows through the transistor 11 in a state where the power supply voltage VDD is applied to the source of the transistor 11 and the ground voltage GND is applied to the drain and the gate. On the other hand, in the state where the ground voltage GND is applied to the source of the transistor 12 and the power supply voltage VDD is applied to the drain and the gate, the drain current IDSN flows through the transistor 12.

  FIG. 4 is a diagram showing the relationship between the power supply voltage VDD and the drain currents IDSP and IDSN. As described above, the on-threshold voltage VonN of the transistor 12 that is a long channel is lower than the on-threshold voltage VonP of the transistor 11 that is a short channel. Therefore, the drain current IDSN rises more steeply than the drain current IDSP as the power supply voltage VDD increases. However, since the short-channel transistor 11 has a smaller on-resistance than the long-channel transistor 12, when the power supply voltage VDD is sufficiently high and the transistors 11 and 12 are fully turned on, the drain current IDSP Is larger than the drain current IDSN.

  Due to the difference in behavior between the drain currents IDSP and IDSN described above, in the region where the power supply voltage VDD is lower than the threshold voltage Vth (weak inversion region), the drain current IDSN flowing through the transistor 12 is more than the drain current IDSP flowing through the transistor 11. Also grows. As a result, the output signal OUT becomes low level. On the other hand, in a region where the power supply voltage VDD is higher than the threshold voltage Vth (strong inversion region), the drain current IDSP flowing through the transistor 11 is larger than the drain current IDSN flowing through the transistor 12. As a result, the output signal OUT becomes high level.

  Therefore, in the voltage detection circuit 10 of the first embodiment, an output whose logic level is switched according to whether the power supply voltage VDD is higher or lower than the threshold voltage Vth without using a comparator or a reference voltage generation unit having a large circuit area. A signal OUT can be generated. Note that the threshold voltage Vth can be arbitrarily set by adjusting W / L [width / length] of the transistors 11 and 12.

<Influence on characteristics due to element variation>
5 and 6 are diagrams showing how the threshold voltage Vth fluctuates due to element variations of the transistors 11 and 12, respectively. When the relationship between the power supply voltage VDD and the bias currents IDSP and IDSN is shown by the solid line in FIG. 5, the output signal OUT is when the power supply voltage VDD is lower than the threshold voltage Vth, as shown by the solid line in FIG. It becomes a low level and becomes a high level when the power supply voltage VDD is higher than the threshold voltage Vth.

  However, when each of the on-threshold voltages VonP and VonN varies due to element variations of the transistors 11 and 12, an unintended variation occurs in the threshold voltage Vth of the voltage detection circuit 10.

  For example, as indicated by a broken line in FIG. 5, the on-threshold voltage VonP of the transistor 11 increases and the bias current IDSP decreases (IDSP → IDSP ′), and the on-threshold voltage VonN of the transistor 12 decreases and the bias current When the IDSN increases (IDSN → IDSN ′), the threshold voltage Vth of the voltage detection circuit 10 increases from a desired value (Vth → Vth ′). As a result, as shown by the broken line in FIG. 6, when the power supply voltage VDD rises, the output signal OUT rises from the low level to the high level later than expected.

Thus, it can be said that the voltage detection circuit 10 of the first embodiment has room for further improvement in that the accuracy of the threshold voltage Vth is low.

Second Embodiment
FIG. 7 is a diagram illustrating a second embodiment of the voltage detection circuit. The voltage detection circuit 10 of the second embodiment is characterized in that a bias voltage generation unit 13 is further added on the basis of the first embodiment. Therefore, the same components as those in the first embodiment are denoted by the same reference numerals as those in FIG. 1, and redundant descriptions are omitted. In the following, the characteristic portions of the second embodiment are mainly described.

  The bias voltage generation unit 13 includes a P-channel MOS field effect transistor 131, an N-channel MOS field effect transistor 132, an N-channel MOS field effect transistor 133, and a P-channel MOS field effect transistor 134.

  The source of the transistor 131 is connected to the application terminal of the power supply voltage VDD. The gate and drain of the transistor 131 are both connected to the gate of the transistor 11. The transistor 131 is paired with the transistor 11. Therefore, the same element variation occurs in the transistors 11 and 131, and each on-threshold voltage VonP varies with the same behavior.

  The source of the transistor 132 is connected to the application terminal of the ground voltage GND. The drain of the transistor 132 is connected to the gate of the transistor 11. The gate of the transistor 132 is connected to the application terminal of the power supply voltage VDD. Note that a load such as a resistor or a current source can be used instead of the transistor 132.

  The source of the transistor 133 is connected to the application terminal of the ground voltage GND. The gate and drain of the transistor 133 are both connected to the gate of the transistor 12. The transistor 133 is paired with the transistor 12. Therefore, the same element variations occur in the transistors 12 and 133, and the on-threshold voltages VonN vary with the same behavior.

  The source of the transistor 134 is connected to the application terminal of the power supply voltage VDD. The drain of the transistor 134 is connected to the gate of the transistor 12. The gate of the transistor 134 is connected to the application terminal of the ground voltage GND. Note that a load such as a resistor or a current source can be used instead of the transistor 134.

  In the bias voltage generation unit 13 configured as described above, when the on-threshold voltage VonP of the transistor 11 decreases due to element variation, the on-threshold voltage VonP of the transistor 131 also decreases with the same behavior. As a result, the forward drop voltage Vf of the diode-connected transistor 131 becomes low, and the bias voltage VBP (= VDD−Vf) rises so as to cancel out the decrease in the on-threshold voltage VonP. Accordingly, it is possible to prevent an increase in the bias current IDSP due to a decrease in the on-threshold voltage VonP.

  Conversely, when the on-threshold voltage VonP of the transistor 11 rises due to element variation, the on-threshold voltage VonP of the transistor 131 also rises with the same behavior. As a result, the forward drop voltage Vf of the diode-connected transistor 131 is increased, so that the bias voltage VBP (= VDD−Vf) is decreased so as to cancel the increase of the on-threshold voltage VonP. Accordingly, it is possible to prevent a decrease in the bias current IDSP due to an increase in the on-threshold voltage VonP.

  In addition, when the on-threshold voltage VonN of the transistor 12 decreases due to element variation, the on-threshold voltage VonN of the transistor 133 also decreases with the same behavior. As a result, the forward drop voltage Vf of the diode-connected transistor 133 is lowered, so that the bias voltage VBN (= Vf) is lowered so as to cancel out the lowered amount of the on-threshold voltage VonN. Therefore, it is possible to prevent an increase in the bias current IDSN due to a decrease in the on-threshold voltage VonN.

  Conversely, when the on-threshold voltage VonN of the transistor 12 rises due to element variation, the on-threshold voltage VonN of the transistor 133 also rises with the same behavior. As a result, the forward drop voltage Vf of the diode-connected transistor 133 is increased, so that the bias voltage VBN (= Vf) is decreased so as to cancel the increase in the on-threshold voltage VonN. Accordingly, it is possible to prevent a decrease in the bias current IDSN due to an increase in the on-threshold voltage VonN.

  As described above, the bias voltage generation unit 13 variably controls the bias voltage VBP in accordance with the on-threshold voltage VonP of the transistor 11, and variably controls the bias voltage VBN in accordance with the on-threshold voltage VonP of the transistor 12.

  More specifically, the bias voltage generator 13 variably controls the bias voltage VBP so that the bias voltage VBP is lowered as the on-threshold voltage VonP is increased and the bias voltage VBP is increased as the on-threshold voltage VonP is decreased. . Further, the bias voltage generator 13 variably controls the bias voltage VBN so that the bias voltage VBN is increased as the on-threshold voltage VonN is increased, and the bias voltage VBN is decreased as the on-threshold voltage VonN is decreased.

  By adopting such a configuration, the threshold voltage Vth of the voltage detection circuit 10 can be kept constant without depending on element variations of the transistors 11 and 12, so that the circuit area is small and the threshold voltage Vth is highly accurate. The detection circuit 10 can be provided.

<Third Embodiment>
FIG. 8 is a diagram illustrating a third embodiment of the voltage detection circuit. The voltage detection circuit 10 of the third embodiment is characterized in that it is further provided with an enable function on the basis of the second embodiment. Therefore, the same components as those in the second embodiment are denoted by the same reference numerals as those in FIG. 7, and redundant descriptions are omitted. In the following, the characteristic portions of the third embodiment are mainly described.

  In order to realize the enable function, the voltage detection circuit 10 of the third embodiment further includes a P-channel MOS field effect transistor 14 and an N-channel MOS field effect transistor 15 in addition to the components of the second embodiment. Inverter 16 and three-state inverter 17.

  The source of the transistor 14 is connected to the application end of the power supply voltage VDD. The drain of the transistor 14 is connected to the gate of the transistor 11. The source of the transistor 15 is connected to the application terminal of the ground voltage GND. The drain of the transistor 15 is connected to the gate of the transistor 12. The gates of the transistors 132 and 14 are both connected to the output terminal of the inverter 16. The input terminal of the inverter 16 is connected to the application terminal of the enable signal EN. The gates of the transistors 134 and 15 are connected to the application terminal of the enable signal EN. The input terminal of the three-state inverter 17 is connected to the application terminal for the power supply voltage VDD. The output terminal of the three-state inverter 17 is connected to the application terminal for the output signal OUT. The control end of the three-state inverter 17 is connected to the output end of the inverter 16.

  In the voltage detection circuit 10 having the above-described configuration, the transistors 14 and 15 and the transistors 131 and 133 are both turned on / off according to the enable signal EN.

  More specifically, when the enable signal EN is at a high level, the transistors 132 and 134 are turned off and the transistors 14 and 15 are turned on. Therefore, the output operation of the bias voltage generator 13 is stopped, the bias voltage VBP is raised to the power supply voltage VDD, and the bias voltage VBN is lowered to the ground voltage GND. As a result, both transistors 11 and 12 are turned off. When the enable signal EN is at a high level, the three-state inverter 17 is in a state where its output operation is permitted. Therefore, the output signal OUT is fixed at a low level without depending on the power supply voltage VDD.

  On the other hand, when the enable signal EN is at a low level, the transistors 132 and 134 are turned on and the transistors 14 and 15 are turned off. Therefore, the bias voltages VBP and VBN are applied from the bias voltage generator 13 to the gates of the transistors 11 and 12. As a result, the transistors 11 and 12 become conductive according to the power supply voltage VDD. When the enable signal EN is at a low level, the 3-state inverter 17 is in a state where its output operation is prohibited (output high impedance state). Therefore, the output signal OUT has a logic level corresponding to the conduction state of the transistors 11 and 12 as described above.

  With such a configuration, the detection operation of the voltage detection circuit 10 can be turned on / off as necessary, so that power consumption can be reduced. For example, when the power supply voltage VDD is started, the enable signal EN is set to a low level and the voltage detection circuit 10 is turned on. After the rising edge of the output signal OUT is detected, the enable signal EN is set to a high level and the voltage detection circuit 10 is turned off. As a result, the power consumption of the voltage detection circuit 10 can be reduced.

  In the third embodiment described above, the configuration using the three-state inverter 17 as an example of the output logic fixing unit that fixes the logic level of the output signal OUT according to the enable signal EN has been described. The configuration of the present invention is not limited to this, and a three-state buffer may be used as the output logic fixing unit, or between the application terminal of the fixed voltage and the application terminal of the output signal OUT / An analog switch for blocking may be used.

  In the third embodiment, the description has been given by taking as an example a configuration in which the enable function is added to the voltage detection circuit 10 of the second embodiment, but the configuration of the present invention is not limited to this. A configuration in which an enable function is added to the voltage detection circuit 10 of the first embodiment (in other words, a configuration in which the bias adjustment function is excluded from the third embodiment) may be employed.

<First application example>
FIG. 9 is a diagram illustrating a first application example of the voltage detection circuit 10. In the first application example, the power supply voltage VDD is supplied to both the voltage detection circuit 10 and the electronic circuit 20, and the output signal OUT of the voltage detection circuit 10 is used as a power-on reset signal of the electronic circuit 20.

  FIG. 10 is a time chart for explaining the operation of the first application example, in which the power supply voltage VDD, the output signal OUT, and the operation state of the electronic circuit 20 are depicted in order from the top. When the power supply voltage VDD is lower than the threshold voltage Vth, the output signal OUT is at a low level, and the electronic circuit 20 is in a reset state. As a result, it is possible to prevent malfunction during power-on. On the other hand, when the power supply voltage VDD becomes higher than the threshold voltage Vth, the output signal OUT becomes high level, and the normal operation of the electronic circuit 20 is started.

  Thus, by using the voltage detection circuit 10 as a means for generating a power-on reset signal, it is possible to reduce the size of the set on which the voltage detection circuit 10 is mounted.

<Second application example>
FIG. 11 is a diagram illustrating a second application example of the voltage detection circuit 10. In the second application example, the power supply voltage VDD1 is supplied to the electronic circuit 30, and the power supply voltage VDD2 is supplied to both the voltage detection circuit 10 and the electronic circuit 40. There is a master-slave relationship between the electronic circuit 30 and the electronic circuit 40, and the electronic circuit 30 generates the control signal CTRL of the electronic circuit 40 based on the output signal OUT of the voltage detection circuit 10. The electronic circuit 30 also has a function of periodically turning on / off the voltage detection circuit 10 using the enable signal EN.

  FIG. 12 is a time chart for explaining the operation of the second application example, in which the power supply voltage VDD2, the enable signal EN, the output signal OUT, and the control signal CTRL are depicted in order from the top. When the enable signal EN is lowered to a low level (a logic level for permitting the operation of the voltage detection circuit 10), if the power supply voltage VDD2 exceeds the threshold voltage Vth, the output signal OUT is a high level. It becomes. At this time, the electronic circuit 30 determines that the power supply voltage VDD2 is supplied to the electronic circuit 40, and outputs a control signal CTRL for setting the electronic circuit 40 to an operating state (RUN). On the other hand, when the power supply voltage VDD2 is lower than the threshold voltage Vth when the enable signal EN is lowered to the low level, the output signal OUT becomes the low level. At this time, the electronic circuit 30 determines that the power supply voltage VDD2 is not supplied to the electronic circuit 40, and outputs a control signal CTRL for causing the electronic circuit 40 to enter a standby state (WAIT).

  With such a configuration, the operation of the electronic circuit 40 can be appropriately turned on / off according to the supply state of the power supply voltage VDD2.

<Other variations>
Various technical features disclosed in the present specification can be variously modified within the scope of the technical creation in addition to the above-described embodiment. For example, the logic level inversion of various signals is arbitrary. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  The voltage detection circuit according to the present invention can be used as, for example, a power-on reset circuit.

DESCRIPTION OF SYMBOLS 10 Voltage detection circuit 11 P channel type MOS field effect transistor 12 N channel type MOS field effect transistor 13 Bias voltage generation part 131 P channel type MOS field effect transistor 132 N channel type MOS field effect transistor 133 N channel type MOS field effect transistor 134 P-channel MOS field effect transistor 14 P-channel MOS field effect transistor 15 N-channel MOS field effect transistor 16 Inverter 17 3-state inverter 20, 30, 40 Electronic circuit

Claims (8)

The source is connected to the application terminal for the power supply voltage to be monitored, the drain is connected to the application terminal for the output signal, the gate is connected to the application terminal for the first bias voltage, and the first on-threshold voltage A first P-channel transistor having:
The source is connected to the ground voltage application terminal, the drain is connected to the output signal application terminal, the gate is connected to the second bias voltage application terminal, and the first on-threshold voltage is A first N-channel transistor having a different second on-threshold voltage;
A bias voltage generator that variably controls the first bias voltage according to the first on-threshold voltage and variably controls the second bias voltage according to the second on-threshold voltage;
A voltage detection circuit comprising: When the power supply voltage is lower than the threshold voltage, the drain current flowing through the first N-channel transistor is larger than the drain current flowing through the first P-channel transistor,
When the power supply voltage is higher than the threshold voltage, the drain current flowing through the first P-channel transistor is larger than the drain current flowing through the first N-channel transistor.
The voltage detection circuit according to claim 1. The bias voltage generator is
The first bias voltage is variably controlled such that the higher the first on-threshold voltage is, the lower the first bias voltage is, and the lower the first on-threshold voltage is, the higher the first bias voltage is.
The second bias voltage is variably controlled such that the second bias voltage is increased as the second on-threshold voltage is higher, and the second bias voltage is decreased as the second on-threshold voltage is lower.
The voltage detection circuit according to claim 2. The bias voltage generator is
A second P-channel transistor having a source connected to the power supply voltage application end, a gate and a drain connected to the gate of the first P-channel transistor, and having a pair property with the first P-channel transistor When;
A first load connected between the gate of the first P-channel transistor and the ground voltage application end;
A second N-channel transistor having a source connected to the application terminal of the ground voltage, a gate and a drain connected to the gate of the first N-channel transistor, and having a pair property with the first N-channel transistor When;
A second load connected between the gate of the first N-channel transistor and the power supply voltage application end;
The voltage detection circuit according to claim 3, further comprising: The first load is a third N-channel transistor;
The second load is a third P-channel transistor.
The voltage detection circuit according to claim 4. The power supply voltage is applied to the gate of the third N-channel transistor,
The ground voltage is applied to the gate of the third P-channel transistor.
The voltage detection circuit according to claim 5. A fourth P-channel transistor having a source connected to the power supply voltage application end and a drain connected to the gate of the first P-channel transistor;
A fourth N-channel transistor having a source connected to the ground voltage application end and a drain connected to the gate of the first N-channel transistor;
Further comprising
The third N-channel transistor and the third P-channel transistor, and the fourth P-channel transistor and the fourth N-channel transistor are all turned on / off according to an enable signal.
The voltage detection circuit according to claim 5.   The voltage detection circuit according to claim 7, further comprising an output logic fixing unit that fixes a logic level of the output signal in accordance with the enable signal.

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