JP2009282908A - Regulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage monitoring regulator outputting a stable voltage while monitoring the output voltage, with fewer elements and a compact layout size compared with a conventional one. <P>SOLUTION: This voltage monitoring regulator 10 outputs an output voltage signal Vreg held in a prescribed voltage, and also outputs a voltage monitored result of the output voltage signal Vreg as a voltage monitored signal Cout, and the voltage monitoring regulator 10 has: an amplifier 16 having an output for supplying the output voltage signal Vreg; and a comparator 62 for comparing a level of a current I1 flowing in the amplifier 16 with a prescribed value, and for outputting the voltage monitored signal Cout in response to a comparison result therein. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a regulator, and more specifically to a regulator having a voltage monitor that outputs a voltage signal maintained at a predetermined voltage and outputs a result of monitoring the voltage of the output signal as a voltage monitoring signal. It is.

  For example, as described in Patent Document 1, an integrated circuit (IC) included in various electric devices is an adjustment circuit for maintaining an output voltage at a predetermined voltage value together with other circuits. A regulator is installed. Further, as described in Patent Document 2, the regulator may be used as a power supply IC.

  Further, the regulator may be provided with an output voltage monitoring circuit for monitoring whether or not a voltage maintained at a predetermined voltage value is output. FIG. 4 shows such a conventional regulator with a voltage monitoring function. . The conventional regulator 100 with a voltage monitoring function includes a Vreg output regulator circuit 112 and a Vreg output monitoring circuit 122. The Vreg output regulator circuit 112 outputs a constant voltage output voltage signal Vreg and a Vreg output monitoring circuit 122. Receives the output voltage signal Vreg and outputs a Vreg voltage monitoring signal (Cout).

  The Vreg output regulator circuit 112 has a grounded DC power supply 114, the output of the DC power supply 114 is connected to the positive electrode (+ polarity) of the operational amplifier 116, and the operational amplifier 116 receives the reference voltage vref1. The operational amplifier 116 outputs an output voltage signal Vreg corresponding to a difference voltage between a reference voltage vref1 input to the positive electrode and a signal node11 input to the negative electrode (−polar electrode) described later. The output of the operational amplifier 116 is also connected to one end of a resistor 118, and the other end of the resistor 118 is a node N11 that is a connection point. The node N11 is connected to the negative electrode of the operational amplifier 116, the signal node11 is supplied to the operational amplifier 116, and is connected to one end of the grounded resistor 120. Here, the resistance ratio between the resistor 118 and the resistor 120 is 1: 1.

  The Vreg voltage monitoring circuit 122 has a grounded DC power supply 124, the output of the DC power supply 124 is connected to the positive electrode of the comparator 126, and the reference voltage vref2 is input to the comparator 126. The Vreg voltage monitoring circuit 122 receives the output voltage signal Vreg from the Vreg output regulator circuit 112. The input of the Vreg voltage monitoring circuit 122 is connected to one end of a resistor 128, and the other end of the resistor 128 is a node N12 that is a connection point. The node N12 is connected to the negative electrode of the comparator 126, and the signal node12 is supplied to the comparator 126. The node N12 is connected to one end of the grounded resistor 130. Here, the resistance ratio between the resistor 128 and the resistor 130 is 3: 5.

  The comparator 126 compares the voltage applied to the positive electrode with the voltage applied to the negative electrode, and outputs a high level voltage monitoring signal Cout when the voltage of the node 12 applied to the negative electrode exceeds the voltage to the positive electrode.

  Next, the operation of the conventional regulator 100 with an output voltage monitoring circuit will be described with reference to FIG. Here, a case where the stable Vreg output voltage of the Vreg output regulator circuit 112 is 5 volts (V) and the Vreg voltage monitoring circuit 122 outputs a high level signal when the Vreg voltage becomes 4 V or more will be described as an example.

When the reference signal vref1 = 2.5V (FIG. 5 (a)), the resistance ratio between the resistors 118 and 120 is 1: 1. When stabilized, the output voltage signal Vreg is 5.0 V (FIGS. (B) and (c)). When the reference signal vref2 = 2.5V (FIG. 5 (d)), the resistance ratio between the resistors 128 and 130 is 3: 5. Therefore, when the output voltage becomes 4.0V, node2 input to the comparator 126 becomes 2.5V. After that, the high level voltage monitoring signal Cout is output (FIG. 5 (f)).
JP 2007-304850 A JP 2005-242769 A

  However, such a conventional regulator with an output voltage monitoring circuit has a problem in that the layout size increases because separate reference voltages and resistors are required for the Vreg output regulator circuit and the Vreg voltage monitoring circuit, respectively.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a regulator with an output voltage monitoring function that outputs a stable voltage while monitoring an output voltage with a smaller number of elements and a smaller layout size than conventional ones. .

  In order to solve the above-described problem, the present invention outputs an output voltage signal maintained at a predetermined voltage, and outputs a result of monitoring the voltage of the output voltage signal as a voltage monitoring signal. An amplifier having an output to be supplied and a comparator that is connected to the amplifier, compares the magnitude of the current flowing through the amplifier with a predetermined value, and outputs a voltage monitoring signal according to the comparison result.

  According to the present invention, since the voltage monitoring signal is output by comparing the magnitude of the current flowing through the amplifier with a predetermined value, it can be configured with a smaller number of elements compared to a conventional regulator with an output voltage monitoring circuit. It becomes possible. In addition, the layout size of the entire regulator can be reduced. The reduction in the number of necessary elements enables the power consumption to be suppressed, and the operation speed can be increased when starting up the regulator.

  Next, embodiments of a regulator with voltage monitoring according to the present invention will be described in detail with reference to the accompanying drawings. Referring to FIG. 1, a voltage monitoring regulator 10 according to an embodiment of the present invention is composed of a Vreg output regulator circuit 12 that smoothes and constants an input DC power supply and outputs the output voltage. Outputs signal Vreg and Vreg voltage monitoring signal (Cout). That is, it can be said that the Vreg output regulator circuit 12 also includes an output voltage monitoring circuit for monitoring whether or not the output voltage signal Vreg is normally output.

  The regulator 10 according to the present embodiment has a possibility of being disposed in anything that needs to supply a stable output voltage, for example, as a part of an IC in an electric device or as a power supply IC.

  The voltage monitoring signal Cout is used, for example, as a signal for starting the operation of another circuit, or as a warning signal when the supply of a normal voltage is suddenly stopped. Can be activated, or certain circuit operations can be reset, and various other applications can be envisaged. In other words, the voltage monitoring signal Cout can be used as a signal for the start / maintenance / termination of other operations that can be performed by other circuits depending on whether the output voltage signal Vreg is output normally or not. Have

  The Vreg output regulator circuit 12 has a DC power supply 14 whose one terminal is grounded, the other terminal of the DC power supply 14 is connected to the positive electrode (+ polarity) of the amplifier 16, and the DC power supply 14 supplies the reference voltage to the amplifier 16. Outputs vref1.

  The amplifier 16 is an operational amplifier as a differential amplifier circuit, for example, and an output voltage corresponding to a difference voltage between a reference voltage vref1 input to the positive electrode from the DC power supply 14 and a signal node1 input to a negative electrode (−polar electrode) described later. Outputs the signal Vreg. The output of the amplifier 16 is also connected to one end of a resistor 18, and the other end of the resistor 18 is a node N1 that is a connection point. The node N1 is connected to the negative electrode of the amplifier 16, the signal node1 is supplied to the amplifier 16, and is connected to one end of the resistor 20. The other end of the grounded resistor 20 is connected. In this embodiment, the resistance ratio between the resistors 18 and 20 is 1: 1. However, the resistance ratio of the two resistors is not limited to 1: 1, and other values may be appropriately selected according to the input voltage, the desired output voltage value, or the like.

  The amplifier 16 also outputs a Vreg voltage monitoring signal Cout that is a signal indicating whether or not the output voltage signal Vreg is normally output. For example, the Vreg voltage monitoring signal Cout is used as a signal for starting the operation of another circuit by notifying the rising of the voltage, and has various uses as described above.

  The resistors 18 and 20 correspond to the resistors 118 and 120 in the conventional Vreg output regulator circuit 112. In this embodiment, the resistance ratio is 1: 1, so the output voltage Vreg at the node N1 is reduced to 1/2. Let That is, the resistors 18 and 20 can be integrated as a resistor device that supplies a signal obtained by dropping the voltage of the output voltage signal Vreg by a predetermined value to the negative electrode of the amplifier 16. Also, the resistors 18 and 20 reduce the output voltage Vreg, and the voltage at the node N1 that has been lowered is input to the negative electrode of the amplifier 16 that outputs the Vreg voltage monitoring signal Cout. In this sense, the conventional Vreg voltage monitoring is performed. It can also be said that it corresponds to the resistors 128 and 130 in the circuit 122.

  Here, an example of a detailed configuration of the amplifier 16 will be described with reference to FIG. The amplifier 16 in this embodiment has a configuration in which an element such as a transistor is further added to the amplifier 116 used in the conventional regulator 100 with a voltage monitoring function. Therefore, for convenience of explanation of the present embodiment, first, a circuit configuration example of the conventional amplifier 116 shown in FIG. 6 will be described below.

  The conventional amplifier 116 includes an N-channel metal oxide semiconductor (NMOS) transistor 22 that is a kind of field effect transistor, the gate of which is connected to the negative electrode of the amplifier 116, and the gate that is a control electrode of the positive electrode of the amplifier 116. It has an NMOS transistor 24 connected. The sources 52 and 52 that are one electrode of the NMOS transistors 22 and 24 are connected in common, and the source 52 is connected to the drain that is the other electrode of the NMOS transistor 26. While the source of the NMOS transistor 26 is grounded, the gate, which is the gate electrode, is connected to the bias source, and the drain current flows through the NMOS transistor 26 by receiving the supply of the bias signal bias.

  The drain 54 of the NMOS transistor 22 is connected to the drain of a P-channel metal oxide semiconductor (PMOS) transistor 28 which is a kind of field effect transistor. Similarly, the drain 56 of the NMOS transistor 24 is connected to the drain of the PMOS transistor 30. Gates 58 and 58 as control electrodes of the PMOS transistors 28 and 30 are connected to each other, and the gate 58 is connected to the NMOS transistor 22 and the drain 54 of the PMOS transistor 28. The source of the PMOS transistor 28 is connected to the power supply voltage VDD. Similarly, the source of the PMOS transistor 30 is also connected to the power supply voltage VDD.

  The drain 56 of the NMOS transistor 24 is connected to the gate of the PMOS transistor 32. The source of the PMOS transistor 32 is connected to the power supply voltage VDD, while the drain is connected to the output of the Vreg output regulator circuit 112, and outputs the output voltage signal Vreg with a constant voltage.

  Hereinafter, returning to the description of the configuration of the amplifier 16 shown in FIG. 2, the same components as those included in the amplifier 116 of the conventional example will be described with the same reference numerals.

  The amplifier 16 includes NMOS transistors 22, 24, and 26 and PMOS transistors 28, 30, and 32 as in the case of the amplifier 116. The arrangement and connection relationship in the present embodiment is the same as the relationship described in the description of the amplifier 116. It is the same.

  As already described, the gates 58 and 58 of the PMOS transistors 28 and 30 are connected to each other, and the commonly connected gate 58 is connected to the NMOS transistor 22 and the drain 54 of the PMOS transistor 28. In the amplifier 16, the gate 58 is further connected to the gate 60 of the PMOS transistor 40. The source of the PMOS transistor 40 is connected to the power supply voltage VDD, and the drain is connected to the drain of the NMOS transistor 42 via the node N2. By being connected in this way, it functions as a so-called current mirror, and a drain current having substantially the same magnitude as the drain current flowing in the PMOS transistor 28 flows in the PMOS transistor 40.

  The source of the NMOS transistor 42 is grounded. Further, the gate of the NMOS transistor 42 is connected to a common bias source that is connected to the gate of the NMOS transistor 26, and the drain current I2 flows through the NMOS transistor 42 by receiving the supply of the bias signal bias.

As shown in FIG. 2, when the drain current flowing through the NMOS transistor 26 is I4 and the drain current flowing through the NMOS transistor 42 is I5,
I4 <(I5) / 2
The transistor dimensions (= gate width / gate length) are set so that The dimension corresponds to the driving capability of the transistor. The larger the dimension value, the larger the on-resistance and the current supply capability.

  The drain of the PMOS transistor 40 connected to the drain of the NMOS transistor 42 via the node N2 is further connected to the input of the inverter 44. The inverter 44 is, for example, a negative logic (not) gate circuit or the like, and judges the supplied signal as either a high level or a low level with reference to a predetermined threshold, and the binarized input signal A circuit that supplies an output signal with an inverted level. The inverter 44 of this embodiment receives a potential difference of N2 caused by the magnitude of the drain current flowing in the PMOS transistor 40 and the drain current flowing in the NMOS transistor 42, and if the potential difference is less than a predetermined threshold, a high level signal is received. Supply from output.

  The output of the inverter 44 is further connected to the input of the inverter 46, and the inverter 46 further inverts the high level or low level signal supplied from the inverter 44 and outputs it as the Vreg voltage monitoring signal Cout. .

  From the above description, it can be said that the NMOS transistors 26 and 42 and the inverters 44 and 46 as a whole are components of the comparator 62 that compares the magnitudes of the drain currents I4 and I5 and outputs the result.

  In this embodiment, since the high-level Vreg voltage monitoring signal Cout is designed to be output when the output voltage signal Vreg of a predetermined value or more is output, the inverters 44 and 46 are connected in series. However, the present invention is not necessarily limited to this configuration. For example, when a high level voltage monitoring signal Cout is required for the output of the voltage Vreg equal to or lower than a predetermined value, the design can be changed as appropriate.

  Next, the operation of the regulator 10 with a voltage monitoring circuit according to the present embodiment will be described with reference to FIGS. Also in this description of the operation, the output voltage Vreg of the stabilized Vreg output regulator circuit 12 is 5V, and when the output voltage signal Vreg becomes 4V or higher, the high level Vreg voltage monitoring signal Cout is output. Shall. The reference voltage vref1 is 2.5V. Of course, the value of the output voltage signal Vreg and the value of the reference voltage vref1 at which the output voltage signal Vreg and the voltage monitoring signal Cout are at the high level can be appropriately selected.

  When the amplifier 16 starts to operate, the amplifier 16 receives the 2.5V reference voltage vref1 (FIG. 3 (a)) input to the positive electrode from the DC power supply 14 and the signal node1 (FIG. 3 (b)) input to the negative electrode. An output voltage signal Vreg corresponding to the difference voltage is output (FIG. 3 (c)). That is, the voltages of the output voltage signals Vreg and node1 gradually increase from the start of the operation of the amplifier 16, and when Vreg = 5.0V, the resistance ratio of the resistor 18 and the grounded resistor 20 is 1: 1. , Node1 also becomes a stable voltage signal of 5V / 2 = 2.5V and is supplied to the negative electrode of the amplifier 16, and the amplifier 16 continues to output the output voltage signal Vreg of 5V.

  Regarding the output of the Vreg voltage monitoring signal Cout, as described above, the current flowing through the NMOS transistor 42 is I4, the current flowing through the NMOS transistor 26 is I5, and the current flowing through the NMOS transistor 22 and the PMOS transistor 28 shown in FIG. A description will be made assuming that I1, the current flowing through the NMOS transistor 24 and the PMOS transistor 30 is I2, and the current flowing through the PMOS transistor 40 is I3.

  Immediately after the operation of the amplifier 16 is started, that is, when the output voltage signal Vreg is 0V or more and less than 4V, the gate of the NMOS transistor 24 is supplied with the reference voltage vref1 stabilized at 2.5V through the positive electrode of the amplifier 16, while The voltage of node1 supplied to the gate of the NMOS transistor 22 through the negative electrode has a problem such as a threshold voltage of the gate voltage of the NMOS transistor 22, and does not reach a voltage that allows a sufficiently large drain current I1 to flow.

  For this reason, the negative voltage applied to the gate of the PMOS transistor 40 connected to the drain 54 of the NMOS transistor 22 is not sufficiently large, so that the current I3 is weak. Also, the negative voltage applied to the gate of the PMOS transistor 30 connected to the drain 54 of the NMOS transistor 22 is not sufficiently large, but since a reference voltage of 2.5 V is applied to the NMOS transistor 24 from the beginning, The current I2 has a constant magnitude from the beginning, and gradually increases as the current I1 increases. On the other hand, a constant bias voltage is applied to the NMOS transistors 26 and 42 from the beginning.

That is, the current flowing inside the amplifier 16 is
I5 = I1 + I2
I1 = I3 <I2
I3 <I4
The relationship will be established.

  At this time, since I3 <I4, the voltage of the node N2 (node2) is only lower than the threshold value of the inverter 44 in the comparator 62. Accordingly, as a result of the comparison processing, the inverter 44 outputs a high level signal, but the inverter 46 further inverts the output signal of the inverter 44 and outputs a low level Vreg voltage monitoring signal Cout.

On the other hand, when the output voltage signal Vreg is 4 V or more and 5 V or less, the voltage of node 1 supplied to the gate of the NMOS transistor 22 through the negative electrode of the amplifier 16 also reaches a sufficiently large voltage, and the negative voltage applied to the gates of the PMOS transistors 28 and 40. Since the voltage is also large enough, the current flowing inside the amplifier 16 is
I5 = I1 + I2
I1 = I2 = I3 = (I5) / 2
The relationship holds.

Here, the NMOS transistor 42
I4 <(I5) / 2
Since the dimensions are set so that the relationship is established, since I3> I4, the voltage of node2 is higher than the threshold value of the inverter 44 in the comparator 62. Accordingly, as a result of the comparison processing, the inverter 44 outputs a low level signal, but the inverter 46 further inverts the output signal of the inverter 44 and outputs a high level Vreg voltage monitoring signal Cout (FIG. 3). (d)).

  In this way, by including the output voltage monitoring circuit in the Vreg output regulator circuit 12, it is possible to configure a similar regulator circuit with fewer elements compared to the conventional regulator with an output voltage monitoring circuit, and thus to reduce the layout size of the regulator circuit. It can be made smaller. Furthermore, it is possible to save power consumption and increase the operation speed.

  The embodiment of the present invention is not limited to the above-described example. For example, the type, number, and arrangement of elements included in the output regulator circuit 12 and the amplifier 16, and the type of each transistor in the element Also, there is a possibility of design change as appropriate within the scope of the inventive idea. Also, the reference voltage vref1, the magnitude of the output voltage signal Vreg, and the reference value of the output voltage signal Vreg at which the voltage monitoring signal Cout is output at a high level can be naturally changed, and as necessary within the scope of the present invention. Thus, the resistance ratio of the resistors 18 and 20 and the dimension setting of each transistor may be changed.

It is a circuit block diagram which shows the structure of the Example of the regulator with voltage monitoring which concerns on this invention. It is a circuit block diagram which shows the structure of the amplifier shown in FIG. It is a timing chart explaining the operation timing in the Example shown in FIG. It is a circuit block diagram which shows the structure of the Example of the regulator with the conventional output voltage monitoring circuit. 5 is a timing chart for explaining operation timings in the conventional regulator shown in FIG. 4. It is a circuit block diagram which shows the structure of the conventional amplifier shown in FIG.

Explanation of symbols

10 Regulator with output voltage monitoring circuit
12 Vreg output regulator circuit
16 Amplifier
18, 20 resistance
22, 24 NMOS transistor
40 PMOS transistor
42 NMOS transistor
62 Comparator

Claims (5)

A regulator having a voltage monitor that outputs an output voltage signal maintained at a predetermined voltage and outputs a result of monitoring the voltage of the output voltage signal as a voltage monitor signal, the regulator comprising:
An amplifier having an output for providing the output voltage signal;
A regulator having a comparator that compares the magnitude of a current flowing through the amplifier with a predetermined value and outputs the voltage monitoring signal according to the comparison result. The regulator according to claim 1,
The amplifier further has a first input supplied with an input signal based on the output voltage signal and a second input supplied with a reference voltage;
A regulator having resistance means connected between an output of the amplifier and a first input. The regulator according to claim 2,
The amplifier is connected to a first input, connected to a first transistor through which a first current flows in response to the input signal, and a second input, and in response to the reference voltage and the input signal. A second transistor through which a current of
The comparator includes a third transistor that is connected to the amplifier and receives a signal related to the magnitude of the first current to flow a third current substantially similar to the first current;
The magnitude of the third current is compared with a predetermined value obtained based on the total value of the first and second currents, and a voltage monitoring signal is output according to the result. regulator. The regulator of claim 3, wherein the comparator further comprises:
A fourth transistor connected to a third transistor via a node for outputting the monitoring voltage signal;
The dimension of the fourth transistor is set so that the fourth current flowing through the fourth transistor is smaller than a predetermined value obtained based on the total value of the first and second currents.
A regulator for performing comparison by detecting a voltage at the node generated by the magnitude of the third and fourth currents.   5. The regulator according to claim 3, wherein the predetermined value obtained based on the total value of the first and second currents is one half of the total value. 6.

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