JP4202961B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a booster circuit.

FIG. 15 is a circuit diagram of a booster circuit 10 built in a conventional semiconductor device (see Patent Document 1). Booster circuit 10 includes a transistor _QNA 1 _{~QNA m} connected in series between the input IN and output OUT, and a capacitor _CA 1 to CA _m each end to the respective transistors _QNA 1 _{~QNA m} is connected Have. The other ends of the capacitors CA _{1 to} CA _m are connected to the clock supply source via the voltage converter 12.

Voltage converter 12 has a voltage conversion circuit _VB 1 through Vb _m connected to the other ends of the capacitors _CA 1 to CA _m. The voltage conversion circuits VB _{1 to} VB _m receive clock signals Φ or Φ bars that are out of phase with each other, boost the voltages of these clock signals, and supply them to the capacitors CA ₁ to CA _m . The timing chart of the clock signal Φ or Φ bar is as shown in FIG. Thereby, the booster 11 boosts the input voltage Vin and outputs an output voltage Vout higher than the input voltage Vin.

FIG. 16 is a circuit diagram showing a configuration of one of the voltage conversion circuits VB _{1 to} VB _m (hereinafter referred to as voltage conversion circuit VB). The voltage conversion circuit VB, one end connected to the voltage source Vin through an n-channel transistor _QNB 1 _{~QNB k,} the capacitor _CB 1 to CB _k which is grounded through the other end n-type transistor _QNC 1 _{~QNC k} A plurality of boosting stages. Voltage conversion circuit VB further includes p-type transistors QPA _{1 to} QPA _k . The transistors QPA _{1 to} QPA _k can connect all the capacitors CB _{1 to} CB _k in series between the input and the output.

Transistors QNB _{1 to} QNB _k and QNC _{1 to} QNC _k and transistors QPA _{1 to} QPA _k have different conductivity types, and are therefore switched alternately by the clock signal Φ or Φ bar. When the clock signal Φ or Φ bar is high, the capacitors CB _{1 to} CB _k are connected in parallel between the input voltage Vin and the ground, and when the clock signal Φ or Φ bar is low, the input voltage Vin and the output CLKOUT. Are connected in series. As the clock signal Φ or Φ bar repeats high and low as shown in FIG. 17, the voltage conversion circuit VB boosts the input voltage Vin from the output CLKOUT to any one of the capacitors CA ₁ to CA _m. Output.
JP 2002-51538 A

  By the way, it is preferable that the power supply voltage (hereinafter also simply referred to as power supply voltage) supplied from the outside of the semiconductor device is low in order to reduce power consumption. Conventionally, the power supply voltage has been gradually reduced to 5V, 3.3V (or 2.5V), and in recent years, the power supply voltage has been reduced from 3.3V to 1.8V. Thus, in the transition period in which the power supply voltage is lowered, the semiconductor device is required to cope with different power supply voltages.

  Even in a semiconductor device corresponding to a single power supply voltage in normal operation, a power supply voltage higher than the power supply voltage in normal operation may be used in a test process before shipment. For example, in order to determine an initial failure, a high voltage is used as a power source in a burn-in process in which the failure is accelerated to cause the device to fail. Therefore, it is preferable that the semiconductor device supports a plurality of power supply voltages having different voltages.

  Generally, when the operation of the semiconductor device is guaranteed when the external power supply voltage is Vccmin to Vccmax, the booster circuit is designed to output a desired output voltage when the power supply voltage is Vccmin. The internal supply voltage (hereinafter, also simply referred to as supply voltage) Vin is an external power supply voltage itself or a voltage obtained by stepping down the power supply voltage, and increases or decreases depending on the power supply voltage. Therefore, when the supply voltage Vin is in the range of Vinmin to Vinmax, the booster circuit is designed to output a desired output voltage when the supply voltage Vin is Vinmin. For example, when voltages of two different ranges of 1.8 V and 3 V are used as the power supply voltage Vcc, Vin = 1.5 V when Vcc = 1.8 V range (Vcc = 1.5 V to 2 V), When Vcc = 3V range (Vcc = 2.5V to 3.6V), Vin = 2.5V can be set. In this case, normally, the booster circuit 10 is designed to output a desired output voltage when Vcc = 1.5V, that is, Vin = 1.5V.

  However, in this case, if the supply voltage Vin is set higher according to the power supply voltage Vcc when the power supply voltage Vcc is on the Vccmax side or when the power supply voltage Vcc is higher than Vccmax in the burn-in process, the booster circuit 10 Will have excessive boost capability. For example, when the booster circuit 10 is designed to output a desired output voltage when Vcc = 1.5V and Vin = 1.5V, the booster circuit 10 has Vcc = 3V and Vin = 2.5V (> When it is set at 1.5V), it has excessive capacity.

Further, when the supply voltage Vin is set high according to the relatively high power supply voltage Vcc, all the boosting stages in the voltage conversion circuit VB boost based on the supply voltage Vin, so that the transistors in the voltage conversion circuit VB Excess voltage is applied. Therefore, some or all of the transistors QNB _{1 to} QNB _k must be high voltage transistors. Since the high breakdown voltage transistor has a lower conductance than the low breakdown voltage transistor, it is necessary to increase the size (channel width) in order to maintain the same conductance as the low breakdown voltage transistor. As a result, the parasitic capacitance increases, so that there are problems that the operation efficiency of the voltage conversion circuit VB is reduced and that the circuit area of the booster circuit 10 is increased.

  In order to cope with the above problem, for example, even when Vcc = 3V, Vin can be set to 1.5V. However, it is not preferable to step down Vcc = 3V to 1.5V because it wastes power. That is, regarding the power consumption in the Vcc = 3V range, the current consumption of the product corresponding to both the Vcc = 1.8V range and the Vcc = 3V range is the current consumption of the product corresponding to only the Vcc = 3V range. It will be bigger than that.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device including a booster circuit that outputs a more stable voltage and has a relatively small circuit area than the prior art even when external power supply voltages have a plurality of different voltage values Is to provide.

A semiconductor device according to an embodiment of the present invention includes a plurality of first switching elements connected in series from an output unit, and a plurality of first capacitors whose one ends are connected between the adjacent first switching elements. A booster circuit unit that receives a clock signal from the other end of the first capacitor and outputs a boosted voltage from the output unit;
One end is connected to the first voltage source via the second switching element, the other end is connected to the reference voltage via the third switching element, and the voltage difference between the first voltage source and the reference voltage And a plurality of boosting stages each having a second capacitor to be charged based on the first and second boosting stages, and are connected in series between a second voltage source and the other end of the first capacitor. And a plurality of fourth switching elements for controlling the number of the second capacitors connected to the first and second voltage sources based on the voltages of the first and second voltage sources, and to the other ends of the adjacent first capacitors. A voltage conversion circuit unit that outputs a reverse phase clock signal is provided ,
The fourth switching element includes the one end of the second capacitor of the boosting stage on the clock voltage source side among the adjacent boosting stages, and the other of the second capacitor of the boosting stage on the output side. Connect between the ends,
A fifth switching element connected between the one end and the other end of the second capacitor in the two boosting stages, and between the one end of each of the second capacitors in the two boosting stages. It further comprises at least one switching element among a sixth switching element to be connected and a seventh switching element for connecting between the other ends of the second capacitors in the two boosting stages. Features.

  The booster circuit incorporated in the semiconductor device according to the present invention can output a stable voltage even when externally supplied voltages have different voltage values, and has a smaller circuit area than the conventional one. In addition, when the external supply voltage is relatively high, the current consumption can be greatly reduced.

  Embodiments according to the present invention will be described below with reference to the drawings. The present invention is not limited to the following embodiments. The same components are given the same reference numbers. In the following embodiments, the effects of these embodiments are not lost even if a p-type transistor is used instead of an n-type transistor and an n-type transistor is used instead of a p-type transistor.

  Semiconductor devices according to the following embodiments include a voltage conversion circuit that can increase or decrease the number of boosting stages based on a power supply voltage between a clock supply source and a boosting unit. Thereby, the booster circuit of the semiconductor device can supply a stable output voltage in a wide range of power supply voltages. These embodiments can be used for a semiconductor device that requires a higher voltage than a power supply voltage, such as a NAND-type nonvolatile memory device.

(First embodiment)
FIG. 1 is a circuit diagram of a booster circuit 100 built in a semiconductor device according to the first embodiment of the present invention. The semiconductor device further includes, for example, a non-volatile memory device (not shown), and the booster circuit 100 outputs the boosted voltage to the non-volatile memory device.

The booster circuit 100 includes a booster unit 110 and a voltage conversion circuit unit 120. Boosting unit 110 includes n-type transistors QNA _{1 to} QNA _m and capacitors CA _{1 to} CA _m−1 . Note that m is an integer of 2 or more. The transistors QNA _{1 to} QNA _m are connected in series from the output unit OUT. Capacitors CA _{1 to} CA _m−1 have one electrode connected to a connection point between adjacent transistors among transistors QNA _{1 to} QNA _m . The other electrodes of the capacitors CA _{1 to} CA _m−1 are connected to the voltage conversion circuit unit 120.

Transistors _QNA 1 _{~QNA m} is, for example, a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor). The capacitors CA _{1 to} CA _m−1 are in electrical contact with, for example, the gate electrode, the gate insulating film, the semiconductor substrate or well diffusion layer, and the semiconductor substrate or well diffusion layer constituting the transistors QNA _{1 to} QNA _m. This is a MOS capacitor composed of a diffusion layer. The gate electrode is, for example, doped silicon, the gate insulating film is, for example, a silicon oxide film, and the well diffusion layer is, for example, an N-type well diffusion layer formed on a semiconductor substrate.

During the step-up operation, a large voltage can be applied to the insulating film between the bipolar plates of the capacitors CA _{1 to} CA _m−1 . Therefore, in order to avoid that the capacitor _{CA 1 ~CA m-1} is the dielectric breakdown, the dielectric film of the capacitor _{CA 1 ~CA m-1} using a gate insulating film of the high voltage transistor.

The voltage conversion circuit unit 120 includes voltage conversion circuits VA _{1 to} VA _m . Each of the voltage conversion circuits VA _{1 to} VA _m includes a clock input unit CLKIN, a clock output unit CLKOUT, and a mode input unit MODE. The clock signal Φ is input to the clock input section CLKIN of the voltage conversion circuit VA _2k−1 , and the clock signal Φ bar (Φ is an inverted signal of Φ) is input to the clock input section CLKIN of the voltage conversion circuit VA _2k. . Note that k is a natural number of m / 2 or less. The clock output unit CLKOUT is connected to the other electrode of the capacitors CA _{1 to} CA _m−1 or the transistor QNA ₁ . Each of the voltage conversion circuits VA _{1 to} VA _m has a boosting stage (see FIG. 2), boosts the clock signal Φ or Φ bar, and outputs the boosted signal from the clock output unit CLKOUT.

The mode signal input to the mode input unit MODE is used to change the number of boosting stages in the voltage conversion circuits VA _{1 to} VA _m based on the magnitude of the supply voltages Vin _{1 to} Vin ₅ (see FIG. 2). In the present embodiment, the mode signal has a binary value of high or low, and the value is switched according to the level of the supply voltage.

The operation of the booster circuit 100 will be described. The clock signal Φ or Φ bar repeats high and low in opposite phases as shown in FIG. The voltage conversion circuits VA _{1 to} VA _m boost the clock signal Φ or Φ bar by the number of boosting stages based on the mode signal, and use the boosted signal as the clock signal CS _OUT to the capacitors CA _{1 to} CA _m−1 . Output. The clock signal CS _OUT boosted by the voltage conversion circuit VA ₁ charges the electrode connected to the transistor QNA ₂ of the capacitor CA ₁ via the transistor QNA ₁ .

Next, the capacitor CA ₁ receives the clock signal CS _OUT bar having a phase opposite to that of the clock signal CS _OUT at the electrode connected to the voltage conversion circuit VA ₂ , and further boosts the voltage at the electrode connected to the transistor QNA _2. . As a result, the transistor QNA ₂ becomes conductive, and the capacitor CA ₁ charges the adjacent capacitor CA ₂ via the transistor QNA ₂ .

Thereafter, the capacitor CA ₂ receives the clock signal CS _OUT via the voltage conversion circuit VA ₃ and further boosts the voltage at the electrode connected to the transistor QNA ₃ . As a result, the transistor QNA ₃ becomes conductive, and the capacitor CA ₂ charges the adjacent capacitor CA ₃ via the transistor QNA ₃ . By sequentially repeating such an operation, the capacitor CA _m−1 outputs the boosted voltage from the output unit OUT as the output voltage Vout via the transistor QNA _m .

FIG. 2 is a circuit diagram showing a configuration of any _{one of} the voltage conversion circuits VA _{1 to} VA _m (hereinafter referred to as voltage conversion circuit VA). The voltage conversion circuit VA includes boosting stages BS1 to BS4, p-type transistors QPB1 to QPB5, and an OR gate G1.

  Boosting stage BS1 includes an n-type transistor QND1, n-type transistor QNE1, and capacitor CD1, boosting stage BS2 includes an n-type transistor QND2, n-type transistor QNE2, and capacitor CD2, and boosting stage BS3 includes , N-type transistor QND3, n-type transistor QNE3, and capacitor CD3, and boosting stage BS4 includes n-type transistor QND4, n-type transistor QNE4, and capacitor CD4. Transistor QND1, capacitor CD1, and transistor QNE1 are connected in series between supply voltage Vin1 and ground. Transistor QND2, capacitor CD2, and transistor QNE2 are connected in series between supply voltage Vin2 and ground. The transistor QND3, the capacitor CD3, and the transistor QNE3 are connected in series between the supply voltage Vin3 and the ground, and the transistor QND4, the capacitor CD4, and the transistor QNE4 are connected in series between the supply voltage Vin4 and the ground. It is connected to the. Clock signal CLK2 is input to the gates of transistors QND1, QND2, QNE1 and QNE2. Clock signal CLK1 is input to the gates of transistors QND3, QND4, QNE3, and QNE4.

  Transistors QPB2-QPB4 are provided between adjacent boosting stages among boosting stages BS1-BS4. The transistor QPB2 is connected between the electrode on the supply voltage Vin1 side of the capacitor CD1 and the electrode on the ground side of the capacitor CD2. Similarly, the transistor QPB3 is connected between the electrode on the supply voltage Vin2 side of the capacitor CD2 and the electrode on the ground side of the capacitor CD3. The transistor QPB4 is connected to the electrode on the supply voltage Vin3 side of the capacitor CD3 and the capacitor CD4. It is connected between the electrodes on the ground side.

  The transistor QPB1 is connected between the supply voltage Vin5 and the electrode on the ground side of the capacitor CD1, and the transistor QPB5 is connected between the electrode on the supply voltage Vin4 side of the capacitor CD4 and the clock output unit CLKOUT. Clock signal CLK2 is input to the gates of transistors QPB1 and QPB2. The clock signal CLK1 is input to each gate of the transistors QPB3 to QPB5.

  Clock signals CLK1 and CLK2 are generated by the clock signal CSIN (Φ or Φ bar) from the clock input section CLKIN. The clock signal CLK1 is the same signal as the clock signal CSIN. The OR gate G1 outputs a logical sum of the clock signal CSIN and the mode signal from the mode input terminal MODE as the clock signal CLK2.

  In the present embodiment, the transistors QND1 to QND4, QNE1 to QNE4, and QPB1 to QPB5 may be MOSFETs. Capacitors CD1 to CD4 include, for example, gate electrodes, gate insulating films, semiconductor substrates or well diffusion layers, and semiconductor contacts or well diffusion layers constituting transistors QND1 to QND4, QNE1 to QNE4, and QPB1 to QPB5. This is a MOS capacitor comprising a diffusion layer for taking The gate electrode is, for example, doped silicon, the gate insulating film is, for example, a silicon oxide film, and the well diffusion layer is, for example, an N-type well diffusion layer formed on a semiconductor substrate. Further, the n-type transistors QND1, QND2, QND3, and QND4 are preferably enhancement type transistors or depletion type transistors having a very small threshold voltage. Thereby, the capacitors CD1, CD2, CD3, and CD4 can be charged to voltages that have not dropped from the supply voltages Vin1, Vin2, Vin3, and Vin4.

  Transistors QND1 to QND4, QNE1 to QNE4, and QPB1 to QPB5 may all be low breakdown voltage transistors. The low breakdown voltage transistor is a transistor having a gate insulating film thickness of about 10 nm or less in terms of oxide film thickness. The insulating film between the electrodes of the capacitors CD1 to CD4 may also have a low breakdown voltage, that is, a film thickness of about 10 nm or less. Since the transistors QND1 to QND4, QNE1 to QNE4, and QPB1 to QPB5 are low breakdown voltage transistors, the parasitic capacitance that degrades the performance of the booster circuit is reduced, and the circuit area is also reduced. The capacitors CD1 to CD4 can have a larger capacity with a smaller area by being for low breakdown voltage. Thereby, the area of the whole booster circuit 100 is reduced. The insulating film thickness between the electrodes of capacitors CD1 to CD4 is preferably equal to the gate insulating film of any of transistors QND1 to QND4, QNE1 to QNE4, and QPB1 to QPB5 in order to facilitate manufacture.

  3 and 4 are timing charts of the clock signal CSIN and the clock signals CLK1 and CLK2 in the mode 1 and the mode 2, respectively. In mode 1 shown in FIG. 3, the mode signal is low (inactive state). This mode 1 is a mode used when the supply voltages Vin1 to Vin5 are relatively low. The case where the supply voltage is low means, for example, a case where the guaranteed range of the power supply voltage from the outside of the semiconductor device is a wide range or a dual range, and the supply voltages Vin1 to Vin5 are about the lowest voltage Vccmin within the guaranteed range.

  In mode 2 shown in FIG. 4, the mode signal is high (active state). This mode 2 is a mode used when the supply voltages Vin1 to Vin5 are relatively high. The case where the supply voltage is high is, for example, a case where the guaranteed range of the power supply voltage from the outside of the semiconductor device is a wide range or a dual range, and the supply voltages Vin1 to Vin5 are close to the maximum voltage Vccmax within the guaranteed range, or a burn-in process In this case, the supply voltages Vin1 to Vin5 are set to the voltage Vccmax or higher on a trial basis. Hereinafter, the operation of the voltage conversion circuit VA will be described for each mode.

(Mode 1)
In mode 1, the clock signals CLK1 and CLK2 are in phase and repeat high and low. As a result, all the boosting stages BS1 to BS4 operate.

  First, when the clock signals CLK1 and CLK2 are high (Vin6), the transistors QND1 to QND4 and QNE1 to QNE4 are turned on, and the transistors QPB1 to QPB5 are turned off. As a result, the capacitors CD1 to CD4 are charged between the supply voltages Vin1 to Vin4 and the ground, respectively. For example, if there is no drop in the charging voltage due to the respective threshold values of the transistors QND1 to QND4, the voltages of Vin1, Vin2, Vin3, and Vin4 are charged between the electrodes of the capacitors CD1 to CD4.

  Next, when the clock signals CLK1 and CLK2 are low (ground potential), the transistors QPB1 to QPB5 are turned on, and the transistors QND1 to QND4 and QNE1 to QNE4 are turned off. Accordingly, the capacitors CD1 to CD4 are connected in series between the supply voltage Vin5 and the clock output unit CLKOUT via the transistors QPB1 to QPB5. As a result, the clock signal CSOUT boosted from the supply voltages Vin1 to Vin5 is supplied from the clock output unit CLKOUT to any of the capacitors CA1 to CAm shown in FIG. The clock signal CSOUT is boosted to about Vin1 + Vin2 + Vin3 + Vin4 + Vin5. The voltage of the clock signal CSOUT at this time is VCLK1.

(Mode 2)
In mode 2, the clock signal CLK2 remains high, and the clock signal CLK1 repeats high and low. Thereby, boosting stages BS1 and BS2 do not operate, and only boosting stages BS3 and BS4 operate.

  First, when the clock signal CLK1 is high, the transistors QND3, QND4, QNE3 and QNE4 are turned on, and the transistors QPB3 to QPB5 are turned off. Thereby, the capacitors CD3 and CD4 are charged between the supply voltages Vin3 and Vin4 and the ground, respectively. The voltages of Vin3 and Vin4 are charged between the electrodes of capacitors CD3 and CD4, respectively.

Next, when the clock signal CLK1 is low, the transistors QPB3 to QPB5 are turned on, and the transistors QND3, QND4, QNE3, and QNE4 are turned off. Since the clock signal CLK2 is always high, the transistors QND1, QND2, QNE1 and QNE2 are on, and the transistors QPB1 to QPB2 are off. Thereby, the capacitors CD3 to CD4 are connected in series between the supply voltage Vin2 and the clock output unit CLKOUT via the transistors QND2 and QPB3 to QPB5. As a result, the clock signal CSOUT boosted from the supply voltages Vin2 to Vin4 is supplied from the clock output unit CLKOUT to any of the capacitors CA _{1 to} CA _m shown in FIG. The clock signal CSOUT is boosted to about Vin2 + Vin3 + Vin4. The voltage of the clock signal CSOUT at this time is VCLK2.

  Obviously, the voltage VCLK2 is smaller than the voltage VCLK1. For example, when supply voltages Vin1 to Vin5 are Vin, VCLK1 = 5 * Vin and VCLK2 = 3 * Vin.

  Therefore, the voltage conversion circuit VA in the present embodiment boosts the clock signal relatively large in mode 1 when the supply voltages Vin1 to Vin5 are relatively low (for example, about 1.5 V), and the supply voltages Vin1 to Vin6 are compared. When the target voltage is high (for example, about 2.5 V or more), the clock signal is boosted relatively small in mode 2.

As a result, the potential conversion circuit VA can supply the clock signal CSOUT having a stable voltage to the capacitors CA ₁ to CA _m regardless of the supply voltages Vin _{1 to} Vin 5. That is, the booster circuit 100 shown in FIG. 1 can have a stable boosting capability even when externally supplied voltages have different voltage values.

  Furthermore, according to the present embodiment, when the supply voltage is relatively high, the capacitors CD1 and CD2 in the first and second boosting stages BS1 and BS2 are not charged / discharged. Thereby, even if a supply voltage becomes large, the increase in the power consumption of the voltage conversion circuit VA is suppressed.

In the present embodiment, the voltage conversion circuits VA _{1 to} VA _m are provided corresponding to the transistors QNA _{1 to} QNA _m , respectively. However, a voltage conversion circuit may be provided for each of a plurality of transistors QNA _{1 to} QNA _m . For example, as shown in FIG. 5, two voltage conversion circuits VA may be provided corresponding to the clock signals Φ and Φbar.

  The supply voltages Vin1 to Vin5 may all be equal to facilitate voltage control of the clock output unit CLKOUT. On the other hand, one of the supply voltages Vin1 to Vin5 may be different and the other may be equal. For example, only the supply voltage Vin5 may be larger than other supply voltages.

  In this embodiment, the transistors QPB1 to QPB5, QND1 to QND4, and QNE1 to QNE4 are all low withstand voltage transistors. However, as some of the supply voltages are increased, some of these transistors have high withstand voltages. A transistor may be used. The high breakdown voltage transistor is a transistor having a gate insulating film thickness of about 10 nm or more in terms of oxide film thickness. For example, when only the supply voltage Vin2 is higher than the other supply voltages, the transistors QPB2, QND2, and QNE2 may be high voltage transistors. In this case, the size and parasitic capacitance of the transistors QPB2, QND2, and QNE2 increase, but the effect of stabilizing the boosting capability is obtained.

  In the present embodiment, the number of boosting stages is four stages BS1 to BS4. However, the number of boosting stages may be 3 or less or 5 or more. However, in actuality, in order to increase the parasitic capacitance and not increase the voltage loss, the boosting stage is preferably four or less.

  Further, in the present embodiment, the transistors QPB1 to QPB5 and the transistors QNE1 to QNE4 are driven in synchronization by clock signals CLK1 and CLK2. However, in order not to increase the voltage loss, the transistors QPB1 to QPB5 may be driven with a delay with respect to the transistors QNE1 to QNE4. Further, in this embodiment, the transistors QND1 and QND2, QNE1 and QNE2, and QPB1 and QPB2 are all input with CLK2 having an amplitude of Vin6. You may be comprised so that a signal may be input. Also, the transistors QND3 and QND4, QNE3 and QNE4, and QPB3 to QPB5 are all input with CLK1 having an amplitude of Vin6, but some of them have the same phase and different amplitude clock signals. It may be configured as follows.

(Second Embodiment)
FIG. 5 is a circuit diagram of a booster circuit 200 built in the semiconductor device according to the second embodiment of the present invention. The step-up circuit 200 includes a step-up unit 210 and a voltage conversion circuit unit 220. Booster unit 210 includes n-type transistors QNA _{0 to} QNA _m and capacitors CA _{1 to} CA _m . The transistors QNA _{0 to} QNA _m are connected in series between the supply voltage Vin and the output unit OUT. Capacitors CA _{1 to} CA _m have one electrode connected to a connection point between adjacent transistors among transistors QNA _{0 to} QNA _m . The other electrodes of the capacitors CA _{1 to} CA _m are connected to the voltage conversion circuit unit 220.

The transistors QNA _{0 to} QNA _m may be MOSFETs similar to the transistors QNA _{1 to} QNA _m in the first embodiment. The capacitors CA _{1 to} CA _m may be the same MOS capacitors as the capacitors CA _{1 to} CA _m−1 in the first embodiment.

The voltage conversion circuit unit 220 includes voltage conversion circuits VC1 and VC2. Each of voltage conversion circuits VC1 and VC2 includes a clock input unit CLKIN, a clock output unit CLKOUT, and a mode input unit MODE. The clock signal Φ is input to the clock input section CLKIN of the voltage conversion circuit VC1, and the clock signal Φ bar is input to the clock input section CLKIN of the voltage conversion circuit VC2. The clock output unit CLKOUT of the voltage conversion circuit VC1 is connected to the other electrode of the capacitor CA _2k-1 , and the clock output unit CLKOUT of the voltage conversion circuit VC2 is connected to the other electrode of the capacitor CA _2k . The voltage conversion circuit VC1 or VC2 has a boosting stage (see FIG. 6) inside, and boosts the clock signal Φ or Φbar shown in FIG. 17 and outputs it from the clock output unit CLKOUT.

  The mode signal input to the mode input unit MODE is used to change the number of boosting stages or the capacity of the boosting stage in the voltage conversion circuit VC1 or VC2 based on the magnitude of the supply voltages Vin1 to Vin3 (see FIG. 6). . In the present embodiment, there are three types of mode signals, MODE1 to MODE3. Details of MODE1 to MODE3 will be described with reference to FIGS.

  FIG. 6 is a circuit diagram showing a configuration of the voltage conversion circuit VC1 or VC2 (hereinafter referred to as voltage conversion circuit VC). Voltage conversion circuit VC includes boosting stages BS1 and BS2, p-type transistors QPB1 to QPB3, and switching elements SW1 to SW3. The boosting stages BS1 and BS2 and the transistors QPB1 to QPB3 may have the same configuration as the boosting stages BS1 and BS2 and the transistors QPB1 to QPB3 in the first embodiment, respectively.

  In the present embodiment, the switching elements SW1 to SW3 are provided between the boosting stage BS1 and the boosting stage BS2. The switching element SW1 is connected between the electrode on the supply voltage Vin1 side of the capacitor CD1 and the electrode on the ground side of the capacitor CD2, and is connected in series to the transistor QPB2. The switching element SW2 is connected between electrodes on the ground side of the capacitors CD1 and CD2. The switching element SW3 is connected between the electrodes on the supply voltage Vin1 side of each of the capacitors CD1 and CD2.

  7 to 9 are equivalent circuit diagrams showing the operation of each mode of the voltage conversion circuit VC shown in FIG. Modes 1 to 3 will be described in detail with reference to FIGS.

(Mode 1)
In mode 1, as shown in FIG. 7, switching element SW1 is on, and switching elements SW2 and SW3 are off. Therefore, since both boosting stages BS1 and BS2 boost the clock signal CSIN, mode 1 is an operation mode when the supply voltages Vin1 to Vin3 are relatively low.

  First, when the clock signal CSIN is high, the transistors QND1, QND2, QNE1, and QNE2 are turned on, and the transistors QPB1 to QPB3 are turned off. Thereby, the capacitors CD1 and CD2 are charged between the supply voltages Vin1 and Vin2 and the ground, respectively. For example, assuming that there is no drop in the charging voltage due to the respective threshold values of transistors QND1 and QND2, the voltages of Vin1 and Vin2 are charged between the electrodes of capacitors CD1 and CD2.

  Next, when the clock signal CSIN is low, the transistors QPB1 to QPB3 are turned on, and the transistors QND1, QND2, QNE1, and QNE2 are turned off. Thus, the capacitors CD1 and CD2 are connected in series between the supply voltage Vin3 and the clock output unit CLKOUT via the transistors QPB1 to QPB3. As a result, the clock signal CSOUT boosted from the supply voltages Vin1 to Vin3 is supplied from the clock output unit CLKOUT to any of the capacitors CA1 to CAm shown in FIG. The clock signal CSOUT is boosted to about Vin1 + Vin2 + Vin3. The voltage of the clock signal CSOUT at this time is VCLK3.

(Mode 2)
In mode 2, as shown in FIG. 8, switching element SW2 is on, and switching elements SW1 and SW3 are off. Therefore, since the boosting stage BS1 does not boost the clock signal CSIN, and only the boosting stage BS2 boosts the clock signal CSIN, mode 2 is an operation mode when the supply voltages Vin1 to Vin3 are relatively high.

  First, when the clock signal CSIN is high, the transistors QND2, QNE1, and QNE2 are turned on, and the transistors QPB1 and QPB3 are turned off. As a result, the capacitor CD2 is charged between the supply voltage Vin2 and the ground. The space between the electrodes of the capacitor CD2 is charged to Vin2.

  Next, when the clock signal CSIN is low, the transistors QPB1 and QPB3 are turned on, and the transistors QND2, QNE1 and QNE2 are turned off. Thus, the capacitor CD2 is connected in series between the supply voltage Vin3 and the clock output unit CLKOUT via the transistors QPB1 and QPB3. As a result, the clock signal CSOUT boosted from the supply voltages Vin2 and Vin3 is supplied from the clock output unit CLKOUT to any of the capacitors CA1 to CAm shown in FIG. The clock signal CSOUT is boosted to about Vin2 + Vin3. The voltage of the clock signal CSOUT at this time is VCLK4.

  It is obvious that the degree of boosting of the voltage VCLK4 is smaller than the degree of boosting of the voltage VCLK3. For example, when supply voltages Vin1 to Vin5 are Vin, VCLK3 = 3 * Vin and VCLK4 = 2 * Vin.

  Therefore, the voltage conversion circuit VC in the present embodiment boosts the clock signal relatively large in mode 1 when the supply voltages Vin1 to Vin3 are relatively low (for example, about 1.5 V), and the supply voltages Vin1 to Vin3 are compared. When the voltage is high (for example, about 2.2 V or more), the clock signal is boosted relatively small in mode 2.

(Mode 3)
In mode 3, as shown in FIG. 9, switching elements SW2 and SW3 are on, and switching element SW1 is off. Therefore, capacitors CD1 and CD2 are connected in parallel. Thereby, boosting stages BS1 and BS2 are equivalent to one boosting stage including a capacitor (referred to as CD12) having a large capacity obtained by adding the capacitances of capacitors CD1 and CD2. Mode 3 is an operation mode in which the booster circuit 200 is operated at a power supply voltage and a temperature exceeding the guaranteed operating range, particularly in the burn-in process. In mode 3, it is assumed that supply voltages Vin1 and Vin2 are Vin12.

  First, when the clock signal CSIN is high, the transistors QND1, QND2, QNE1, and QNE2 are turned on, and the transistors QPB1 and QPB3 are turned off. As a result, the capacitor CD12 is charged between the supply voltage Vin12 and the ground. For example, the voltage between the electrodes of the capacitor CD12 is charged to Vin12.

  Next, when the clock signal CSIN is low, the transistors QPB1 and QPB3 are turned on, and the transistors QND1, QND2, QNE1, and QNE2 are turned off. Thus, the capacitor CD2 is connected between the supply voltage Vin3 and the clock output unit CLKOUT via the transistors QPB1 and QPB3. As a result, the clock signal CSOUT boosted from the supply voltages Vin12 and Vin3 is supplied from the clock output unit CLKOUT to any of the capacitors CA1 to CAm shown in FIG. For example, the clock signal CSOUT is boosted to Vin12 + Vin3. The voltage of the clock signal CSOUT at this time is VCLK5. Assuming that Vin3 and Vin12 are Vin, the voltage VCLK5 is 2 * Vin, which is equal to the voltage VCLK4 in the second mode. Therefore, when the supply voltages Vin1 to Vin3 are relatively high (for example, about 2.2 V or more), the clock signal can be boosted relatively small even in mode 3.

  Furthermore, since the capacitance of the capacitor CD12 is larger than that of the capacitor CD2 in mode 2, the output current is larger than that in mode 2. Therefore, in order to operate at a high temperature, it is suitable for a burn-in process in which the load current of the booster circuit increases due to the leakage current. Here, the leakage current refers to junction leakage in the diffusion layer, sub-threshold leakage in the transistor, and the like. Since the boosting capability is high, the current consumption is larger than that in mode 2, but an increase in current consumption is not a problem in the burn-in process.

  According to this embodiment, the booster circuit 200 can have a stable boost capability even when externally supplied voltages have different voltage values. Even in the burn-in process, by using mode 3, it is possible to output a stable output voltage while increasing the output current. In mode 2, even if the supply voltage is large, an increase in power consumption of the voltage conversion circuit VC is suppressed.

  As the insulating films of the capacitors CD1 and CD2, a gate oxide film of a low breakdown voltage transistor is used. Thereby, the area of the whole booster circuit 200 is reduced.

  The capacitance values of the capacitors CD1 and CD2 may be equal. However, the capacitance of the capacitor CD1 may be larger than the capacitance of the capacitor CD2. Thereby, in the mode 1 in which the capacitors CD1 and CD2 are connected in series, the amplitude of the clock signal CSOUT is ideal due to the parasitic capacitances of the transistors QND1, QND2, QNE2, QPB2, QPB3, the capacitors CD1, CD2 and the wiring connecting them. It is possible to prevent the value from becoming smaller.

In the present embodiment, two voltage conversion circuits VC1 and VC2 are provided corresponding to the clock signals Φ and Φbar. However, the voltage conversion circuit VC may be provided corresponding to each of the transistors QNA _{1 to} QNA _m as shown in FIG.

  The supply voltages Vin1 to Vin3 may be all equal to facilitate voltage control of the clock output unit CLKOUT. On the other hand, one of the supply voltages Vin1 to Vin3 may be different and the other may be equal. For example, only the supply voltage Vin3 may be larger than other supply voltages.

  In this embodiment, the transistors QPB1 to QPB3, QND1, QND2, QNE1 and QNE2 are all low withstand voltage transistors. However, as some of the supply voltages are increased, some of these transistors have high withstand voltages. A transistor may be used. For example, when only the supply voltage Vin2 is higher than the other supply voltages, the transistors QPB2, QND2, and QNE2 may be high voltage transistors. In this case, the size and parasitic capacitance of the transistors QPB2, QND2, and QNE2 increase, but the effect of stabilizing the boosting capability is obtained.

  In this embodiment, the number of boosting stages is two stages BS1 to BS2. However, the number of boosting stages may be three or more. However, in actuality, in order to increase the parasitic capacitance and not increase the voltage loss, the boosting stage is preferably four or less.

  Further, in this embodiment, the transistors QPB1 to QPB3 and the transistors QNE1 and QNE2 are driven in synchronization by the clock signal CSIN. However, in order not to increase the voltage loss, the transistors QPB1 to QPB3 may be driven with a delay relative to the transistors QNE1 and QNE2. Further, in the present embodiment, the same CLKIN is input to all of the transistors QND1 and QND2, QNE1 and QNE2, and QPB1 to QPB3. However, a clock signal having the same phase and different amplitude is input to some of the transistors. It may come to be.

  Next, specific examples of the switching elements SW1 to SW3 in the second embodiment are shown.

  FIG. 10 shows an embodiment of the switching element SW1. Terminals TM1 and TM2 are connected to transistor QPB2 and boosting stage BS2, respectively. The terminal TM1 and the terminal TM2 are turned on or off by the mode signal MODE1.

  The switching element SW1 includes a PMOS transistor QP3, an NMOS transistor QN8, a capacitor C3, an NMOS transistor QN6, an NMOS transistor QN7, a NOR gate NOR1, and an inverter INV1. The transistor QP3 may have the same configuration as any of the transistors QPB1 to QPB3. Transistors QN6, QN7, and QN8 may have the same configuration as transistors QND1, QND2, QNE1, or QNE2. The capacitor C3 may have the same configuration as the capacitor CD1 or CD2.

  The transistor QP3 is connected between the terminals TM1 and TM2. The back gate of the transistor QP3 is connected to the terminal TM1. Transistor QN7, capacitor C3 and transistor QN6 are connected in series between supply voltage Vin and ground. The transistor QN8 is connected to the gate of the transistor QP3, and is further connected between the connection point of the transistor QN7 and the capacitor C3 and the ground.

  The NOR gate NOR1 receives a signal obtained by inverting the mode signal MODE1 with the inverter INV1 and the clock signal CSIN, and outputs a negative logical sum of these signals to the gate of the transistor QN8. Clock signal CSIN is input to the gates of transistors QN7 and QN6. Vin may be any of Vin1 to Vin3.

  When the clock signal CSIN is high (Vin), the transistors QN6 and QN7 are turned on and the transistor QN8 is turned off. Therefore, the terminal TM1 becomes the ground potential, and the gate potential of the transistor QP3 becomes Vin, so that the transistor QP3 is turned off. Note that there is no voltage drop due to the threshold value of the transistor QN7. At this time, the other electrode of the capacitor C3 is charged to a voltage of Vin1. The terminal TM2 is grounded via the boosting stage BS2 when the clock signal CSIN is high. Therefore, no forward bias is applied between the drain and N well (channel portion) of the transistor QP3. As a result, the terminal TM1 and the terminal TM2 become non-conductive.

  When the clock signal CSIN is low (ground potential), the transistors QN6 and QN7 are turned off. At this time, when the mode signal MODE1 is high (active state), the transistor QN8 is turned on. As a result, the gate potential of the transistor QP3 becomes the ground potential, so that the transistor QP3 is turned on. That is, the terminals TM1 and TM2 are electrically connected.

  On the other hand, when the mode signal MODE1 is low (inactive state), the transistor QN8 is turned off. As a result, the voltage Vin1 is held between the gate and source of the transistor QP3 by the capacitor C3, so that the transistor QP3 is turned off. That is, the terminal TM1 and the terminal TM2 are not conductive.

  When the mode signal MODE1 is high, the switching element SW1 becomes conductive or non-conductive between the terminals TM1 and TM2 depending on the clock signal CSIN. However, when the mode signal MODE1 is high, the switching element SW1 may maintain the conduction state between the terminals TM1 and TM2 regardless of the state of the clock signal CSIN.

  FIG. 11 shows an embodiment of the switching element SW2. Terminals TM3 and TM4 are connected to electrodes on the ground side of capacitors CD1 and CD2, respectively. The terminals TM3 and TM4 are turned on or off by the mode signals MODE2 and MODE3.

  The switching element SW2 includes a PMOS transistor QP4, an NMOS transistor QN9, a capacitor C4, a NAND gate NAND1, a NOR gate NOR2, and an inverter INV2. The transistor QP4 may have the same configuration as any of the transistors QPB1 to QPB3. Transistor QN9 may have the same configuration as transistors QND1, QND2, QNE1 or QNE2. The capacitor C4 may have the same configuration as the capacitor CD1 or CD2.

  The transistor QP4 is connected between the terminals TM3 and TM4. The back gate of the transistor QP4 is connected to the terminal TM3. The capacitor C4 is connected between the gate of the transistor QP4 and the terminal TM3. The transistor QN9 is connected between the gate of the transistor QP4 and the ground.

  The NOR gate NOR2 receives the mode signals MODE2 and MODE3, and outputs a negative logical sum of these signals. The NAND gate NAND1 receives a signal obtained by inverting the clock signal CSIN by the inverter INV2 and an output signal from the NOR gate NOR2, and outputs a negative logical product of these signals to the gate of the transistor QN9.

  When the mode signal MODE2 or the mode signal MODE3 is high (active state), the transistor QN9 is turned on. Therefore, since the transistor QP4 is also turned on, the terminals TM3 and TM4 are electrically connected.

  When the mode signal MODE2 and the mode signal MODE3 are low (inactive state) and the clock signal CSIN is high (Vin), the transistor QN9 is turned on, so that the gate potential of the transistor QP4 is set to the ground potential (0V). Become. However, since the terminals TM3 and TM4 are grounded through the boosting stages BS1 and BS2, respectively, the transistor QP4 is not turned on. At this time, the potential difference between both electrodes of the capacitor C4 is approximately 0V.

  When the mode signal MODE2 and the mode signal MODE3 are low (inactive state) and the clock signal CSIN is low (0 V), the transistor QN9 is turned off. At this time, since the potential difference 0V is held between the gate and the source of the transistor QP4 by the capacitor C4, the transistor QP4 is turned off. That is, the terminals TM3 and TM4 are non-conductive.

  FIG. 12 shows an embodiment of the switching element SW3. Terminals TM5 and TM6 are connected to electrodes on the supply voltage side of capacitors CD1 and CD2, respectively. The terminal TM5 and the terminal TM6 are turned on or off by the mode signal MODE3.

  The switching element SW3 includes a PMOS transistor QP5, NMOS transistors QN10 and QN11, a capacitor C5, a NOR gate NOR3, and an inverter INV3. Transistor QP5 may have the same configuration as any of transistors QPB1 to QPB3. The transistors QN10 and QN11 may have the same configuration as the transistors QND1, QND2, QNE1 or QNE2. The capacitor C5 may have the same configuration as the capacitor CD1 or CD2.

  The transistor QP5 is connected between the terminals TM5 and TM6. The back gate of the transistor QP5 is connected to the terminal TM5. The capacitor C5 is connected between the gate of the transistor QP5 and the terminal TM5. The transistor QN10 is connected between the gate of the transistor QP5 and the ground. The transistor QN11 is connected between the gate of the transistor QP5 and the supply voltage Vin. The NOR gate NOR3 receives a signal obtained by inverting the clock signal CSIN by the inverter INV3 and the mode signal MODE3, and outputs a negative logical sum of these signals to the gate of the transistor QN11. The mode signal MODE3 is input to the gate of the transistor QN10.

  When the mode signal MODE3 is high (active state), the transistor QN10 is turned on, so that the gate potential of the transistor QP5 becomes the ground potential (0 V). Further, when the clock signal CSIN is high, the terminals TM5 and TM6 are connected to the supply voltage Vin via the boosting stages BS1 and BS2, respectively. When the clock signal CSIN is low, the terminals TM5 and TM6 are boosted to the supply voltage Vin or higher. Therefore, the transistor QP5 is turned on and conducts between the terminals TM5 and TM6.

  Next, when the mode signal MODE3 is low (inactive state), the transistor QN10 is turned off. Further, when the clock signal CSIN is high (Vin), the transistor QN11 is turned on, and the gate potential of the transistor QP5 is Vin. It is assumed that there is no voltage drop due to the threshold value of the transistor QN11. At this time, the terminals TM5 and TM6 are connected to the supply voltage Vin through the boosting stages BS1 and BS2, respectively. Note that Vin1 = Vin2 = Vin. Therefore, the transistor QP5 is turned off. At this time, the potential difference between both electrodes of the capacitor C5 is 0V.

  When the mode signal MODE3 is low (inactive state) and the clock signal CSIN is low (0 V), the transistor QN11 is turned off, but the capacitor C5 causes a potential difference between the gate and the source of the transistor QP5. 0V is held. Therefore, the transistor QP5 is turned off. That is, the terminals TM5 and TM6 are non-conductive.

  The forms of the switching elements SW1 to SW3 shown in FIGS. 10 to 12 are merely examples, and any switch circuit having an equivalent function may be used.

(Third embodiment)
FIG. 13 is a circuit diagram of the voltage conversion circuit VD in the booster circuit according to the third embodiment of the present invention. The boosting unit may be the same as that of the boosting circuit 110 or 210 of the first or second embodiment, and will not be described. Further, the arrangement of the voltage conversion circuit VD in the voltage conversion circuit unit may be the same as that of the voltage conversion circuit unit 120 or 220 in the first or second embodiment, and thus the description thereof is omitted.

  The voltage conversion circuit VD has a configuration in which boosting stages BS30 and BS40 for high breakdown voltage, p-type high breakdown voltage transistors QPB30 to QPB50, and switching elements SW1 to SW3 are added to the voltage conversion circuit VC in the second embodiment. .

  Boosting stage BS30 includes an n-type high voltage transistor QND30, a capacitor CD3 and an n-type high voltage transistor QNE30. The transistor QND30, the capacitor CD3, and the transistor QNE30 are connected in series between the supply voltage Vin3 and the ground. Boosting stage BS40 includes an n-type high voltage transistor QND40, a capacitor CD4 and an n-type high voltage transistor QNE40. The transistor QND40, the capacitor CD4, and the transistor QNE40 are connected in series between the supply voltage Vin4 and the ground.

  The transistor QPB30 is connected between the supply voltage side electrode of the capacitor CD2 and the ground side electrode of the capacitor CD3. The transistor QPB40 and the switching element SW1 are connected in series between the supply voltage side electrode of the capacitor CD3 and the ground side electrode of the capacitor CD4. The transistor QPB50 is connected between the supply voltage side electrode of the capacitor CD4 and the clock output unit CLKOUT.

  The switching element SW2 is connected between the ground-side electrodes of the capacitors CD3 and CD4. Switching element SW3 is connected between the electrodes on the supply voltage side of capacitors CD3 and CD4.

  The voltage conversion circuit VD has four boosting stages, which is larger than the number of boosting stages included in the voltage conversion circuit VC in the second embodiment. Therefore, a high voltage is generated in the subsequent boosting stages BS30 and BS40 in which a high voltage is generated. Therefore, high breakdown voltage transistors are used as the transistors in the boosting stages BS30 and BS40. On the other hand, since only the potential difference between the supply voltage Vin3 or Vin4 and the ground is applied to the capacitors CD3 and CD4, a gate insulating film for low withstand voltage may be used. Thereby, a circuit area can be made comparatively small.

  In the present embodiment, similarly to the second embodiment, when the mode signal MODE1 is high (active state), the switching element SW1 is on and the switching elements SW2 and SW3 are off. When the mode signal MODE2 is high, the switching element SW2 is on and the switching elements SW1 and SW3 are off. When the mode signal MODE3 is high, the switching elements SW2 and SW3 are on and the switching element SW1 is off. Hereinafter, each mode will be described.

(Mode 1)
The switching element SW1 is on and the switching elements SW2 and SW3 are off. At this time, since all of the boosting stages BS1 to BS40 boost the clock signal CSIN, mode 1 is an operation mode when the supply voltages Vin1 to Vin3 are relatively low.

  First, when the clock signal CSIN is high, the capacitors CD1 to CD4 are charged between the supply voltages Vin1 to Vin4 and the ground, respectively. For example, if there is no drop in the charging voltage due to the threshold values of the transistors QND1 to QND40, the voltages of Vin1, Vin2, Vin3, and Vin4 are charged between the electrodes of the capacitors CD1 to CD4.

  Next, when the clock signal CSIN is low, the capacitors CD1 to CD4 are connected in series between the supply voltage Vin5 and the clock output unit CLKOUT via the transistors QPB1 to QPB50. As a result, the clock signal CSOUT boosted from the supply voltages Vin1 to Vin5 is output. The clock signal CSOUT is boosted to about Vin1 + Vin2 + Vin3 + Vin4 + Vin5. The voltage of the clock signal CSOUT at this time is VCLK7. If Vin1 to Vin5 are Vin, the voltage VCLK7 is about 5 * Vin.

(Mode 2)
Switching element SW2 is on, and switching elements SW1 and SW3 are off. Thereby, boosting stages BS1 and BS30 do not operate, and only boosting stages BS2 and BS40 operate. Therefore, mode 2 is an operation mode when supply voltages Vin1 to Vin3 are relatively high.

  First, when the clock signal CSIN is high, the capacitors CD2 and CD40 are charged between the supply voltages Vin2 and Vin4 and the ground, respectively. For example, Vin2 and Vin4 are charged between the electrodes of the capacitors CD2 and CD40, respectively.

  Next, when the clock signal CSIN is low, the capacitors CD2 and CD40 are connected in series between the supply voltage Vin5 and the clock output unit CLKOUT via the transistors QPB1, QPB30, and QPB50. As a result, the clock signal CSOUT boosted from the supply voltages Vin2, Vin4 and Vin5 is output. For example, the clock signal CSOUT is boosted to about Vin2 + Vin4 + Vin5. The voltage of the clock signal CSOUT at this time is VCLK8. For example, if Vin2, Vin4, and Vin5 are Vin, the voltage VCLK8 is about 3 * Vin.

  It is clear that the degree of boosting of the voltage VCLK8 is smaller than the degree of boosting of the voltage VCLK7. Therefore, the voltage conversion circuit VD in the present embodiment boosts the clock signal relatively large in mode 1 when the supply voltages Vin1 to Vin5 are relatively low (for example, about 1.5 V), and the supply voltages Vin1 to Vin5 are compared. When the target voltage is high (for example, about 2.5 V or more), the clock signal is boosted relatively small in mode 2.

(Mode 3)
In mode 3, the switching elements SW2 and SW3 are on and the switching element SW1 is off. Therefore, capacitors CD1 and CD2 are connected in parallel, and capacitors CD30 and CD40 are connected in parallel. Thereby, boosting stages BS1 and BS2 are equivalent to one boosting stage including a capacitor (referred to as CD12) having a large capacity obtained by adding the capacitances of capacitors CD1 and CD2. Similarly, the boosting stages BS3 and BS4 are equivalent to one boosting stage including a capacitor (referred to as CD34) having a large capacity obtained by adding the capacitors CD30 and CD40. Mode 3 is an operation mode in which the booster circuit is operated at a power supply voltage and a temperature exceeding the guaranteed operating range, particularly in the burn-in process. It is assumed that the supply voltages Vin1 and Vin2 are Vin12 and the supply voltages Vin3 and Vin4 are Vin34.

  First, when the clock signal CSIN is high, the capacitors CD12 and CD34 are charged between the supply voltages Vin12 and Vin34 and the ground, respectively. For example, Vin12 and Vin34 are charged between the electrodes of the capacitors CD12 and CD34, respectively.

  Next, when the clock signal CSIN is low, the capacitors CD12 and CD34 are connected in series between the supply voltage Vin5 and the clock output unit CLKOUT via the transistors QPB1, QPB30, and QPB50. As a result, the clock signal CSOUT boosted from the supply voltages Vin12, Vin34 and Vin5 is output. For example, the clock signal CSOUT is boosted to about Vin12 + Vin34 + Vin5. The voltage of the clock signal CSOUT at this time is VCLK9.

  For example, if Vin1 to Vin5, Vin12, and Vin34 are Vin, the voltage VCLK8 and the voltage VCLK9 are both about 3 * Vin. Therefore, when the supply voltages Vin1 to Vin5 are relatively high (for example, about 2.5 V or more), the clock signal can be boosted relatively small even in mode 3.

  Further, since the capacitances of the capacitors CD12 and CD34 are larger than the capacitances of the capacitors CD2 and CD4 in the mode 2, the output current is larger than that in the mode 2. Therefore, in order to operate at a high temperature, it is suitable for a burn-in process in which the load current of the booster circuit increases due to the leakage current. Here, the leakage current refers to junction leakage of the diffusion layer, sub-threshold leakage of the transistor, and the like. Since the boosting capability is high, the current consumption is larger than that in mode 2, but an increase in current consumption is not a problem in the burn-in process.

  Thereby, this embodiment has the same effect as the second embodiment. Further, in the present embodiment, the subsequent boosting stages BS30 and BS40 are configured by high voltage transistors. Therefore, each voltage conversion circuit VD can boost the clock signal CSIN greatly.

  The supply voltages Vin1 to Vin5 may all be equal to facilitate voltage control of the clock output unit CLKOUT. On the other hand, one of the supply voltages Vin1 to Vin5 may be different and the other may be equal.

  In the present embodiment, the number of boosting stages is four stages BS1 to BS4. However, the number of boosting stages may be three or less and may be five or more. However, in actuality, in order to increase the parasitic capacitance and not increase the voltage loss, the boosting stage is preferably four or less.

  Further, in the present embodiment, the transistors QPB1 to QPB50 and the transistors QNE1 to QNE40 are driven in synchronization by the clock signal CSIN. However, in order not to increase the voltage loss, the transistors QPB1 to QPB50 may be driven with a delay with respect to the transistors QNE1 to QNE40. Furthermore, in the present embodiment, the same CLKIN is input to all of the transistors QND1 to QND40, QNE1 to QNE40, and QPB1 to QPB50, but a clock signal having the same phase and different amplitude is input to some of the transistors. It may be like this.

(Fourth embodiment)
FIG. 14 is a circuit diagram of the voltage conversion circuit VE in the booster circuit according to the fourth embodiment of the present invention. The boosting unit may be the same as that of the boosting circuit 110 or 210 of the first or second embodiment, and will not be described. Further, the arrangement of the voltage conversion circuit VE in the voltage conversion circuit unit may be the same as that of the voltage conversion circuit unit 120 or 220 in the first or second embodiment, and thus the description thereof is omitted.

The voltage conversion circuit VE includes boosting stages BS1 and BS2 and switching elements SW4 and SW5. Switching element SW4 is connected between the ground-side electrode of the electrode and the capacitor CD2 of the supply voltage side of the capacitor CD _1. Thereby, switching element SW4 acts in the same manner as switching element SW1 and transistor QPB2 in FIG. Switching element SW5 is connected between the electrodes on the supply voltage side of capacitors CD1 and CD2. Thereby, the switching element SW5 acts in the same manner as the switching element SW3 of FIG.

  The switching element SW4 includes a PMOS transistor QP6, a capacitor C6, NMONS transistors QN12 and QN13, a NOR gate NOR4, and an inverter INV4. The source and drain of the transistor QP6 are respectively connected between the supply voltage side electrode of the capacitor CD1 and the ground side electrode of the capacitor CD2. Transistors QN12 and QN13 are connected in series between supply voltage Vin and ground. The gate of the transistor QP6 is connected to a connection point between the transistors QN12 and QN13, and is further connected to the supply voltage side electrode of the capacitor CD1 through the capacitor C6. The back gate of the transistor QP6 is connected to the source of the transistor QP6 and the supply voltage side electrode of the capacitor CD1.

  The NOR gate NOR4 receives the mode signal MODE1 and the clock signal CSIN via the inverter INV4, and outputs a negative logical sum of these signals to the gate of the transistor QN13. The gate of the transistor QN12 is connected to the clock input section CLKIN.

  Next, the operation of the switching element SW4 will be described. When the mode signal MODE1 is high (active state) and the clock signal CSIN is low, the transistors QN12 and QN13 are turned off and on, respectively. Thus, since the gate of the transistor QP6 is at the ground potential, the transistor QP6 is turned on.

  When the mode signal MODE1 is high (active state) and the clock signal CSIN is high, the transistors QN12 and QN13 are turned on and off, respectively. Therefore, the gate potential of the transistor QP6 is charged to Vin1. It is assumed that there is no voltage drop due to the threshold value of the transistor QN12. At this time, since the source of the transistor QP6 is also charged to Vin1, the transistor QP6 is turned off. Note that there is no voltage drop due to the threshold value of the transistor QND1. Thereby, when the clock signal CSIN is low, the switching element SW1 conducts the boosting stages BS1 and BS2, and when the clock signal CSIN is high, the switching element SW1 conducts the boosting stages BS1 and BS2.

  When the mode signal MODE1 is low (inactive state), the transistor QN13 is always off. The transistor QN12 is turned on when the clock signal CSIN is high. As a result, the gate potential of the transistor QP6 is charged to Vin1. At this time, the source of the transistor QP6 is charged to Vin1 by the transistor QND1. That is, the source and gate potentials of the transistor QP6 are the same. When the clock signal CSIN is low, the source potential of the transistor QP6 becomes high, but the capacitor C6 keeps the gate potential of the transistor QP6 at the same level as the source potential, and the transistor QP6 remains off.

  The switching element SW5 includes a PMOS transistor QP7, a capacitor C7, NMOS transistors QN14 and QN15, an inverter INV5, and a NOR gate NOR5. The source and drain of the transistor QP7 are connected to the supply voltage side electrodes of the capacitors CD1 and CD2, respectively. Transistors QN14 and QN15 are connected in series between supply voltage Vin and ground. The gate of the transistor QP7 is connected to the connection point between the transistors QN14 and QN15, and is further connected to the supply voltage side electrode of the capacitor CD1 via the capacitor C7. The back gate of the transistor QP7 is connected to the source of the transistor QP7 and the supply voltage side electrode of the capacitor CD1.

  The NOR gate NOR5 receives the clock signal CSIN and the mode signal MODE2 via the inverter INV4, and outputs a negative logical sum of these signals to the gate of the transistor QN14. The mode signal MODE2 is input to the gate of the transistor QN15.

  Next, the operation of the switching element SW5 will be described. When the mode signal MODE2 is high (active state), the transistor QN14 is always off and the transistor QN15 is always on. Therefore, the gate potential of the transistor QP7 becomes the ground potential, and the switching element SW5 is always in a conductive state.

  When the mode signal MODE2 is low (inactive state), the transistor QN15 is always off. Transistor QN14 is turned on when clock signal CSIN is high. Therefore, the gate potential of the transistor QP7 is charged to Vin1. However, it is assumed that there is no voltage drop due to the threshold value of the transistor QN14. At this time, since the source of the transistor QP7 is also charged to Vin1 by the transistor QND1, the potential of the source and gate of the transistor QP7 is the same. When the clock signal CSIN is low, the source potential of the transistor QP7 is increased, but the capacitor C7 keeps the gate potential of the transistor QP7 at the same level as the source potential, and the transistor QP7 remains off.

  According to the present embodiment, the amplitude of the clock signal CSOUT is about Vin1 + Vin2 + Vin3 when the boosting stages BS1 and BS2 are connected in series when the mode signal MODE1 is high. When the mode signal MODE2 is high, the boosting stage BS2 does not perform a boosting operation, so the amplitude of the clock signal CSOUT is Vin1 + Vin3.

  As described above, according to the present embodiment, the number of boosting stages in the potential conversion circuit VE can be reduced based on the mode change. Therefore, this embodiment has the same effect as the first embodiment.

The supply voltages Vin1 to Vin3 may be all equal to facilitate voltage control of the clock output unit CLKOUT. On the other hand, one of the supply voltages Vin _{1 to} Vin ₃ may be a different voltage and the other may be equal.

  In the present embodiment, a gate insulating film of a low breakdown voltage transistor can be used for the insulating layer of the capacitor constituting the boosting stages BS1 and BS2. Therefore, the area of these capacitors is small and the circuit area is small.

  In this embodiment, the number of boosting stages is two stages BS1 to BS2. However, the number of boosting stages may be three or more. However, in actuality, in order to increase the parasitic capacitance and not increase the voltage loss, the boosting stage is preferably four or less.

  The capacitance values of the capacitors CD1 and CD2 may be equal. However, the capacitance of the capacitor CD1 may be larger than the capacitance of the capacitor CD2. Thus, in mode 1 in which capacitors CD1 and CD2 are connected in series, the amplitude of clock signal CSOUT connects transistors QND1, QND2, QNE2, QP6, QP7, QN12 to QN15, capacitors CD1, CD2, C6, and C7. It is possible to prevent a decrease from an ideal value due to the parasitic capacitance of the wiring.

1 is a circuit diagram of a booster circuit 100 built in a semiconductor device according to a first embodiment of the present invention. Any one of the voltage conversion circuit _VA 1 to VA _m (hereinafter, referred to as voltage conversion circuits VA) circuit diagram showing the configuration of a. 4 is a timing chart of a clock signal CS _IN , a clock signal CLK1, and a clock signal CLK2 in mode 1. 4 is a timing chart of a clock signal CS _IN , a clock signal CLK1, and a clock signal CLK2 in mode 2. The circuit diagram of the voltage booster circuit 200 incorporated in the semiconductor device according to the second embodiment of the present invention. The circuit diagram which shows the structure of the voltage conversion circuit VC. The equivalent circuit diagram which shows the operation | movement in the mode 1 of the voltage converter circuit VC. The equivalent circuit diagram which shows the operation | movement in mode 2 of the voltage converter circuit VC. The equivalent circuit diagram which shows the operation | movement in the mode 3 of the voltage converter circuit VC. One embodiment of switching element SW1. One embodiment of switching element SW2. One embodiment of switching element SW3. The circuit diagram of voltage conversion circuit VD in the booster circuit according to the third embodiment of the present invention. FIG. 10 is a circuit diagram of a voltage conversion circuit VE in a booster circuit according to a fourth embodiment of the present invention. FIG. 3 is a circuit diagram of a booster circuit 10 built in a conventional semiconductor device. The circuit diagram which shows the structure of the voltage conversion circuit VB. Timing chart of clock signal Φ or Φ bar.

Explanation of symbols

100 step-up circuit 110 boosting unit 120 voltage converting circuit section n-type transistors QNA ₁ ~QNA _m
Capacitors CA _{1 to} CA _m-1
Voltage conversion circuit VA _{1 to} VA _m
MODE mode input section
Φ, Φ bar Clock signals BS1 to BS4 Boosting stages QND1 to QND4, QNE1 to QNE4 n-type transistors QPB1 to QPB5 p-type transistors CD1 to CD4 Capacitors Vin1 to Vin5 Supply voltage

Claims (6)

A plurality of first switching elements connected in series from the output section; and a plurality of first capacitors connected at one end between the adjacent first switching elements, from the other end of the first capacitor A booster circuit unit that inputs a clock signal and outputs a boosted voltage from an output unit; and
One end is connected to the first voltage source via the second switching element, the other end is connected to the reference voltage via the third switching element, and the voltage difference between the first voltage source and the reference voltage And a plurality of boosting stages each having a second capacitor to be charged based on the power supply, and at least between the adjacent boosting stages, and in series between a second voltage source and the other end of the first capacitor. A plurality of fourth switching elements that control the number of the second capacitors connected to the first and second voltage sources based on the voltages of the first and second voltage sources, and to the other ends of the adjacent first capacitors. A voltage conversion circuit unit that outputs a reverse phase clock signal is provided ,
The fourth switching element includes the one end of the second capacitor of the boosting stage on the clock voltage source side among the adjacent boosting stages, and the other of the second capacitor of the boosting stage on the output side. Connect between the ends,
A fifth switching element connected between the one end and the other end of the second capacitor in the two boosting stages, and between the one end of each of the second capacitors in the two boosting stages. It further comprises at least one switching element among a sixth switching element to be connected and a seventh switching element for connecting between the other ends of the second capacitors in the two boosting stages. A featured semiconductor device. Supplying a first clock signal to each gate of the second and third switching elements in a part of the boosting stages and to each gate of the fourth switching element between the part of the boosting stages; A clock supply circuit for supplying a second clock signal to the gates of the second and third switching elements in the other boosting stages, and to the gate of the fourth switching element between the other boosting stages; In addition,
Amplitudes of the first clock signal and the second clock signal are changed based on voltages of the first and second voltage sources, and one of the first clock signal and the second clock signal is changed. The number of the second capacitors connected in series between the second voltage source and the other end of the first capacitor is controlled by stopping one clock operation. 2. The semiconductor device according to 1. By controlling the fifth switching element, the sixth switching element, and the seventh switching element, the second capacitor in a part of the boosting stages can be connected to the second voltage source and the second switching element. 2. The semiconductor device according to claim 1, wherein the semiconductor device is separated from the second capacitor connected in series between the other end of the first capacitor. The second capacitor in the plurality of boosting stages is connected in parallel by controlling the fifth switching element, the sixth switching element, and the seventh switching element. 2. The semiconductor device according to 1. The second capacitor is a MOS capacitor including a gate electrode, a gate insulating film, and a channel region or a well diffusion layer constituting any of the second to fourth switching elements,
2. The semiconductor device according to claim 1, wherein the gate insulating film has a thickness of 10 nm or less. A non-volatile storage device;
The semiconductor device according to claim 1, wherein the booster circuit unit outputs the boosted voltage from the output unit to the nonvolatile memory device.

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