JP3205756B2 - Electronics - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device having a built-in booster circuit composed of a MOS transistor and a capacitor.

[0002]

2. Description of the Related Art FIG. 18 shows a conventional boosting system.
In FIG. 18, a power supply 1801 generates an electromotive voltage Vp. The oscillation circuit 1802 is driven by the electromotive voltage Vp of the power supply 1801, and outputs a clock signal P1. Booster circuit 180
3 boosts the voltage of the power supply 1801 using the clock signal P1, and outputs the boosted voltage Vdd to the boosted voltage output terminal 1804.

FIG. 19 shows a booster circuit 1803 shown in FIG.
FIG. In FIG. 19, 1901 corresponds to FIG.
Reference numeral 1902 denotes an electromotive voltage input terminal for inputting an electromotive voltage Vp of the power supply 1801, and a first clock for inputting a first clock signal P11 which is one of the clock signals P1 output from the oscillation circuit 1802 shown in FIG. Signal input terminal, 1
903, a second clock signal input terminal for inputting a second clock signal P12, which is one of the clock signals P1, 1904, a boosted voltage output terminal for outputting a boosted voltage Vdd, 1905, a boosting unit, and 1914, , A diode.

[0004] The more the number of boosting units 1905 connected in series, the greater the multiple of boosting. Step-up unit 1
At 905, 1910 is an input terminal, and 1911 is
The boosted voltage output terminal 1912 is connected to the first clock signal P
1113, a first clock signal input terminal for inputting
Is a second clock signal input terminal for inputting the second clock signal P12, 1906 and 1907 are diodes, and 1908 and 1909 are capacitors.

A signal obtained by inverting the first clock signal P1 is a second clock signal P2. The circuit operation is already well known and will not be described.

[0006]

The above-mentioned conventional voltage boosting system has a drawback that a booster circuit requires a plurality of diodes, and the diodes cause a loss. As the diode, a Schottky diode is often used to reduce a forward voltage drop. However, even if the Schottky diode is used, voltage loss and power loss due to forward voltage loss are unavoidable, and there is a problem that there is a loss of about 0.2 V per one Schottky diode.

Next, in the above-mentioned conventional boosting system, since there is no means for detecting the voltage of the power supply, the boosting multiple of the boosting circuit cannot be set to an appropriate value according to the voltage of the power supply. That is, the boosted voltage of the boosting system is set to 2
When charging the next battery, etc., even if the voltage of the power supply is high and charging can be performed even if the boosting factor is small, charging is performed through a boosting circuit of a high boosting factor with a large loss, so that charging efficiency is reduced, When driving an IC or the like with the boosted voltage, there is a problem that the voltage of the power supply further increases and the boosted voltage exceeds the upper limit of the drive voltage of the IC or the like.

[0008]

According to the present invention, as a first means, there is provided a booster circuit for charging / discharging a capacitor by using a MOS transistor which is a linear switching element and performing a boost. Since MOS transistors can be integrated on a silicon substrate, they can be made smaller than conventional booster circuits. Further, since a non-linear element such as a diode is not used, a booster circuit with a small boost loss can be obtained, and an efficient boost system can be obtained.

As a second means, a voltage detection circuit is provided,
The voltage of the power supply is detected, a detection signal corresponding to the voltage of the power supply is output, and the booster circuit receives the detection signal and changes the boosting multiple. With this configuration, the boosted voltage can be boosted by a boosting multiple according to the voltage of the power supply, and the boosted voltage can be charged to a secondary battery or the like. Therefore, charging loss is small. Even if the voltage is increased to some extent, a boosting system capable of preventing the boosted voltage from exceeding the upper limit of the drive voltage of an IC or the like can be obtained.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a case where an N-channel MOS transistor and a P-channel MOS transistor are formed by a P-type substrate N-well process will be described. The booster circuit of the booster system of the present invention is an N-channel MOS
A transistor or a P-channel MOS transistor is configured to step up by charging and discharging a capacitor.

The booster circuit of the booster system according to the present invention includes:
Any method may be used as long as it is based on the above configuration. As a first method, a first electrode of a capacitor is connected to a GND terminal, and an input voltage is supplied to a second electrode of the capacitor. Then, by supplying an input voltage to the first electrode, the input voltage generated at the second electrode is reduced by two times.
A plurality of booster circuits for performing double boosting by repeating the act of outputting a double boosted voltage are connected in series, and as a method of performing (2n) times boosting, or as a second method, a plurality of capacitors are charged in parallel. Then, a method of performing (1 + n) times boosting by connecting in series, and further,
As a third method, three methods of performing (1 + n) times boosting by changing the diode of the conventional boosting circuit to a MOS transistor are recommended.

Further, in the booster circuit of the booster system according to the present invention, the MOS transistor constituting the booster circuit is GN
The MOS transistor serving to discharge to the D potential may be an N-channel MOS transistor, but the MOS transistor serving to supply a voltage may be an N-channel MOS transistor or a P-channel MOS transistor according to the supplied voltage.
Higher boosting efficiency can be achieved by properly using transistors, and further, boosting from a lower voltage becomes possible. For example, if the voltage supplied by the MOS transistor is at least a voltage higher than the absolute value of the threshold voltage of the P-channel MOS transistor, the P-channel MOS
If an S transistor is used and the voltage is lower than that, an N-channel MOS transistor may be used.

Further, the oscillation circuit of the boosting system of the present invention has a gate receiving a clock signal from the oscillation circuit.
In order to maximize the capabilities of OS transistors,
In order to obtain the highest voltage, that is, a clock signal having a peak value of the boosted voltage, it is recommended that the power supply be a boosted voltage. Further, when the voltage of the power supply fluctuates, the clock signal is made to fluctuate according to the voltage of the power supply in order to obtain an optimum boosted power according to the voltage of the power supply. That is, it is recommended that the oscillation circuit change the frequency of the output clock signal in accordance with the voltage of the power supply.

On the other hand, the boosting system of the present invention includes a voltage detecting circuit for detecting the voltage of the power supply, and changes the boosting multiple of the boosting circuit in accordance with a detection signal corresponding to the voltage of the power supply output from the voltage detecting circuit. It is recommended to configure. It is recommended that the voltage detection circuit of the present invention be operated intermittently in order to reduce current consumption. In order to operate the voltage detection circuit intermittently, a new intermittent pulse generation circuit and a signal storage circuit are provided. The circuit is operated intermittently with the intermittent pulse generated by the intermittent pulse generation circuit, and a detection signal output at the time of operation of the voltage detection circuit is input to the booster circuit via the signal storage circuit, and the voltage detection circuit It is recommended that the detection signal during operation be continuously output to the booster circuit until the next operation.

Further, in order to further reduce the voltage operation, each circuit of the boosting system of the present invention has a P-type gate and an N-channel MOS transistor if the MOS transistor constituting each circuit of the boosting system is a P-channel type MOS transistor. Type M
The OS transistor is configured with an N-type gate, that is, the absolute value of the threshold voltage of each MOS transistor is reduced by adopting a configuration in which the off-leak current can be suppressed even if the absolute value of the threshold voltage is lowered. Is recommended.

The power supply of the boosting system is not limited as long as it generates an electromotive voltage. The power supply is effective for boosting a thermoelectric conversion element, a solar cell, and a capacitor charged with a voltage, which fluctuate the electromotive voltage. In particular, as described above, the present booster system has the characteristics of being able to operate at a lower voltage and achieve higher boosting efficiency, so that it can be used for boosting a thermoelectric conversion element that cannot obtain an electromotive voltage for its volume. In addition, the volume of the thermoelectric conversion element can be reduced, and a small portable device such as a wristwatch using the thermoelectric conversion element as a power source can be realized.

[0017]

An embodiment of the present invention will be described with reference to the drawings.
Unless otherwise noted, the power supply has a structure in which the low potential side is a GND terminal, the high potential side is a Vdd terminal, and the circuit is a CMOS transistor manufactured by a P substrate N well process and the P substrate is a GND terminal. Is described. Therefore, the substrate of all N-channel MOS transistors is common and is connected to the GND terminal. “High” means a signal at the voltage level of the boosted voltage Vdd, and “Low” means a signal at the GND level.

FIG. 1 is a block diagram of a thermoelectric conversion element boosting system according to an embodiment of the present invention. Thermoelectric conversion element 101, oscillation circuit 103, and intermittent pulse generation circuit 10
4, a voltage detection circuit 105, a signal storage circuit 106, a booster circuit 107, a diode 102, and a smoothing capacitor 10.
8, 109. The thermoelectric conversion element 101
An element that generates power by the principle of the Seebeck effect.
Although not shown, an impurity is introduced into a Bi-Te-based material to form a P-type semiconductor and an N-type semiconductor, and a plurality of elements connected to each other are connected in series. Denotes a GND terminal, and includes an oscillation circuit 103, an intermittent pulse generation circuit 104, a voltage detection circuit 105, and a signal storage circuit 10.
6 and the GND terminal of the booster circuit 107 to take out the electromotive voltage Vp from the other electrode. The internal resistance is about 2 kΩ, and the electromotive voltage is about 0.4 V at a temperature difference of 1 ° C.

The oscillation circuit 103 has a configuration in which a power supply terminal is connected to Vdd, and the oscillation frequency varies in accordance with Vp. The power supply terminal of the intermittent pulse generation circuit 104 is Vdd
To the clock signal P output from the oscillation circuit 101.
1 is a circuit for generating an intermittent pulse signal P2 based on the signal No. 1.

The voltage detection circuit 105 has a power supply terminal of Vdd.
And outputs a detection signal P3 corresponding to the Vp.
In this configuration, the intermittent operation is performed by the intermittent pulse signal P <b> 2 from No. 4. The signal storage circuit 106 has a power supply terminal connected to Vdd, and stores a detection signal P3 when the voltage detection circuit 105 is in operation.
This is a circuit which stores the voltage until the next operation of the voltage detection circuit 105 and outputs the stored detection signal P3 as a storage signal P4.

The booster circuit 107 has a power supply terminal connected to Vdd, and boosts Vp to a boosted voltage Vd higher than Vp.
and a circuit for boosting the voltage of each MOS by the clock signal P1.
By turning on / off the transistor and charging / discharging the capacitor, the boosted voltage Vdd is generated, and the boosting multiple is switched according to the storage signal P4.

The diode 102 uses the electromotive voltage Vp of the thermoelectric conversion element 101 as power for boosting at the initial stage when the boosted voltage is not stored in Vdd, and
Is high enough, and if the boost action is not necessary,
dd, and the thermoelectric conversion element 101
And Vdd are connected so that the direction from the thermoelectric conversion element 101 to Vdd is forward.

Further, the output of the thermoelectric conversion element 101 and V
The dd is provided with smoothing capacitors 108 and 109 having one side connected to the GND terminal. With the above configuration, the boosting multiple of the boosting circuit 107 is
1 can be switched in accordance with the electromotive voltage of 1 so that Vp can be efficiently boosted to a boosted voltage Vdd,
Step-up voltage Vdd generated when Vp becomes too high
Overvoltage can be prevented.

Further, by intermittently operating the voltage detection circuit 105, the power consumption of the voltage detection circuit 105 can be reduced. That is, the power required for boosting can be suppressed, so that boosting efficiency is improved. Note that the diode 102 is a Schottky diode with a small forward voltage drop, a diode-connected (0.1 V) MOS transistor with a low threshold voltage, or
Diode-connected threshold voltage is low (0.1
V) Gate and source or drain are P type or N
A type MOS transistor is recommended.

In this embodiment, the thermoelectric conversion element has been described as an example. However, in order to increase the electromotive voltage of an element that generates electric power by using other external energy, or to use a storage element such as a capacitor or a secondary battery. It is needless to say that the present invention can be applied to boost the voltage. FIG. 2 is a circuit diagram of the booster circuit 107 shown in FIG. First booster circuit 201 Second booster circuit 202, third booster circuit, fourth booster circuit, two-input NAND circuits 209, 211, 213, inverter circuits 210, 211, 214, P-channel MOS transistors 223, 224, and a smoothing capacitor 205, 20
6,207 and a diode 208.

First, the connection state of each component will be described.
An electromotive force input terminal 215 for inputting the electromotive force Vp of the thermoelectric conversion element is connected to the input terminal of the first booster circuit 201 and the positive electrode of the diode 208. The output terminal of the first booster circuit is connected to the other electrode of the smoothing capacitor 205 having one electrode connected to the GND terminal, and to the input terminal of the second booster circuit 202.

The output terminal of the second booster circuit 202 includes the other electrode of the smoothing capacitor 206 having one electrode connected to the GND terminal, the negative electrode of the diode 208, and the drain terminal of the P-channel MOS transistor 223. And the input terminal of the third booster circuit 203. The output terminal of the third booster circuit 203 connects one electrode to G
The other electrode of the smoothing capacitor 207 connected to the ND terminal, the drain terminal of the P-channel MOS transistor 224, and the input terminal of the fourth booster circuit 204 are connected.

The output terminal of the fourth booster circuit 204 is connected to the respective sources of the P-channel MOS transistors 223 and 224, the N well, and the boosted voltage output terminal 221 for outputting the boosted voltage Vdd. A clock signal input terminal 216 for inputting a clock signal P1 from the oscillation circuit is connected to one input terminal of each of the two-input NAND circuits 209, 211, and 213.

A first detection signal input terminal 217 for inputting a first storage signal P41 storing a first detection signal, which is one of the detection signals from the voltage detection circuit, is a two-input NAND.
The clock signal input terminal of the circuit 209 is connected to the other input terminal. A second storage signal P storing a second detection signal which is one of the detection signals from the voltage detection circuit
The second detection signal input terminal 218 for inputting 42 is connected to the input terminal of the two-input NAND circuit 211 to which the clock signal input terminal is not connected, and to the gate terminal of the P-channel MOS transistor 223.

A third detection signal input terminal 219 for inputting a third storage signal P43 storing a third detection signal, which is one of the detection signals from the voltage detection circuit, is a two-input NAND.
An input terminal to which the clock signal input terminal of the circuit 213 is not connected;
Connected to the gate terminal. The output terminal of the two-input NAND circuit 209 is connected to the input terminal of the inverter circuit 210 and the first terminal.
The booster circuit 201 and the second booster circuit 202 are connected to respective second clock signal input terminals.

The output terminal of the inverter circuit 210 is connected to the first
The booster circuit 201 and the second booster circuit 202 are respectively connected to the first clock signal input terminals. Inverter circuit 212
Is connected to the first clock signal input terminal of the third booster circuit, and the output terminal of the inverter circuit 214 is connected to the first clock signal input terminal of the fourth booster circuit.

The two-input NAND circuits 209 and 21
1, 213 and inverter circuits 210, 212, 214
Are connected to a power supply terminal Vd to which the boosted voltage Vdd is input.
Each of the GND terminals is connected to the GND terminal 220 connected to the low voltage side electrode of the thermoelectric conversion element. Next, the operation will be described.

The first storage signal P41 and the second storage signal P
When both 42 and the third storage signal P43 are “low”, no clock signal is input to all the boosting circuits, so that all the boosting circuits do not operate and no boosting action is performed.
The P-channel MOS transistors 223 and 224
Is on, but the leakage of current from the boosted voltage output terminal 221 via both transistors is only the charging current of the capacitance component hanging on the drains of both transistors.

When the first storage signal P41 is "high" and the second
When the storage signal P42 and the third storage signal P43 are “low”, the clock signals of the first booster circuit 201 and the second booster circuit 202 are input, so that the first booster circuit 201 and the second booster circuit
Since only the booster circuit 202 operates and the P-channel MOS transistor 223 turns on, the electromotive voltage V
First, p is boosted about twice by the first boosting circuit 201, further doubled by the second boosting circuit 202, and supplied to Vdd via the P-channel MOS transistor 223. That is, since the boosting multiple is about four times, Vdd becomes about four times Vp. Although the P-channel MOS transistor 224 is also turned on, the leakage of the current from the boosted voltage output terminal 221 via the transistor is only the charging current of the capacitance component hanging on the drain of the transistor.

The first storage signal P41 and the second storage signal P
When the signal 42 is “high” and the third storage signal P43 is “low”, the clock signals of the first booster circuit 201 and the second booster circuit 202 are input.
The booster circuit 202 and the third booster circuit 203 operate, the P-channel MOS transistor 223 turns off, and the P-channel MOS transistor 224 turns on.
Is boosted approximately twice by the first booster circuit 201,
The voltage is boosted approximately twice by the booster circuit 202, further doubled by the third booster circuit 203, and supplied to the output terminal 221 via the P-channel MOS transistor 224. That is, since the boosting multiple is about eight times, Vdd becomes about eight times Vp.

The first storage signal P41 and the second storage signal P
When both the reference signal 42 and the third storage signal P43 are "high", the clock signal is input to all the boosting circuits, so that the P-channel MOS transistors 223 and 224 are turned off, and all the boosting circuits operate. First, the first booster circuit 2
01 is boosted about twice, the second booster circuit 202 boosts about twice, the third booster circuit 203 boosts about twice,
Further, the voltage is boosted by about twice by the fourth booster circuit 204 and output from the boosted voltage output terminal 221. That is, since the boosting multiple is about 16 times, Vdd becomes about 16 times Vp.

Although the diode 208 will be described in detail later, the first booster circuit 201 and the second booster circuit 201 have a feature that the boosting ability is small when the voltage Vdd is low. The first step-up circuit 201 and the second step-up circuit 201
The third booster circuit 203 and the fourth booster circuit
This is provided to improve the voltage by boosting the voltage by the boosting circuit 204.

In other words, with the above-described configuration, as described above, a booster circuit capable of varying the booster multiple in accordance with the output signals P41, P42, P43 of the signal storage circuit storing the detection signal of the voltage detection circuit is realized. it can. FIG. 3 is a circuit diagram of the first booster circuit 201 shown in FIG. 2 in the present invention. First, the connection will be described. The input terminal 302 to which the electromotive voltage Vp of the thermoelectric conversion element is input is connected to the drain of the N-channel MOS transistor 306 and the source of the N-channel MOS transistor 307, and
Clock signal input terminal 304 is an N-channel MOS
The transistor 307 is connected to the gates of the N-channel MOS transistor 308 and the second clock signal input terminal 305 is connected to the N-channel MOS transistor 306
The source of the N-channel MOS transistor 306 is connected to the drain of the N-channel MOS transistor 308 and the second electrode of the capacitor 310, and the first electrode of the capacitor 310 is connected to the gate of the channel MOS transistor 309. , An output terminal 303 connected to the drain of the N-channel MOS transistor 307 and the source of the N-channel MOS transistor 309 and outputting a boosted voltage is connected to the drain of the N-channel MOS transistor 309, and a GND input terminal 311 Is
In this configuration, the source is connected to the source of the N-channel MOS transistor 308.

Next, the operation will be described. First, first
When the first clock signal input from the clock signal input terminal 304 is “high”, the second clock signal input from the second clock signal input terminal 305 is “low”, and the N-channel type MOS transistors 307 and 308 are turned on, and N-channel type MOS transistor 30
6 and 309 are turned off.
Is supplied with the voltage supplied to the input terminal 302 via the N-channel MOS transistor 307, the voltage rises to a certain voltage Va, and the second electrode of the capacitor is connected to the N-channel MOS transistor 308. Is low through the supply of the GND voltage via.

Next, the first clock signal input terminal 304
When the first clock signal input from is "low",
Second clock signal input from second clock signal input terminal 305
Becomes “high” and the N-channel MO
Since the S transistors 307 and 308 are turned off and the N-channel MOS transistors 306 and 309 are turned on, the second electrode of the capacitor 310 is connected to the N-channel MOS transistor.
Since the voltage supplied to the input terminal 302 is supplied through the transistor 306, the voltage increases to a certain voltage Vb. Therefore, the first electrode of the capacitor rises to a voltage obtained by adding the Va and the Vb, and the voltage is increased through the N-channel MOS transistor 309.
Since the voltage is supplied to the output terminal 303, the voltage of the output terminal 303 rises to a certain voltage Vc.

Here, the values of Va, Vb, and Vc are related to the maximum voltage that can be supplied when the N-channel MOS transistor is turned on, and the voltage supplied by the N-channel MOS transistor is the maximum voltage. Any small voltage can be supplied as long as it is less than or equal to the value,
If the voltage is higher than the maximum voltage value,
It can supply only up to the maximum voltage value.

That is, Va indicates that the voltage supplied from the input terminal 302 is equal to the N-channel MOS transistor 307.
Is less than or equal to the maximum voltage value, the voltage supplied from the input terminal 302 is the same as the voltage supplied from the input terminal 302.
7 is higher than the maximum voltage value, the N-channel MOS
The maximum voltage value of the transistor 307 is obtained, and Vb is the voltage supplied from the input terminal 302 when the N-channel type MO
When the voltage is equal to or less than the maximum voltage value of the S transistor 306, the voltage is the same as the voltage supplied from the input terminal 302.
When the voltage supplied from the input terminal 302 is an N-channel type M
When the voltage is higher than the maximum voltage value of the OS transistor 306, it becomes the maximum voltage value of the N-channel MOS transistor 306, and Vc is a value obtained by adding Va and Vb generated at the first electrode of the capacitor 310 to N-channel. When the voltage is equal to or lower than the maximum voltage value of the type MOS transistor 309, the voltage becomes the same as the value obtained by adding Va and Vb.
When the voltage is higher than the maximum voltage value of the channel type MOS transistor 309, the N-channel type MOS transistor 309
Of the maximum voltage value.

The maximum voltage value of each N-channel MOS transistor is defined as the maximum voltage value of each N-channel MOS transistor when each N-channel MOS transistor is on.
This is a value obtained by subtracting the threshold voltage of each N-channel MOS transistor from the “high” voltage of each clock signal input to the gate of the S transistor, that is, Vdd.

That is, in the first booster circuit, the voltage to be boosted is low, and each N-channel MOS transistor
When only a voltage equal to or less than the maximum voltage value of the channel type MOS transistor needs to be supplied, the voltage can be efficiently boosted, and the voltage can be boosted from any low voltage. However, when the voltage to be boosted is high, or When the Vdd is low and one of the N-channel MOS transistors of the booster circuit must supply a voltage higher than the maximum voltage value of the N-channel MOS transistor, the boosting is performed. If the efficiency becomes poor and the boosted voltage becomes higher, or
When d is further reduced, the voltage may be reduced.

Therefore, each of the N-channel MOS transistors of the first booster circuit is constituted by an N-type gate so that the leakage current can be suppressed even if the threshold voltage is lowered. Is set as low as possible (approximately 0.2 V) so that even when Vdd is low, the voltage can be boosted from a higher voltage. The first booster circuit includes:
In this configuration, the turned-off MOS transistor is turned on at the same time as the turned-on MOS transistor of the first booster circuit is turned off. With a configuration in which the first booster circuit is turned on, the through current can be eliminated and the boosting efficiency of the first booster circuit can be improved.

FIG. 4 is a circuit diagram of the second booster circuit 202 shown in FIG. 2 according to the present invention. The configuration is almost the same as that of the first booster circuit shown in FIG. 3. The difference from the first booster circuit of FIG. 3 is that the N-channel MOS transistor 309 of the first booster circuit of FIG. In the second booster circuit, the drain is connected to the first electrode of the capacitor 410, the source and the N-well are connected to the output terminal 403,
The only difference is that the gate is replaced by a P-channel MOS transistor 409 whose gate is connected to the first clock signal input terminal 404.

In the operation, the timing at which each MOS is turned on and off is the same as that of the first booster circuit shown in FIG.
Is different from the first booster circuit in that when the P-channel MOS transistor 409 is turned on, the capacitor 410
Of the P-channel MO
If the boosted voltage is lower than the lowest voltage that the S transistor 409 can supply,
When the forward direction of the N-type N-well from the P-type drain of No. 9 is lower than 0.6 V, the voltage cannot be supplied to the output terminal 403 at all. When the boosted voltage is 0.6 V or more, the boosted voltage is Can be supplied to the output terminal 403 only up to a voltage obtained by subtracting 0.6 V from the output terminal 403. However, when the boosted voltage is equal to or higher than the minimum voltage, the boosted voltage can be supplied to the output terminal 403 no matter how high the voltage is. .

The minimum voltage that the P-channel MOS transistor 409 can supply is the minimum voltage that the P-channel MOS transistor can supply from the drain to the source or from the source to the drain of the transistor via the channel. Since the threshold voltage of the transistor is subtracted from the voltage of the gate of the transistor, the minimum voltage of the P-channel MOS transistor 409 in FIG.
Since the value obtained by subtracting the threshold value from the "low" voltage of the gate of the transistor 409, that is, the negative value of the threshold value is subtracted from the GND voltage, this is the absolute value of the threshold voltage.

That is, in the second booster circuit, the voltage to be boosted is the N-channel MOS transistor 40.
The boosted voltage generated at the first electrode of the capacitor 410 below the maximum voltage of the P-channel MOS
When the voltage of the transistor 409 is equal to or higher than the minimum voltage, the voltage can be efficiently boosted. However, when the voltage to be boosted is high or when the Vdd is low, the voltage to be boosted is an N-channel MOS transistor. 407,
When the voltage exceeds one of the maximum voltages of one of the N-channel MOS transistors 406, the boosting efficiency is degraded or the voltage is lowered.
When the voltage is lower than the minimum voltage of the transistor 409, no voltage is output to the output terminal 403.

Therefore, each MOS transistor of the second booster circuit is formed of an N-type gate in the case of an N-channel MOS transistor, and is formed of a P-type gate in the case of a P-channel MOS transistor. Therefore, even if the absolute value of the threshold voltage is lowered, the configuration is such that the leakage current can be suppressed, and the absolute value of the threshold voltage is made as low as possible (0.2 V
By doing so, even when Vdd is low, the voltage can be boosted from a higher voltage, and further, the voltage can be boosted from a lower voltage.

The second booster circuit has a configuration in which the turned-off MOS transistor is turned on at the same time as the turned-on MOS transistor of the second boosted circuit is turned off. By turning on the MOS transistor which has been turned off and then on, the through current can be eliminated and the boosting efficiency of the second booster circuit can be improved.

FIG. 5 is a circuit diagram of the third booster circuit 203 and the fourth booster circuit 204 of FIG. The configuration is similar to that of the N-channel MOS transistor 30 of the second booster circuit shown in FIG.
6 and 307, the source of the P-channel MOS transistor and the N-well are connected to the input terminal 5 as shown in FIG.
02, the drain is connected to the second electrode of the capacitor 510, and the gate is connected to the first clock signal input terminal 5
N-channel MOS transistor 506 connected to terminal 04
And a drain connected to the input terminal 502, a source and an N-well connected to the first electrode of the capacitor 510, and a gate replaced by a P-channel MOS transistor 507 connected to the second clock signal input terminal 505. It is.

The operation of each MOS is the same as the ON / OFF timing of the MOS transistor in the second booster circuit shown in FIG. 4. However, when the P-channel MOS transistor 507 is turned ON, the first terminal of the capacitor 510 is supplied from the input terminal 502. When a voltage is supplied to the electrodes of the P-channel type,
When the voltage is lower than the minimum voltage that can be supplied by the OS transistor 507 and the forward direction of the N well from the P-type drain of the transistor is lower than 0.6 V, no power can be supplied at all. Although only a value obtained by subtracting 0.6 V from the voltage of the terminal 502 can be supplied, when the voltage is equal to or higher than the minimum voltage, the voltage of the input terminal 502 can be supplied as it is, and when the P-channel MOS transistor 506 is turned on, the input terminal 502 When a voltage is supplied to the second electrode of the capacitor 510 from the
When the voltage at the input terminal 502 is equal to or higher than the minimum voltage of the transistor, the voltage at the input terminal 502 can be supplied as it is.

That is, the third and fourth booster circuits
Although the voltage cannot be boosted from a voltage lower than the minimum voltage that can be supplied by each P-channel MOS transistor, the voltage can be boosted from a higher voltage as long as the voltage is higher than the minimum voltage. Therefore, in the case of each of the P-channel MOS transistors of the third booster circuit, the P-type gate is configured so that the leakage current can be suppressed even if the absolute value of the threshold voltage is reduced, and the threshold voltage is reduced. By lowering the absolute value of the value voltage as much as possible (about 0.2 V), a lower voltage (0.
2V).

The third and fourth booster circuits have a configuration in which the turned-off MOS transistor is turned on at the same time as the turned-on MOS transistor is turned off. Is turned off and then the MOS transistor that has been turned off is turned on, thereby eliminating through current and improving the boosting efficiency of the booster circuit.

The booster circuit 107 of this embodiment shown in FIG.
The first to fourth booster circuits having the above-described features are
The second booster boosts the voltage boosted by the first booster, the third booster boosts the voltage boosted by the second booster, and the fourth booster boosts the voltage boosted by the third booster. The second booster circuit boosts the voltage to a voltage that can be boosted by the third booster circuit, and the first booster circuit boosts the voltage to a voltage that can be boosted by the second booster circuit.
If d is 0.3 V or more and Vp inputted from the electromotive force input terminal 215 is 0.05 V or more, the voltage can be boosted.

In the present embodiment, as shown in FIG. 1, the voltage V
By raising p, the electromotive voltage V of the thermoelectric conversion element 101 is increased.
p can be efficiently boosted, and the low electromotive force Vp
(0.05 V), a thermoelectric conversion element step-up system capable of stepping up from 0.05 V was realized. The booster circuit of this embodiment shown in FIG. 2 is designed to boost the electromotive voltage of the thermoelectric conversion element having the above-described performance to a voltage that can drive an IC operating at about 1.5 V, such as a watch IC. However, when the voltage to be boosted is different, such as when boosting the electromotive voltage of a thermoelectric conversion element having a different performance or another power generation element, or when boosting the voltage of a storage element such as a capacitor or a secondary battery, or If the required boosted voltage value is different, such as when the required voltage of the driving IC is different, the first booster circuit or the third booster circuit may be further connected in series, or the first booster circuit may be provided in plurality. Needless to say, a design change may be made such as a configuration in which a plurality of third booster circuits are connected in series after serial connection, or a configuration in which only a plurality of third booster circuits are connected in series.

FIG. 6 is a circuit diagram of booster circuit 608 in the case where booster circuit 107 shown in FIG. 1 has a configuration different from that of the booster circuit shown in FIG. It is composed of a total of 15 booster circuits from the first booster circuit 601 to the fifteenth booster circuit 606, two-input NAND circuits 617, 619, 621, inverter circuits 616, 618, 620, and a P-channel MOS transistor 622. are doing.

First, the connection state of each component will be described.
An electromotive force input terminal 609 for inputting Vp, which is an electromotive voltage of the thermoelectric conversion element, is connected to the first input terminal of the first booster circuit 601 and the first input terminal of the first booster circuit 601 to the fifteenth booster circuit 606. 2 input terminal. An output terminal of each booster circuit other than the fifteenth booster circuit 606 is connected to a first input terminal of a booster circuit located next, and an output terminal of the fifteenth booster circuit is a P-channel MOS transistor 62.
2, the source of the P-channel MOS transistor 622 and the N well are connected to a boosted voltage output terminal 610 that outputs a boosted voltage Vdd.

The clock signal input terminal 611 for inputting the clock signal P1 from the oscillation circuit is connected to one input terminal of each of the two-input NAND circuits 617, 619 and 621. A first detection signal input terminal 612 for inputting a first storage signal P41 storing a first detection signal, which is one of the detection signals from the voltage detection circuit, is a two-input NAND 621.
Clock signal input terminal 611 is connected to the other input terminal.

A second detection signal input terminal 613 for inputting a second storage signal P42 storing a second detection signal, which is one of the detection signals from the voltage detection circuit, is a two-input NAND.
619 is connected to the other input terminal. A third detection signal input terminal 614 that inputs a third storage signal P43 that stores a third detection signal, which is one of the detection signals from the voltage detection circuit,
The clock signal input terminal 611 of the input NAND 617 is connected to the other input terminal.

The output terminal of the two-input NAND circuit 617 is
The input terminal of the inverter circuit 616 and the first booster circuit 60
The first to eighth booster circuits 602 are connected to the second clock signal input terminals of the respective booster circuits. An output terminal of the inverter circuit 616 is connected between the first booster circuit 601 and the eighth booster circuit 602.
Connected to the first clock signal input terminal of each booster circuit.

The output terminal of the two-input NAND circuit 619 is
The input terminal of the inverter circuit 618 and the ninth booster circuit 60
The third to twelfth booster circuits 604 are connected to the second clock signal input terminals of the respective booster circuits. The output terminal of the inverter circuit 618 is connected between the ninth booster circuit 603 and the twelfth booster circuit 6.
04 is connected to the first clock signal input terminal of each booster circuit.

The output terminal of the two-input NAND circuit 621 is
An input terminal of the inverter circuit 620 and the thirteenth booster circuit 6
The second clock signal input terminal of each booster circuit of the booster circuits 605 to 606 is connected to the gate of the P-channel MOS transistor 622. Inverter circuit 620
Are connected to the first clock signal input terminals of the respective booster circuits of the thirteenth booster circuit 605 to the fifteenth booster circuit 606.

Note that two-input NAND circuits 617 and 61
9,621 and inverter circuits 616,618,620
Are connected to a power supply terminal Vd to which the boosted voltage Vdd is input.
Connected to the d input terminal 608, each GND terminal is connected to the GND potential input terminal 615 connected to the low voltage side electrode of the thermoelectric conversion element. Next, the operation will be described.

The first storage signal P41 and the second storage signal P
When both 42 and the third storage signal P43 are “low”, the clock signal is not input to all the boosting circuits, so that
All booster circuits do not operate and do not perform boosting action. First
Is high and the second storage signal P42
When the third storage signal P43 is “low”, the clock signal is input only to the booster circuits from the thirteenth booster circuit 605 to the fifteenth booster circuit 606, so that the thirteenth booster circuit 605 to the fifteenth booster circuit 606 , The booster circuit operates. That is, since three booster circuits operate and boost the voltage by the voltage of Vp by one booster circuit, the boosted voltage of 4Vp obtained by adding 3Vp to the electromotive voltage Vp of the thermoelectric conversion element is:
It is output from the output terminal of the fifteenth booster circuit 606.

The first storage signal P41 and the second storage signal P
When 42 is “high” and the third storage signal P43 is “low”, the clock signal is input only to the booster circuits from the ninth booster circuit 603 to the fifteenth booster circuit 606. To the fifteenth booster circuit 606 operate. That is, since seven booster circuits operate, a boosted voltage of 4 Vp obtained by adding 7 Vp to the electromotive voltage Vp of the thermoelectric conversion element is output from the output terminal of the fifteenth booster circuit 606.

The first storage signal P41 and the second storage signal P
When both 42 and the third storage signal P43 are "high", the clock signal is input to all the boosting circuits, so that all the boosting circuits operate. That is, since 15 booster circuits operate, 16 Vp obtained by adding 15 Vp to the electromotive voltage Vp of the thermoelectric conversion element is output from the output terminal of the fifteenth booster circuit 606.

The boosted voltage is output from the output terminal of the fifteenth booster circuit 606. The boosted voltage is not always output, but is output only when the clock signal P1 is "high" and the clock signal is "high". At the time of "low", the electromotive voltage Vp of the thermoelectric conversion element is output as it is from the output terminal.
That is, the output terminal is directly used as the boosted voltage output terminal 610.
When the clock signal P1 is “low”, the boosted voltage that has been output with great effort becomes the electromotive voltage Vp of the thermoelectric conversion element.
Will fall to Therefore, a P-channel MOS transistor 622 is provided, and the transistor is connected to the clock signal P.
1 is high when it is high, and the clock signal P1 is low.
In the case of turning off, the above problem was cleared.

As described above, by configuring the booster circuit as shown in FIG. 6, as described above, according to the storage signal output from the signal storage circuit storing the detection signal of the voltage detection circuit, A booster circuit that can change the booster multiple
It can be realized with a configuration different from the booster circuit shown in FIG. FIG. 7 is a circuit diagram of the first to third booster circuits shown in FIG. 6 in the present invention.

First, the connection state will be described. First
Input terminal 703 is connected to the drain of N-channel MOS transistor 708, and second input terminal 702 is connected to
The first clock signal input terminal 705 is connected to the source of the N-channel MOS transistor 709, the first clock signal input terminal 705 is connected to the gate of the N-channel MOS transistor 708, and the second clock signal input terminal 706 is connected to the N-channel MOS transistor 709. , 710, the source of the N-channel MOS transistor 708 is connected to the drain of the N-channel MOS transistor 710 and the second electrode of the capacitor 711, and the first electrode of the capacitor 711 is connected to the N-channel MOS transistor 710. Type MOS transistor 709
And an output terminal 704 for outputting a boosted voltage, and a GND input terminal 707 is connected to a source of an N-channel MOS transistor 710.

Next, the operation will be described. First, first
When the first clock signal input from the clock signal input terminal 705 is “low”, the second clock signal input from the second clock signal input terminal 706 is “high”.
And N channel type MOS transistors 709 and 71
0 turns on and the N-channel MOS transistor 708 turns off, so that the first electrode of the capacitor 711 is
The electromotive voltage Vp of the thermoelectric conversion element supplied to the second input terminal 702 via the channel type MOS transistor 709
Is supplied, the voltage rises to a certain voltage Va, and the second electrode of the capacitor goes "low" because the voltage of GND is supplied through the N-channel MOS transistor 708.

Next, the first clock signal input terminal 705
When the first clock signal input from is "high",
The second clock signal input from the second clock signal input terminal 706
Becomes "low" and the N-channel MO
Since the S transistors 709 and 710 are turned off and the N-channel MOS transistor 708 is turned on, the second electrode of the capacitor 711 is supplied to the first input terminal 703 via the N-channel MOS transistor 708. Is supplied, the voltage rises to a certain voltage Vb.
Therefore, the first electrode of the capacitor is
And the voltage Vb, and the voltage is output from the output terminal 704.

Here, the values of Va and Vb are related to the maximum voltage that can be supplied when the N-channel MOS transistor is turned on.
If the supplied voltage is less than the maximum voltage value, any small voltage can be supplied. However, if the supplied voltage is higher than the maximum voltage value, no matter how large the voltage can be, only the maximum voltage value can be supplied.

That is, when the voltage supplied from the second input terminal 702 is equal to or less than the maximum voltage value of the N-channel MOS transistor 709, Va is the second input terminal 7.
02, but the voltage supplied from the second input terminal 702 is equal to the voltage supplied from the N-channel type MO.
When the voltage is higher than the maximum voltage value of the S transistor 709,
When the voltage supplied from the first input terminal 703 is equal to or less than the maximum voltage value of the N-channel MOS transistor 708, Vb is the first input terminal. The same voltage as the voltage supplied from the first input terminal 703
Is higher than the maximum voltage value of the N-channel MOS transistor 708, the voltage becomes the maximum voltage value of the N-channel MOS transistor 708.

The above-mentioned maximum voltage value of each N-channel MOS transistor refers to each N-channel MOS transistor when each N-channel MOS transistor is on.
This is a value obtained by subtracting the threshold voltage of each N-channel MOS transistor from the “high” voltage of each clock signal input to the gate of the S transistor, that is, Vdd.

That is, the booster circuit shown in FIG.
When the voltage to be boosted is low and each N-channel MOS transistor needs to supply only a voltage equal to or less than the maximum voltage value of each N-channel MOS transistor, the voltage can be efficiently boosted, and the voltage can be boosted from any low voltage. However, when the voltage to be boosted is high or when Vdd is low, each N-channel type M
If any one of the OS transistors must supply a voltage higher than the maximum voltage value of the N-channel MOS transistor, the boosting efficiency becomes poor,
Further, when the voltage to be boosted becomes higher or when the above-mentioned Vdd becomes further lower, the voltage may be lowered.

Therefore, each of the N-channel MOS transistors of the booster circuit shown in FIG. 7 is constituted by an N-type gate, so that the leakage current can be suppressed even if the threshold voltage is lowered. Threshold voltage as low as possible (0.2
(Approximately V), the voltage can be increased from a higher voltage even when Vdd is low. Note that the above-described booster circuit shown in FIG.
MOS that was turned off at the same time that the transistor was turned off
The transistor is turned on.
MOS that was turned off after turning off the OS transistor
With the structure in which the transistor is turned on, a through current can be eliminated and the boosting efficiency of the booster circuit can be improved.

FIG. 8 shows the fourth embodiment of the present invention shown in FIG.
It is a circuit diagram of the 1st to 15th booster circuits. The configuration is almost the same as that of the booster circuit of FIG. 7, and the difference is that the N-channel MOS transistor 708 of the booster circuit of FIG.
Connect the source and the N-well to the first input terminal 803,
Connecting the drain to the second electrode of the capacitor 811;
The only difference is that the gate is replaced by a P-channel MOS transistor 808 whose gate is connected to the second clock signal input terminal 806.

The operation is almost the same as that of the booster circuit shown in FIG.
8 turns on, and the voltage input to the first input terminal 803 becomes P
The relationship between the voltage of the first input terminal 803 and the voltage Vb when the voltage Vb is supplied to the second electrode of the capacitor 811 via the channel type MOS transistor 808,
When the voltage of the first input terminal 803 is lower than the lowest voltage that can be supplied by the channel type MOS transistor 506, the voltage cannot be supplied at all. However, when the voltage of the first input terminal 803 is equal to or higher than the lowest voltage of the transistor, The difference is that the voltage of the first input terminal 803 can be supplied as it is.

The minimum voltage that the P-channel MOS transistor 808 can supply is the minimum voltage that the P-channel MOS transistor can supply from the drain to the source or from the source to the drain of the transistor via the channel. Since the threshold voltage of the transistor is subtracted from the voltage of the gate of the transistor, the minimum voltage of the P-channel MOS transistor 808 is calculated from the “low” voltage of the gate of the transistor 808. Since the negative threshold value is subtracted from the value obtained by subtracting the threshold value, that is, the GND voltage, the absolute value of the threshold voltage is obtained.

That is, the booster circuit shown in FIG.
When the voltage input to the second input terminal 802 is equal to or less than the maximum voltage of the N-channel MOS transistor 809,
Is input to the input terminal 803 of the P-channel type MO.
When the voltage of the S transistor 808 is equal to or higher than the minimum voltage, the voltage can be efficiently boosted. However, when the voltage of the second input terminal 802 is equal to or higher than the maximum voltage of the N-channel MOS transistor 809, the boosting efficiency deteriorates. If the voltage of the first input terminal 803 is lower than the minimum voltage of the P-channel MOS transistor 808, the voltage cannot be boosted at all.

Therefore, in the present invention, each MOS transistor of the booster circuit shown in FIG.
In the case of an S transistor, an N-type gate is used, and in the case of a P-channel MOS transistor, a P-type gate is used. Thus, even if the absolute value of the threshold voltage is lowered, the leak current can be suppressed. By making the absolute value of the threshold voltage as low as possible (approximately 0.2 V), the voltage can be boosted from a higher voltage even when Vdd is low, and the voltage can be boosted from a lower voltage.

The booster circuit shown in FIG. 8 has a configuration in which the turned on MOS transistor is turned off and the turned off MOS transistor is turned on at the same time as the turned on MOS transistor. Is turned off and then the MOS transistor that has been turned off is turned on, thereby eliminating through current and improving the boosting efficiency of the booster circuit.

The booster circuit 607 of this embodiment shown in FIG.
The first to third booster circuits having the above-described features are arranged in the preceding stage, and the fourth to fifteenth booster circuits having the above-described features are arranged in the subsequent stage. The fourth to fifteenth boost circuits perform boosting from a low voltage, which is weak, and the fourth to fifteenth boost circuits perform first to third boosting.
By boosting the voltage from a high voltage that the booster circuit is not good at, it is possible to boost the voltage if Vdd is 0.3 V or more and the electromotive voltage Vp of the thermoelectric conversion element is 0.05 V or more. Was completed.

In the present embodiment, as shown in FIG. 1, the boosting circuit 607 shown in FIG. 6 boosts the electromotive voltage Vp of the thermoelectric conversion element 101 to increase the electromotive voltage Vp of the thermoelectric conversion element 101. A thermoelectric conversion element boosting system that can efficiently boost the voltage and that can boost the voltage even from the low electromotive force Vp (0.05 V) is realized. The booster circuit of the present embodiment shown in FIG. 6 is designed to boost the electromotive voltage of the thermoelectric conversion element having the above-mentioned performance to a voltage that can drive an IC operating at about 1.5 V, such as a watch IC. However, when the voltage to be boosted is different, such as when boosting the electromotive voltage of a thermoelectric conversion element having a different performance or another power generation element, or when boosting the voltage of a storage element such as a capacitor or a secondary battery, or In the case where the required boosted voltage value is different, for example, when the required voltage of the driving IC is different, the number of booster circuits shown in FIG. 7 arranged at the preceding stage or the booster circuit shown in FIG. Needless to say, design changes such as increasing or decreasing the number may be performed.

FIG. 9 is a circuit diagram of the booster circuit 907 in the case where the booster circuit 107 shown in FIG. 1 has a different configuration from the configuration of the booster circuit shown in FIG. 2 or FIG. First, the connection state will be described. An electromotive force input terminal 909 for inputting Vp which is an electromotive voltage of the thermoelectric conversion element is connected to a first booster circuit 901.
And an N-channel MOS transistor 915
And the drain of the N-channel MOS transistor 917.

The output terminal of each booster circuit other than the eighth booster circuit 906 is connected to the input terminal of the next booster circuit,
The output terminal of the eighth booster circuit 906 is a boosted voltage output terminal 9
Connect to 10. The clock signal input terminal 911 for inputting the clock signal P1 from the oscillation circuit is a two-input NAND
One input terminal of each of the circuits 927, 929, 931, the input terminal of the inverter circuit 936, and the gates of the N-channel MOS transistors 916, 917 are connected.

A first detection signal input terminal 912 for inputting a first storage signal P41 storing a first detection signal, which is one of the detection signals from the voltage detection circuit, is a two-input NAND.
927, an input terminal to which the clock signal input terminal 911 is not connected, and an N-channel MOS transistor 91.
9,920 gates. A second detection signal input terminal 91 for inputting a second storage signal P42 storing a second detection signal which is one of the detection signals from the voltage detection circuit.
3 is a clock signal input terminal 9 of the two-input NAND 929
11 and the N-channel type M
The gates of the OS transistors 921 and 922 and the gate of the P-channel MOS transistor 925 are connected.

A third detection signal input terminal 914 for inputting a third storage signal P43 storing a third detection signal, which is one of the detection signals from the voltage detection circuit, is a two-input NAND.
931 which is not connected to the clock signal input terminal 911 and the N-channel MOS transistor 92
3, 924 and the gate of a P-channel MOS transistor 926.

The output terminal of the two-input NAND circuit 927 is
The input terminal of the inverter circuit 928 and the first booster circuit 90
1 and the second clock signal input terminal of the second booster circuit 902. An output terminal of the inverter circuit 928 is connected to first clock signal input terminals of the first booster circuit 901 and the second booster circuit 902.

The output terminal of the two-input NAND circuit 629 is
The input terminal of the inverter circuit 930 and the third booster circuit 90
3 and the second clock signal input terminal of the fourth booster circuit 904. An output terminal of the inverter circuit 930 is connected to first clock signal input terminals of the third booster circuit 903 and the fourth booster circuit 904.

The output terminal of the two-input NAND circuit 931 is
The input terminal of the inverter circuit 932 and the fifth booster circuit 90
The fifth to eighth booster circuits 906 are connected to the second clock signal input terminals of the respective booster circuits. The output terminals of the inverter circuit 932 are connected to the fifth booster circuit 905 to the eighth booster circuit 906
To the first clock signal input terminal.

The output terminal of the inverter circuit 936 is connected to the gates of N-channel MOS transistors 915 and 918. The source of the N-channel MOS transistor 915 is connected to N-channel MOS transistors 916 and 91
9, 921, 923, and the source of the N-channel MOS transistor 917 is connected to the N-channel MOS transistor 917.
Connected to the drains of OS transistors 918, 920, 922, and 924, an N-channel MOS transistor 91
6,918 sources are connected to the GND terminal.

The source of the N-channel MOS transistor 919 is connected to the third clock signal input terminals of the first booster circuit 901 and the second booster circuit 902, and the N-channel MOS transistor
The source of the OS transistor 920 is connected to the fourth clock signal input terminal of the first booster circuit. N-channel type M
The source of the OS transistor 921 is connected to the third booster circuit 90
3 and the third clock signal input terminal of the fourth booster circuit 904, and the source of the N-channel MOS transistor 922 is connected to the fourth clock signal input terminal of the third booster circuit 903 and the second booster circuit 902. I do.

The source of the N-channel MOS transistor 923 is connected to the third clock signal input terminal of each booster circuit from the fifth booster circuit 905 to the eighth booster circuit, and the source of the N-channel MOS transistor 924 is The fourth clock signal input terminals of the respective booster circuits from the fourth booster circuit 904 to the eighth booster circuit 906 are connected.

P channel type MOS transistor 925,
926 and the N-well are connected to a boosted voltage output terminal 910
Connect to The two-input NAND circuits 927 and 92
9,931 and inverter circuits 928,930,93
2,936 are connected to a Vdd input terminal 908 to which the boosted voltage Vdd is inputted, and each GND terminal is connected to a low voltage side electrode of the thermoelectric conversion element.
Connect to the potential input terminal 935.

Connecting to the GND terminal means connecting to the GND potential input terminal 935 connected to the lower potential electrode of the thermoelectric conversion element. Next, the operation will be described. The first storage signal P41 and the second storage signal P
When all the signals 42 and the third storage signal P43 are “low”, no clock signal is input to each clock signal input terminal of all the boosting circuits, so that all the boosting circuits do not operate.
No boost action is performed. Although the P-channel MOS transistors 925 and 926 are on, the leakage of current from the boosted voltage output terminal 910 via both transistors is only the charging current of the capacitance component hanging on the drains of both transistors. .

When the first storage signal P41 is "high" and the second
When the storage signal P42 and the third storage signal P43 are "low", a clock signal is input to each clock signal input terminal of the first booster circuit 901 and a clock signal other than the fourth clock signal input terminal of the second booster circuit 902 The clock signal is input to the clock signal input terminal of the first booster circuit 901,
Since the voltage is boosted by Vp and boosted by Vp in the second booster circuit 902 and the P-channel MOS transistor 925 is turned on, the boosted voltage output terminal 910 via the P-channel MOS transistor 925 is connected to the boosted voltage output terminal 910 by 4Vp obtained by adding 3 Vp to Vp. Are supplied. That is, the boosted voltage is 4 Vp
Becomes Note that a P-channel MOS transistor 926
However, the leakage of the current from the boosted voltage output terminal 910 via the transistor is only the charging current of the capacitance component hanging on the drains of the two transistors.

The first storage signal P41 and the second storage signal P
When the signal 42 is “high” and the third storage signal P43 is “low”, the first booster circuit 901, the second booster circuit 902, and the third
A clock signal is input to each clock signal input terminal of each booster circuit of the booster circuit 903, and the fourth
Since the clock signal is input to the clock signal input terminals other than the clock signal input terminal of FIG.
Since each of the first to third booster circuits 903 boosts the voltage by 2 Vp, and the fourth booster circuit 904 boosts the voltage by Vp, the P-channel MOS transistor 925 turns off and the P-channel MOS transistor 262 turns on. A voltage of 8 Vp obtained by adding 7 Vp to Vp is supplied to a boosted voltage output terminal 910 via a P-channel MOS transistor 926. That is, the boost voltage Vdd becomes 8 Vp.

The first storage signal P41 and the second storage signal P
When all the clock signals 42 and the third storage signal P43 are “high”, the clock signal is input to all the clock input terminals of all the boosting circuits.
Since the voltage is increased by Vp in the eighth booster circuit, a voltage of 16 Vp obtained by adding 15 Vp to Vp is supplied to the boosted voltage output terminal 910. That is, the boost voltage V
dd becomes 16 Vp.

Although the booster of each booster circuit is described as 2 Vp or Vp, this value is obtained because Vp is an N-channel MOS transistor 915, 917, 919, 9
20, 921, 922, 923, 924 or less, that is, the case where the peak value of the clock signal input to the third or fourth clock signal input terminal of each booster circuit is Vp. . When Vp is higher than the maximum voltage value, the peak value of the clock signal input to the third or fourth clock signal input terminal of each booster circuit becomes the maximum voltage value, and the boosted voltage of each booster circuit is It is twice the maximum voltage value or the maximum voltage value. That is, the boosted voltage decreases.

Therefore, in the booster circuit shown in FIG. 9 of this embodiment, the N-channel MOS transistor 91 of the booster circuit is used.
5,917,919,920,921,922,92
No. 3,924, the gate is formed of an N type so that the leak current can be suppressed even when the threshold voltage is lowered, and the threshold voltage is reduced as low as possible (about 0.2 V), so that the Vp is increased to some extent. However, the boost amount of each booster circuit is set to 2Vp or V
p.

As described above, the booster circuit is configured as shown in FIG. 9, and as described above, according to the storage signal output from the signal storage circuit storing the detection signal of the voltage detection circuit, A booster circuit that can change the booster multiple
It can be realized with a configuration different from the booster circuit shown in FIG. 2 or FIG. FIG. 10 shows the first embodiment of the present invention shown in FIG.
FIG. 4 is a circuit diagram of a second booster circuit.

First, the connection state will be described. The input terminal 1002 is connected to the N-channel MOS transistor 10
08, the gate of the N-channel MOS transistor is connected to the first clock signal input terminal 1004
In addition, the source of the transistor is a capacitor 1010
First electrode and an N-channel MOS transistor 10
09 and the second of the capacitor 101
Is connected to the third clock signal input terminal 1006, the gate of the N-channel MOS transistor 1009 is connected to the second clock signal input terminal 1005, and the source of the transistor is connected to the first electrode of the capacitor 1011. Connect to the output terminal 1003 and connect the capacitor 1011
Is connected to a fourth clock signal input terminal 1007
Connect to

Next, the operation will be described. Note that the higher voltage of the third or fourth clock signal is Vh, and the lower voltage is “low”. First, a case where a clock signal is input to the fourth clock signal input terminal 1007 will be described. The clock signal of the first clock signal input terminal 1004 is set to “high”,
5, the clock signal of the third clock signal input terminal 106 is set to "low", the clock signal of the fourth clock signal input terminal 1007 is set to Vh, and the N-channel MOS transistor 1008 is turned on. By turning off the channel MOS transistor 1009, lowering the first electrode of the capacitor 1010 by Vh from the previous state, and raising the first electrode of the capacitor 1011 by Vh from the previous state, The electric charge is supplied to the first electrode of the capacitor 1010 via the N-channel MOS transistor 1008, and at the same time, the output terminal 1 is connected to the first electrode of the capacitor 1011.
003, the first state in which the boosted voltage is output, and the clock signal of the first clock signal input terminal 1004 is set to “low”.
The clock signal of the second clock signal input terminal 1005 is “high”, the clock signal of the third clock signal input terminal 106 is Vh, the fourth clock signal input terminal 1007
, The N-channel MOS transistor 1008 is turned off, the N-channel MOS transistor 1009 is turned on, and the first
Is increased by Vh from the previous state, and the first electrode of the capacitor 1011 is decreased by Vh from the previous state, so that the first electrode of the capacitor 1010 is switched from the first electrode of the capacitor 1010 via the N-channel MOS transistor 1009 to The second state in which charge is supplied to the first electrode of the capacitor 1011 is alternately repeated, and charges are sequentially supplied from the input terminal 1002 to the output terminal 1003, so that a boosted voltage is output from the output terminal 1003.

The boosted voltage output from the output terminal 1003 is charged from the drain to the source when each N-channel MOS transistor is turned on until the voltage difference between the drain and the source of each N-channel MOS transistor disappears. Can be supplied, the boosted voltage of the first electrode of the capacitor 1010 becomes a value obtained by adding Vh to the voltage of the input terminal 1002, and the boosted voltage of the first electrode of the capacitor 1011 becomes the boosted voltage of the capacitor 1010.
h is a value obtained by adding 2Vh to the voltage of the input terminal 1002. However, even when one of the N-channel MOS transistors is turned on, the voltage of the drain of the transistor is changed when the transistor is turned on. If the voltage of the source of the transistor reaches the maximum voltage value of the transistor even though it is higher than the voltage of the source, the value becomes lower than otherwise.
In some cases, the value may be equal to or lower than the voltage of the input terminal 1002, that is, the value may be a stepped-down value.

That is, the above-described booster circuit 1001 operates when the voltage to be boosted is low or when the voltage Vd
If d is high and the maximum voltage value of each N-channel MOS transistor is high, and if each N-channel MOS transistor needs to supply only a voltage equal to or less than the maximum voltage value of the transistor, the voltage is efficiently boosted. It has the characteristic that it can be boosted from any low voltage, but when the boosted voltage is high, or when Vdd is low and the maximum voltage value of each N-channel MOS transistor is low as described above, If one of the N-channel MOS transistors has to supply a voltage higher than the maximum voltage value of the N-channel MOS transistor, the boosting efficiency becomes poor or the boosted voltage becomes higher. If Vdd is further reduced, the voltage may be reduced.

Therefore, each of the N-channel MOS transistors of the booster circuit shown in FIG. 10 is constituted by an N-type gate, so that the leakage current can be suppressed even if the threshold voltage is lowered. Set the threshold voltage as low as possible (0.
(Approximately 2 V) so that the voltage can be boosted from a higher voltage even when Vdd is low. Next, a case where a clock signal is not input to the fourth clock signal input terminal 1007 will be described.

The fourth clock signal input terminal 10 described above
The only difference from the case where a clock signal is input to 06 is that the capacitor 1011 is a smoothing capacitor and does not contribute to boosting. That is, the boosted voltage output to the output terminal 1003 is reduced by the Vh, and thus has a value obtained by adding the voltage of the input terminal 1002 to the Vh.

FIG. 11 shows the third embodiment of the present invention shown in FIG.
FIG. 9 is a circuit diagram of the first to seventh booster circuits. The configuration is almost the same as the booster circuit shown in FIG.
N-channel MOS transistor 1008 of the booster circuit of FIG.
Is connected to the input terminal 110 as shown in FIG.
2. Replace the source and the N-well with a P-channel MOS transistor 1108 having a first electrode connected to the first electrode of the capacitor 1110 and a gate connected to the second clock signal input terminal;
As shown in FIG. 11, the N-channel MOS transistor 1009 of the booster circuit shown in FIG. 10 has a drain connected to the first electrode of the capacitor 1110, a source and an N-well connected to the first electrode of the capacitor 1111, and a gate connected to the first electrode. P-channel MOS connected to clock signal input terminal 1104
The only difference is that the transistor 1109 is replaced.

In the operation, the timing when each MOS transistor is turned on and off and the timing when the level of the clock signal input to the second electrode of each capacitor is Vh and "low" are determined by the booster circuit 1001 shown in FIG. The difference is in the voltage condition at which the voltage can be efficiently boosted. That is, in the booster circuit shown in FIG. 10, since each MOS transistor is formed of an N-channel MOS transistor, when the voltage supplied by each N-channel MOS transistor is equal to or less than the maximum voltage value of the transistor,
Although boosting can be performed efficiently, the boosting circuit shown in FIG.
Since the OS transistor is formed of a P-channel MOS transistor, if the voltage supplied by each P-channel MOS transistor is equal to or higher than the minimum voltage of the transistor, the voltage can be efficiently boosted.

In other words, the booster circuit shown in FIG. 11 described above uses a P-channel MOS
When the transistor supplies a voltage equal to or higher than the minimum voltage value of the transistor, the voltage can be efficiently boosted, and
It has the characteristic of being able to boost the voltage from any high voltage. However, if the voltage to be boosted is low and either of the N-channel MOS transistors supplies a voltage less than the minimum voltage value of the transistor, the boosting efficiency is increased. Drops,
In some cases, there is a feature that no voltage is output from the output terminal.

Therefore, each of the P-channel MOS transistors of the booster circuit shown in FIG. 11 is constituted by a P-type gate, so that the leakage current can be suppressed even if the absolute value of the threshold voltage is lowered. By setting the absolute value of the threshold voltage as low as possible (about 0.2 V), the voltage can be boosted from a lower voltage. FIG. 12 is a circuit diagram of the eighth booster circuit shown in FIG. 9 in the present invention. The configuration is
It is almost the same as the booster circuit 1101 shown in FIG.
The only difference is that the booster circuit 1101 shown in FIG. 11 has no capacitor 1111. Therefore, nothing is connected to the fourth clock signal input terminal 1207 as shown in FIG.

The operation is almost the same as that of the booster circuit 1101 shown in FIG. 11 except that the capacitor 1 shown in FIG.
Since there is no 111, the boosted voltage output from the output terminal 1203 corresponds to Vh by the output terminal 1 of the booster circuit 1101 in FIG.
The point is that the voltage is lower than the boosted voltage output to 103.
In the booster circuit 907 of this embodiment shown in FIG. 9, the first booster circuit and the second booster circuit in the preceding stage are configured by the booster circuit shown in FIG. 10 as described above, and the third to seventh booster circuits in the subsequent stage are used. 11, the eighth booster circuit at the last stage is configured by the booster circuit shown in FIG. 12, and the first booster circuit and the second booster circuit form the second booster circuit. The booster circuit boosts the voltage from a low voltage that the third to eighth booster circuits are not good at.
To the eighth booster circuit, the first booster circuit and the second booster circuit perform boosting from a high voltage that they are not good at.
If dd is 0.3 V or more and the electromotive voltage Vp of the thermoelectric conversion element is 0.05 V or more, it is possible to have a feature that the voltage can be boosted.

In this embodiment, as shown in FIG. 1, the boosting circuit 907 shown in FIG. 9 boosts the electromotive voltage Vp of the thermoelectric conversion element 101 to increase the electromotive voltage Vp of the thermoelectric conversion element 101. A thermoelectric conversion element boosting system that can efficiently boost the voltage and that can boost the voltage even from the low electromotive force Vp (0.05 V) is realized. The booster circuit of the present embodiment shown in FIG. 9 is designed to boost the electromotive voltage of the thermoelectric conversion element having the above-mentioned performance to a voltage that can drive an IC operating at about 1.5 V, such as a watch IC. However, when the voltage to be boosted is different, such as when boosting the electromotive voltage of a thermoelectric conversion element having a different performance or another power generation element, or when boosting the voltage of a storage element such as a capacitor or a secondary battery, or In the case where the required boosted voltage value is different, such as when the required voltage of the driving IC is different, FIG.
The number of booster circuits indicated by, or FIG.
Needless to say, a design change such as increasing or decreasing the number of booster circuits indicated by 1 may be performed.

Further, by combining the features of the configurations of the respective boosting circuits shown in FIGS. 2, 6, and 10 described above, a boosting circuit exhibiting the intended performance can be realized. Needless to say. FIG. 13 shows a circuit diagram of the oscillation circuit 103 shown in FIG. 1 in this embodiment. First, the connection state will be described.

An electromotive voltage input terminal 1301 for inputting the electromotive voltage Vp of the thermoelectric conversion element is connected to a depletion type (normally on type) N-channel MOS transistor 13.
V6 to which the boosted voltage Vdd is connected.
The dd input terminal 1304 is connected to the drain of the N-channel MOS transistor 1306, the sources of the P-channel MOS transistors 1318 and 1319, and the N well.

Depletion type N-channel type M
The source of the OS transistor 1306 is a P-channel type
The source and the N well of the OS transistors 1310, 1312, and 1314 are connected to the source and the N well of the P-channel MOS transistor 1316 of the inverter circuit 1308. The drain of the P-channel MOS transistor 1310 is connected to the N-channel MOS transistor 1311
And a first electrode of a capacitor 1322;
Connected to the gates of P-channel MOS transistor 1312 and N-channel MOS transistor 1313.

P-channel MOS transistor 1312
Is an N-channel MOS transistor 131
3, the first electrode of the capacitor 1323, and the gates of the P-channel MOS transistor 1314 and the N-channel MOS transistor 1315. The drain of the P-channel MOS transistor 1314 is connected to the drain of the N-channel MOS transistor 1315,
The gate of the channel type MOS transistor 1311 and P
The gates of the channel MOS transistor 1316 and the N channel MOS transistor 1317 are connected to the gate of the N channel MOS transistor 1321.

P-channel MOS transistor 1316
Is an N-channel MOS transistor 131
7 and an N-channel MOS transistor 13
20 gate. The drain of P-channel MOS transistor 1318 is connected to the gate of P-channel MOS transistor 1319 and the drain of N-channel MOS transistor 1320.

P-channel MOS transistor 1319
Is a P-channel MOS transistor 131
8 and an N-channel MOS transistor 132
1 and a clock signal output terminal 1302 for outputting the clock signal P1. N-channel type MO
S transistors 1311, 1313, 1315, 131
7, 1320, 1321 and the capacitor 13
The second electrodes 22 and 1323 are connected to the GND terminal.

Note that reference numeral 1307 enclosed by a dotted line denotes a ring oscillator circuit, 1308 denotes an inverter circuit, and 1309 denotes a level shift circuit. In addition, the above-mentioned GND
To connect to a terminal means to connect to a GND potential input terminal 1305 that is connected to a lower potential side electrode of the thermoelectric conversion element.

Next, the operation of each section will be described. Depletion type N-channel MOS transistor 130
6 regulates the voltage of Vdd input from the Vdd input terminal 1304. The regulated voltage of the transistor is a value obtained by adding the voltage of the gate of the transistor, that is, the electromotive voltage Vp of the thermoelectric conversion element, to the absolute value of the threshold voltage of the transistor. That is, the regulated voltage of the transistor increases when the electromotive voltage Vp of the thermoelectric conversion element increases, and decreases when the Vp decreases.

Ring oscillator circuit 1307 generates a clock signal. The frequency of the clock signal increases when the power supply voltage of the ring oscillator circuit 1307, that is, the regulated voltage increases, and decreases when the regulated voltage decreases. Therefore, when the electromotive voltage Vp of the thermoelectric conversion element increases, the frequency of the clock signal increases, and when the Vp decreases, the frequency of the clock signal decreases.

The inverter circuit 1308 receives the clock signal and outputs a clock signal obtained by inverting the phase of the clock signal. The level shift circuit 1309 is
A clock signal from the ring oscillator circuit 1307;
Input a clock signal from the inverter circuit 1308,
A clock signal obtained by converting the peak value of the clock signal from the inverter circuit 1308 into a boosted voltage Vdd is output to a clock signal output terminal 1302.

That is, by adopting the above-described configuration shown in FIG. 13, it is possible to realize an oscillation circuit in which the frequency of the output clock signal can be varied according to the electromotive voltage Vp of the thermoelectric conversion element. Further, the oscillation circuit of the present embodiment shown in FIG.
For each MOS transistor other than the depletion type N-channel MOS transistor 1306, a P-channel MOS transistor, a P-type gate, N In the case of a channel type MOS transistor, the absolute value of the threshold voltage of each MOS transistor is made as low as possible (approximately 0.2 V) by using an N-type gate, and the boosted voltage Vdd or the electromotive voltage of the thermoelectric conversion element is reduced. It has a feature that a clock signal can be output even at a low Vp voltage (about 0.3 V).

FIG. 14 is a circuit diagram of the intermittent pulse generation circuit 104 shown in FIG. First, the connection state will be described. The clock signal input terminal 1401 for inputting the clock signal P1 from the oscillation circuit is connected to the inverter circuits 1405, 140
7, the output terminal of the inverter circuit 1405 is connected to the first electrode of the capacitor 1408 whose second electrode is connected to the GND terminal and to the input terminal of the inverter circuit 1406. The terminal is connected to the first input terminal of the two-input NAND circuit 1409, and the output terminal of the inverter circuit 1407 is connected to the two-input N
The output terminal of the two-input NAND circuit 1409 is connected to the second input terminal of the AND circuit 1409, and is connected to the inverter circuit 1
The output terminal of the inverter circuit 1410 is connected to an intermittent pulse output terminal 1402 that outputs an intermittent pulse P2.

It should be noted that each inverter circuit and a two-input NAND
In the circuit, a power supply terminal of the circuit is connected to a Vdd input terminal 1403 to which the boosted voltage Vdd is input.
The terminal is connected to the GN connected to the low voltage side electrode of the thermoelectric conversion element.
Connect to D potential input terminal 1404. Next, the operation will be described. The clock signal P1 input from the clock signal input terminal 1401 is input to a first input terminal of a two-input NAND circuit 1409 via an inverter circuit 1405 and an inverter circuit 1406. This two-input NAND circuit 1
The phase of the clock signal input to the first input terminal 409 is delayed from that of the clock signal P1 by the time for charging and discharging the capacitor 1408.

On the other hand, through the inverter circuit 1407, 2
The clock signal input to the second input terminal of the input NAND circuit 1409 has a phase inverted from that of the clock signal P1. The two-input NAND circuit 1409 includes
Since the above-described clock signal is input to the input terminal of the circuit, the output terminal of the NAND circuit is connected to the capacitor 1408 from the time when the second input terminal of the NAND circuit changes from “low” to “high”. , The first input terminal of the two-input NAND circuit goes high.
A clock signal that becomes “low” is output only during a period from when the signal changes to “low”, that is, only when the capacitor 1408 is charged.

The inverter circuit 1401 inverts the phase of the clock signal output from the two-input NAND circuit 1409, and outputs the inverted signal to the intermittent pulse signal output terminal 1402. From the intermittent pulse signal output terminal 1402, the clock signal output from the inverter circuit 1410 is output as an intermittent pulse signal P2. Needless to say, the "high" period of the intermittent pulse signal P2 can be changed by changing the driving capability of the inverter circuit 1405 or the capacitance value of the capacitor 1408.

Further, the intermittent pulse generation circuit 104 of the present embodiment shown in FIG. 14 is designed so that each MOS transistor constituting each circuit can suppress the leak current even if the absolute value of the threshold voltage is lowered. The absolute value of the threshold voltage of each MOS transistor is made as low as possible (about 0.2 V) by using a P-type gate for a P-channel MOS transistor and an N-type gate for an N-channel MOS transistor. It has a feature that an intermittent pulse signal can be output even when the boosted voltage Vdd is low.

FIG. 15 is a circuit diagram of the voltage detection circuit 105 shown in FIG. 1 in this embodiment. First, a description will be given of a connection state. An electromotive voltage input terminal 1501 for inputting an electromotive voltage Vp of a thermoelectric conversion element is connected to a first electrode of a resistor Ra1501 and a gate of an N-channel MOS transistor 1524. The second electrode of the resistor Ra is connected to the first electrode of the resistor Rb and the N-channel MOS transistor 152.
6 gate.

The second electrode of the resistor Rb is connected to the first electrode of the resistor Rc.
And the gate of the N-channel MOS transistor 1528, and the second electrode of the resistor Rc is connected to the drain of the N-channel MOS transistor 1514. The intermittent pulse signal input terminal 1502 for inputting the intermittent pulse signal P2 is
14 and the input terminal of the inverter circuit 1515.

The output terminal of the inverter circuit 1515 is P
The gate of the channel type MOS transistor 1516 and N
Connected to the gate of a channel type MOS transistor 1517. Depletion type (normally on type)
In the N-channel MOS transistor 1518, the drain of the transistor is connected to the drain of the P-channel MOS transistor 1516, and the gate of the transistor is connected to the source of the transistor and the N-channel MOS transistor 1516.
The drain and the gate of the transistor 1519, the drain of the N-channel MOS transistor 1517, the P-channel MOS transistor 1521 and the N-channel MOS
Connected to the gate of S transistor 1522.

P-channel MOS transistor 1520
Is connected to the drain of the transistor, the gates of P-channel MOS transistors 1523, 1525, and 1527, and the drain of N-channel MOS transistor 1521. The source of the N-channel MOS transistor 1521 is connected to the drain of the N-channel MOS transistor 1522 and the sources of the N-channel MOS transistors 1524, 1526, 1528.

P-channel MOS transistor 1523
Of the N-channel MOS transistor 152
4 and a third output of the third detection signal P33.
Output terminal 1503. P-channel type MOS
The drain of the transistor 1525 is an N-channel type MO.
The drain of the S transistor 1526 is connected to the second output terminal 1504 that outputs the second detection signal P32.

P-channel MOS transistor 1527
Of the N-channel MOS transistor 152
8 and a first output of the first detection signal P31.
Output terminal 1505. A Vdd input terminal 1506 for inputting the boosted voltage Vdd is a P-channel type MOS.
Transistors 1516, 1520, 1523, 152
5,1527 sources, N well and inverter circuit 1
515 power supply.

N-channel MOS transistor 151
Source of 4,1517,1519,1522 is GND
Connected to terminal. Note that, in a portion surrounded by a dotted line shown in FIG. 15, reference numeral 1508 denotes a voltage dividing resistor, 1504 denotes a reference voltage generating circuit, and 1510 denotes a comparator circuit. Also,
The connection to the above-mentioned GND terminal means that the GND potential input terminal 1 connected to the lower potential side electrode of the thermoelectric conversion element.
507.

Next, the operation of each section will be described. The voltage dividing resistor 1508 outputs a divided voltage of the electromotive voltage Vp of the thermoelectric conversion element. The divided voltage includes a resistor Ra1511 and a resistor Rb1.
A first divided voltage for dividing the voltage by a resistor in which the resistor 512 and the resistor Rc1514 are connected in series, a resistor Ra1511 and a resistor Rb
1512, and a second divided voltage divided by a resistor Rc1514. The first divided voltage is a first electrode of a resistor Rb1512, and a second divided voltage. The divided voltage is output from the first electrode of the resistor Rc. Further, the N-channel MOS transistor 1514 having the gate to which the intermittent pulse signal P2 is input outputs a divided voltage only during the period when the intermittent pulse signal P2 is "high", and when the intermittent pulse signal P2 is "low". By cutting off the current flowing through each resistor so as not to generate a divided voltage, intermittent operation is performed to reduce current consumption.

The reference voltage generator 1509 outputs a reference voltage. The reference voltage is output from the drain of the N-channel MOS transistor 1519. Further, a P-channel MOS transistor 1516 which inputs the intermittent pulse signal P2 to the gate via the inverter circuit 1509
The N-channel MOS transistor 1517 outputs a reference voltage only during a period when the intermittent pulse signal P2 is “high”, and turns off the P-channel MOS transistor 1516 during a period when the intermittent pulse signal P2 is “low”. Vd
By cutting the current from d, turning on the N-channel MOS transistor 1517 and outputting the GND potential instead of the reference voltage, intermittent operation is performed to reduce current consumption.

The comparator circuit section 1510 is a comparator circuit using a current mirror type comparator system. The comparator circuit section 1510 inputs the reference voltage input to the gate of the N-channel MOS transistor 1521 and the gate of the N-channel MOS transistor 1524. The electromotive voltage Vp of the thermoelectric conversion element is compared. When the voltage of Vp is lower than the reference voltage, the signal is “high”. When the voltage of Vp is higher than the reference voltage, the signal is low. Is output from the third output terminal 1503 as the third detection signal P33, the reference voltage, the N-channel MOS
Voltage-dividing resistor 1 input to the gate of transistor 1526
The first divided voltage from 508 is compared, and is “high” when the first divided voltage is lower than the reference voltage, and when the first divided voltage is higher than the reference voltage. An operation of outputting a “low” signal as a second detection signal P2 from a second output terminal 1504;
The second divided voltage from the voltage dividing resistor unit 1508 input to the gate of the N-channel MOS transistor 1528 is compared, and when the second divided voltage is lower than the reference voltage, “high”; If the first divided voltage is higher than the reference voltage, a "low" signal is output to the first detection signal P31.
Is output from the first output terminal 1505.

Further, the comparator circuit 1510
When the reference voltage is output by the N-channel MOS transistor 1522 that inputs the reference voltage to the gate, that is, when the intermittent pulse signal P2 is "high", a current flows to the GND terminal. Therefore, the detection operation is performed, and when the reference voltage is not output and the GND potential is output, that is, when the intermittent pulse signal is “low”, the current to the GND terminal is cut off. ,
The detection operation is disabled. In other words, the current consumption is reduced by performing the detection operation intermittently.

The first divided voltage is 0.4 V when the electromotive voltage Vp of the thermoelectric conversion element is 0.8 V, and the second divided voltage is 1.0 V when the electromotive voltage Vp of the thermoelectric conversion element is 1.0 V. It is designed to be 0.4V at 6V, and the reference voltage is 0.4V.
v. That is, the third detection voltage P33 is “low” when the electromotive voltage Vp of the thermoelectric conversion element is 0.4 V or more, and “high” when the Vp is less than 0.4 V.
And the second detection signal P2 indicates that Vp is 0.8
When the voltage is equal to or higher than V, the signal is "low", and when the voltage Vp is less than 0.8 V, the signal becomes "high". High ".

Further, the voltage detection circuit 105 of the present embodiment shown in FIG. 15 is configured such that each MOS transistor constituting each circuit has a P.sub.P so that the leakage current can be suppressed even if the absolute value of the threshold voltage is lowered. For a channel type MOS transistor, a P-type gate, for an N-channel type MOS transistor,
By using an N-type gate, the absolute value of the threshold voltage of each MOS transistor is minimized (about 0.2 V).
In addition, even if the boosted voltage Vdd or the electromotive voltage Vp of the thermoelectric conversion element is low, each detection signal can be output.

In other words, the voltage detection circuit 105 of this embodiment shown in FIG. 1 is configured as shown in FIG. 15, and operates intermittently with the intermittent pulse signal P2, thereby reducing the current consumption. Can be realized. FIG. 16 shows a circuit diagram of the signal storage circuit 106 shown in FIG. 1 in this embodiment. First, a connection state will be described. A first input terminal 1601 for inputting a first detection signal P31 output from the voltage detection circuit is connected to a signal input terminal of the first storage circuit 1610 and output from the voltage detection circuit. Second detection signal P
32 is connected to the signal input terminal of the second storage circuit 1611, and the third input terminal 1603 for receiving the third detection signal P33 output from the voltage detection circuit is connected to the third input terminal 1603. Connect to the signal input terminal of the memory circuit 1612.

An intermittent pulse signal input terminal 1604 for inputting the intermittent pulse signal P2 output from the intermittent pulse generation circuit
Is connected to the first intermittent pulse signal input terminal of each of the first storage circuit 1610, the second storage circuit 1611, and the third storage circuit 1612, and the input terminal of the inverter circuit 1613, and the output terminal of the inverter circuit 1613 First storage circuit 1610, second storage circuit 1611, and third storage circuit 16
Twelve second intermittent pulse signal input terminals.

The Vdd input terminal 1608 for inputting the boosted voltage Vdd is connected to the first storage circuit 1610 and the second storage circuit 1610.
11 and a GND potential input terminal 1609 connected to the respective Vdd input terminals of the third storage circuit 1612 and connected to the lower potential side electrode of the thermoelectric conversion element.
And the GND potential input terminals of the second storage circuit 1611 and the third storage circuit 1612.

The output terminal of the first storage circuit 1610
, And the output terminal of the second storage circuit 1611 is connected to the second output terminal 1606 that outputs the second storage signal P42. The output terminal of 1612 is connected to the third output terminal 1607 which outputs the third storage signal P43.

A power supply terminal of the inverter circuit 1613 is connected to a Vdd input terminal 1608 for inputting the boosted voltage Vdd.
, And the GND terminal of the inverter circuit 1613 is connected to the GND potential input terminal 1609 connected to the lower potential side electrode of the thermoelectric conversion element. Next, the operation will be described. First,
During the period when the intermittent pulse signal P2 is “high”, the first intermittent pulse signal input terminal of each memory circuit is “high” and the second intermittent pulse signal input terminal of each memory circuit is “low”. The first storage circuit 1610 stores the first detection signal P3
1 is output to the first output terminal 1605 and the second signal
The storage signal circuit 1611 outputs the same signal as the second detection signal P32 to the second output terminal 1606, and the third storage circuit 1612 outputs the same signal as the third detection signal P33 to the third output terminal 1607. Output.

Next, during the period in which the intermittent pulse signal P2 goes "low" after "high", the first intermittent pulse signal input terminal of each memory circuit goes "low" and the second
Since the intermittent pulse signal input terminal becomes “high”, the first
The storage circuit 1610 stores the voltage of the first detection signal P31 when the intermittent pulse signal P2 changes from “high” to “low”, and stores the stored voltage of the first detection signal P31 in the first output terminal 1605. To the second storage circuit 161
1 stores the voltage of the second detection signal P32 when the intermittent pulse signal P2 changes from “high” to “low”, and stores the stored voltage of the second detection signal P32 in the second output terminal 160.
6, the third storage circuit 1612 stores the voltage of the third detection signal P33 when the intermittent pulse signal P2 changes from “high” to “low”, and stores the voltage of the stored third detection signal P33. The voltage is continuously output to the third output terminal 1607.

That is, the signal storage circuit 106 shown in FIG. 1 is configured as shown in FIG. 16, so that the period in which the intermittently operating voltage detection circuit is operating, that is, the intermittent pulse signal
During the “high” period, the detection signal of the voltage detection circuit 105 is output as a storage signal as it is, and during the period when the voltage detection circuit is not operating, that is, during the period when the intermittent pulse signal is “low”, the voltage before the period is applied. A signal storage circuit that stores a detection signal during a period in which the detection circuit is operating and outputs the stored detection signal as a storage signal can be realized.

FIG. 17 shows the first storage circuit 16 shown in FIG.
10 is a circuit diagram of the second storage circuit 1611 and the third storage circuit 1612. First, the connection state will be described. The detection signal input terminal 1702 for inputting the detection signal is a P-channel type M
Source of OS transistor 1708 and N-channel type MO
Connect to the drain of S transistor 1709. The first intermittent pulse signal input terminal 1703 to which the intermittent pulse signal P2 is input is connected to the N-channel MOS transistor 17.
09 and P-channel MOS transistor 171
0 gate.

A second intermittent pulse signal input terminal 1704 to which a signal whose phase is inverted from that of the intermittent pulse signal P2 is input.
Is connected to the gate of the P-channel MOS transistor 1708 and the gate of the N-channel MOS transistor 1711. P-channel MOS transistor 1708
Of the N-channel MOS transistor 170
9 and a P-channel MOS transistor 171
0 and the N-channel MOS transistor 171
1 and the input terminal of the inverter circuit 1712, and the output terminal of the inverter circuit 1712 is connected to the input terminal of the inverter circuit 1713.

The output terminal of the inverter circuit 1713 is P
A drain of a channel type MOS transistor 1710;
A source of an N-channel MOS transistor 1711;
It is connected to a storage signal output terminal 1705 that outputs a storage signal. A Vdd input terminal 1706 for inputting the boosted voltage Vdd is connected to a P-channel MOS transistor 170.
8, 1710 N-wells and inverter circuits 1712,
A GND potential input terminal 1707 connected to the power supply terminal of the thermoelectric conversion element 1713 and connected to the lower potential side electrode of the thermoelectric conversion element is connected to the GND terminals of the inverter circuits 1712 and 1713.

Next, the operation will be described. First, when the intermittent pulse signal P2 is "high", the first intermittent pulse signal input terminal 1703 is "high" and the second intermittent pulse signal input terminal 1704 is "low". , The N-channel MOS transistor is turned on, the P-channel MOS transistor 1710 and the N-channel MOS transistor 1711 are turned off, and the detection signal input from the detection signal input terminal 1702 is input to the input terminal of the inverter circuit 1712. Therefore, the detection signal is output from the storage signal output terminal 1705 as it is.

Next, the intermittent pulse signal P2 is changed to the aforementioned "
When the state changes from “high” to “low”, the first intermittent pulse signal input terminal 1703 changes to “low” and the second intermittent pulse signal input terminal 1704 changes to “high”. And N-channel MO
The S transistor is turned off, and the P-channel MOS transistor 1710 and the N-channel MOS transistor 171
1 is turned on, and the input terminal of the inverter circuit 1712 is
The detection signal input from the detection signal input terminal 1702 is not input, and the last detection signal when the above-described intermittent pulse signal is “high” remains input. Therefore, the intermittent pulse is output from the storage signal output terminal 1705. The last detection signal when the signal is "high" continues to be output.

That is, with the configuration shown in FIG. 17, when the intermittent pulse signal is "high", that is, when the voltage detection circuit is operating and outputting the detection signal, the detection signal is not changed. Is output as a storage signal, and when the above-mentioned intermittent pulse signal goes from “high” to “low”, that is, when the voltage detection circuit stops and the detection signal is no longer output, the above-mentioned intermittent pulse signal is output. Is "High", the last detection signal is stored, and the next intermittent pulse signal is "High".
A storage circuit that continues to output the stored detection signal until the time becomes

As described above, in this embodiment, the signal storage circuit 106 shown in FIG. 1 is configured as shown in FIG. 16 by using a storage circuit having the configuration shown in FIG.
When the intermittently operating voltage detection circuit 105 shown in FIG. 1 is operating, the detection signal of the voltage detection circuit is output as a storage signal as it is, and when the voltage detection circuit is stopped, A signal storage circuit that stores a detection signal before the detection circuit is stopped, that is, when the circuit is operating, and outputs the stored detection signal until the voltage detection circuit starts operating next time can be realized.

Further, the signal storage circuit according to the present embodiment comprises:
For each MOS transistor constituting the signal storage circuit, a P-type gate for a P-channel type MOS transistor and a P-type gate for an N-channel type MOS transistor so that leakage current can be suppressed even if the absolute value of the threshold voltage is lowered. By using an N-type gate, the absolute value of the threshold voltage of each MOS transistor is made as low as possible (about 0.2 V), and even if the boosted voltage Vdd or the electromotive voltage Vp of the thermoelectric conversion element is low, It has a feature that can output a stored signal.

[0161]

The present invention is embodied in the form described above and has the following effects. By installing a P-channel type MOS transistor and an N-channel type MOS transistor in appropriate places, charging and discharging a capacitor with the MOS transistor to boost the voltage, a booster circuit with high boosting efficiency and capable of boosting voltage from a low voltage can be realized.

The absolute value of the threshold voltage of each MOS transistor is determined by using a MOS transistor having a P-type gate if the MOS transistor is a P-channel type MOS transistor and an N-type gate if the MOS transistor is an N-channel type MOS transistor. Since the voltage can be reduced, it is possible to realize a booster circuit capable of further raising the voltage from a low voltage. In addition, a power supply that generates power by external energy, for example, an oscillation circuit that can vary the frequency of a clock signal that is output according to the electromotive voltage of the thermoelectric conversion element is provided. By adopting a configuration in which the voltage is boosted, a boosting system that can convert the electromotive force of the thermoelectric conversion element to boosted power without waste can be realized.

Further, a voltage detection circuit for detecting an electromotive voltage of the thermoelectric conversion element and outputting a detection signal corresponding to the electromotive voltage is provided, and the detection signal output from the voltage detection circuit determines the boosting multiple of the booster circuit. With a variable configuration, it is possible to realize a boosting system that can efficiently convert the electromotive force of the thermoelectric conversion element into boosted power even if the electromotive voltage of the thermoelectric conversion element fluctuates.

Further, an intermittent pulse generation circuit for generating an intermittent pulse from a clock signal from an oscillation circuit is provided, and the voltage detection circuit is operated intermittently by the intermittent pulse signal. And outputting the detection signal output from the voltage detection circuit to the booster circuit as a storage signal. During a period in which the voltage detection circuit is not operating, the final detection when the previous voltage detection circuit was operating is performed. A signal storage circuit that stores the signal and outputs the stored detection signal to the booster circuit as a storage signal until the voltage detection circuit operates next, and the booster circuit outputs the signal from the signal storage circuit. With a configuration in which the boosting factor is varied according to the storage signal, the current consumed by the voltage detection circuit is reduced, and an efficient boosting system can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a boosting system.

FIG. 2 is a circuit diagram showing an embodiment of a booster circuit.

FIG. 3 is a circuit diagram of a booster circuit.

FIG. 4 is a circuit diagram of a booster circuit.

FIG. 5 is a circuit diagram of a booster circuit.

FIG. 6 is a circuit diagram of an embodiment of a booster circuit.

FIG. 7 is a circuit diagram showing an embodiment of a booster circuit.

FIG. 8 is a circuit diagram showing an embodiment of a booster circuit.

FIG. 9 is a circuit diagram of an embodiment of a booster circuit.

FIG. 10 is a circuit diagram showing an embodiment of a booster circuit.

FIG. 11 is a circuit diagram showing an embodiment of a booster circuit.

FIG. 12 is a circuit diagram showing an embodiment of a booster circuit.

FIG. 13 is a circuit diagram showing an embodiment of an oscillation circuit.

FIG. 14 is a circuit diagram showing an embodiment of an intermittent pulse generation circuit.

FIG. 15 is a circuit diagram showing an embodiment of a voltage detection circuit.

FIG. 16 is a circuit diagram showing an embodiment of a signal storage circuit.

FIG. 17 is a circuit diagram illustrating an embodiment of a signal storage circuit.

FIG. 18 is a block diagram showing a conventional boosting system.

FIG. 19 is a circuit diagram showing a booster circuit of a conventional booster system.

[Explanation of symbols]

 Reference Signs List 101 thermoelectric conversion element 103 oscillation circuit 104 intermittent pulse generation circuit 105 signal storage circuit 107 booster circuit P1 clock signal P2 intermittent pulse signal P3 detection signal P4 storage signal VP electromotive voltage Vdd boosted voltage GND GND terminal

──────────────────────────────────────────────────続 き Continuation of the front page (72) Miwauchi Miwa, Inventor 1-8-8 Nakase, Mihama-ku, Chiba-shi, Chiba Pref. JP-A-9-73326 (JP, A) JP-A-64-50553 (JP, A) JP-A-8-262161 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H02M 3/07

Claims (16)

(57) [Claims] 1. An M having a gate electrode and first and second electrodes.
An OS transistor is used as a switch element, and an input terminal is connected to a first electrode of the first switch element and a second electrode of the third switch element, and a second electrode of the first switch element is connected to a second electrode of the capacitor. And the second of the second switch elements
And the first electrode of the second switch element is connected to
Connected to the ND terminal, the first electrode of the capacitor is connected to the third
A first electrode of the switching element, is connected to the second electrode of the fourth switching element, the first electrode of the fourth switching element takes the connected configuration to the output terminal, the first and fourth switching elements off While the second and the second
Operation for turning on three switch elements, and second and third switches
While the element is off, the first and fourth switch elements are turned off.
Switch elements so that
Input a control signal to the gate electrode of
Output voltage that is higher than the input
A first booster unit and a second booster unit configured to output from
The boosting power output from the first boosting unit.
The power thus obtained as input power of the second booster unit,
Using the boosted power output from the second boosting unit,
And the first boosting unit is configured to output a compressed power .
The first electrode of the first to fourth switch elements is a source electrode, and the second electrode is a second electrode.
The electrode is the drain electrode and the substrate electrode is GND
Consists of N-channel MOS transistor connected to terminal
And, the second step-up unit, first from a first of said booster unit
The first electrode of the three switch element is a source electrode and the second electrode is a drain electrode.
Use a rain electrode and connect the substrate electrode to the GND terminal.
And a fourth N-channel MOS transistor.
The first electrode of the switch element is a source electrode, and the second electrode is a drain electrode.
Connect the substrate electrode to the source electrode as the in electrode
To be configured with a P-channel MOS transistor
An electronic device having a booster circuit. 2. The first boosting unit, or
The power of the input power input to the input terminal of the second booster unit
The pressure is used for a fourth switch element of the second booster unit.
Threshold Voltage of P-Channel MOS Transistor
The electronic device according to claim 1, wherein the absolute value is equal to or smaller than the absolute value of the electronic device. 3. An M transistor having a gate electrode and first and second electrodes.
Using an OS transistor as a switch element, the input terminal
The first switch element has a first electrode and a third switch element.
The second electrode of the first switch element is connected to the second electrode of the
Is the second electrode of the capacitor and the second electrode of the second switch element.
And the first electrode of the second switch element is connected to
Connected to the ND terminal, the first electrode of the capacitor is connected to the third
A first electrode of the switch element and a second electrode of the fourth switch element;
And the first electrode of the fourth switch element is connected to the output
It takes connected to each terminal, while the first and fourth switching elements are turned off, the second and
Operation for turning on three switch elements, and second and third switches
While the element is off, the first and fourth switch elements are turned off.
Switch elements so that
Input a control signal to the gate electrode of
Output voltage that is higher than the input
A first booster unit and a second booster unit configured to output from
The boosting power output from the first boosting unit.
The power thus obtained as input power of the second booster unit,
Using the boosted power output from the second boosting unit,
And the first boosting unit is configured to output a compressed power .
The first electrode of the first to fourth switch elements is a source electrode, and the second electrode is a second electrode.
The electrode is the drain electrode and the substrate electrode is GND
Consists of N-channel MOS transistor connected to terminal
And, the second step-up unit, the first and third of said booster unit
And a fourth switch element, the first electrode is a source electrode, the second electrode
Pole as the drain electrode and the substrate electrode as the source electrode.
Consists of P-channel MOS transistor connected to the pole
The first electrode of the second switch element is connected to the source electrode,
Electrode as drain electrode and substrate electrode as GN
An N-channel MOS transistor connected to the D terminal
An electronic device having a booster circuit characterized by comprising: 4. An input to an input terminal of said first step-up unit.
The voltage of the input power to be input is the first input voltage of the two booster units.
Or a P-channel type MO used for the third switch element
It must be less than the absolute value of the threshold voltage of the S transistor
The electronic device according to claim 3, wherein: 5. An M having a gate electrode and first and second electrodes.
Using an OS transistor as a switch element, the input terminal
The first switch element has a first electrode and a third switch element.
The second electrode of the first switch element is connected to the second electrode of the
Is the second electrode of the capacitor and the second electrode of the second switch element.
And the first electrode of the second switch element is connected to
Connected to the ND terminal, the first electrode of the capacitor is connected to the third
A first electrode of the switch element and a second electrode of the fourth switch element;
And the first electrode of the fourth switch element is connected to the output
It takes connected to each terminal, while the first and fourth switching elements are turned off, the second and
Operation for turning on three switch elements, and second and third switches
While the element is off, the first and fourth switch elements are turned off.
Switch elements so that
Input a control signal to the gate electrode of
Output voltage that is higher than the input
A first booster unit and a second booster unit configured to output from
The boosting power output from the first boosting unit.
The power thus obtained as input power of the second booster unit,
Using the boosted power output from the second boosting unit,
And the first boosting unit is configured to output a compressed power .
The first electrode of the first to third switch elements is a source electrode, the second electrode is
The electrode is the drain electrode and the substrate electrode is GND
Consists of N-channel MOS transistor connected to terminal
Then, the first electrode of the fourth switch element is connected to the source electrode and the second electrode.
Pole as the drain electrode and the substrate electrode as the source electrode.
Consists of P-channel MOS transistor connected to the pole
And, the second step-up unit, the first and third of said booster unit
And a first electrode of the fourth switch element as a source electrode and a second electrode
Is the drain electrode and the substrate electrode is the source electrode
Composed of a P-channel MOS transistor connected to
The first electrode of the second switch element is a source electrode, and the second electrode is a second electrode.
The pole is the drain electrode and the substrate electrode is the GND end
Composed of N-channel MOS transistors connected to
An electronic device having a booster circuit . 6. An input to an input terminal of the first booster unit.
Voltage input power is the fourth switch of the booster unit
Of a P-channel MOS transistor used in a
The electronic device according to claim 5, wherein the threshold voltage is equal to or less than an absolute value of the threshold voltage . 7. An M having a gate electrode and first and second electrodes.
An OS transistor is used as a switch element, and an input terminal is connected to a first electrode of the first switch element and a third switch element.
The second electrode of the first switch element is connected to the second electrode of the capacitor and the second electrode of the second switch element.
And the first electrode of the second switch element is connected to
Connected to the ND terminal, the first electrode of the capacitor is connected to the third
A first electrode of the switch element and a second electrode of the fourth switch element;
And the first electrode of the fourth switch element is an output terminal.
Taking a configuration that is connected to the child, while the first and fourth switching elements are turned off, the second and
Operation for turning on three switch elements, and second and third switches
While the element is off, the first and fourth switch elements are turned off.
Switch elements so that
Input a control signal to the gate electrode of
Output voltage that is higher than the input
A first booster unit and a second booster unit configured to output from
And a third booster unit , using boosted power output from the first booster unit.
The power thus obtained as input power of the second booster unit,
Power using the boosted power output from the second booster unit
The power is defined as the input power of the third booster unit,
Using the boost power output from the boost unit,
And the first booster unit is configured to output a force .
The first electrode of the first to fourth switch elements is a source electrode, and the second electrode is a second electrode.
The electrode is the drain electrode and the substrate electrode is GND
Consists of N-channel MOS transistor connected to terminal
And, the second step-up unit, first from a first of said booster unit
The first electrode of the three switch element is a source electrode and the second electrode is a drain electrode.
Use a rain electrode and connect the substrate electrode to the GND terminal.
And a fourth N-channel MOS transistor.
The first electrode of the switch element is a source electrode, and the second electrode is a drain electrode.
Connect the substrate electrode to the source electrode as the in electrode
And the third booster unit includes first and third booster units of the booster unit.
And a first electrode of the fourth switch element as a source electrode and a second electrode
Is the drain electrode and the substrate electrode is the source electrode
Composed of a P-channel MOS transistor connected to
The first electrode of the second switch element is a source electrode, and the second electrode is a second electrode.
The pole is the drain electrode and the substrate electrode is the GND end
Composed of N-channel MOS transistors connected to
An electronic device having a booster circuit. 8. The first boosting unit or the first boosting unit,
The power of the input power input to the input terminal of the second booster unit
The pressure is used for a fourth switch element of the second booster unit.
Threshold Voltage of P-Channel MOS Transistor
The electronic device according to claim 7, wherein the absolute value is not more than the absolute value of 9. An M transistor having a gate electrode and first and second electrodes.
Using an OS transistor as a switch element, the input terminal
The first switch is connected to the first electrode of the first switch element, and is connected to the first switch.
The second electrode of the switch element is connected to the second electrode of the capacitor.
A second switch connected to the second electrode of the two-switch element;
The first electrode of the element is connected to the GND terminal and a capacitor
The first electrode of the first switch is connected to the first electrode of the third switch element and the output of the third switch element.
And the second electrode of the third switch element is connected to the
The first switch element is configured to be connected to the source terminal.
While the switch is off, the second switch element and the third switch element
Following the operation of turning on the switch, the second switch element and the third switch
The first switch element is turned on while the switch element is off.
Operation of each switch element so that
A control signal is input to the gate electrode, and the first switch element is turned off.
Input voltage from the input terminal,
Or, from the power supply voltage input from the power supply terminal
Output voltage having a high voltage from the output terminal.
A first booster unit and a second booster unit, and uses boosted power output from the first booster unit.
The input power of the input terminal of the second booster unit
And the boosted power output from the second booster unit is
The first boosting unit is configured to output boosted power using the first boosting unit.
The first to third switch elements, the first electrode is a source electrode, the
Two electrodes as drain electrodes and substrate electrode as GN
An N-channel MOS transistor connected to the D terminal
And the second booster unit has a first switch of the booster unit.
Ji element, the first electrode source over the source electrode, the drain of the second electrode
Electrode, substrate electrode connected to source electrode
P-channel type MOS transistors, the second and third
The switch element is connected to the first electrode as the source electrode and the second electrode as the source electrode.
Use a rain electrode and connect the substrate electrode to the GND terminal.
Constructing a continuous N-channel MOS transistor
An electronic device having a step-up circuit . 10. An input to an input terminal of said first booster unit.
Input power voltage or power supply power
The pressure is used for a first switch element of the second booster unit.
Threshold Voltage of P-Channel MOS Transistor
The electronic device according to claim 9, wherein the absolute value is equal to or less than the absolute value of 11. A MOS transistor having a gate electrode and first and second electrodes is used as a switch element, a first input terminal is connected to a first electrode of the switch element, and a second electrode of the switch element is connected to a first electrode of the switch element. , The first electrode of the capacitor and the output terminal, the second electrode of the capacitor,
Take the connection configurations to the second input terminal, the period in which the switching element is turned on, year second input
The operation of inputting a voltage lower than a certain voltage to the terminal
While the switch element is off, the second input terminal
Operation of inputting a voltage higher than the certain voltage to
The gate electrode of the switch element is alternately repeated.
Input a control signal to the second input terminal.
The first input terminal each time a voltage higher than
With a voltage higher than the voltage of the input power input from
A first booster unit configured to output the compressed power to the output terminal.
And a second booster unit , using boosted power output from the first booster unit.
The power thus obtained as input power of the second booster unit,
Using the boosted power output from the second booster unit
The first boosting unit is configured to output boosted power, and the first boosting unit is configured to output boosted power .
The switch element has a first electrode as a drain electrode and a second electrode as a source electrode.
Substrate electrode and connect substrate electrode to GND terminal
And the second booster unit includes a switch of the booster unit.
The device has a first electrode as a drain and a second electrode as a source,
P-channel type M with substrate electrode connected to source
An electronic device including a booster circuit, which is an OS transistor . 12. An input terminal of the first booster unit.
The voltage of the input power to be input is equal to the voltage of the second booster unit.
P-channel type MOS transistor used for switch element
The electronic device according to claim 11, wherein the threshold voltage is equal to or less than an absolute value of a threshold voltage of the electronic device. 13. The boosting circuit according to claim 13 , wherein said control signal is boosted by said boosting circuit.
It is configured to generate using electric power.
A first voltage level having a voltage level and a second voltage level.
Is a voltage corresponding to the voltage of the boosted power, and the second power
The voltage level is a voltage corresponding to the voltage of the GND terminal.
13. The method according to claim 1, further comprising a booster circuit characterized by the following.
An electronic device according to any one of the above . 14. The electronic device further supplies electric power.
Power supply, and the power is supplied by the power supply.
Voltage circuit generates boosted power of a voltage higher than the power voltage.
And the step-up circuit further comprises:
Is used as the switch element.
Threshold voltage of P-channel MOS transistor
2. The method according to claim 1, wherein the operation is performed when the value is equal to or smaller than a logarithmic value.
14. The electronic device according to any one of 13 . 15. The power supply generates an electromotive force according to a temperature difference.
The electronic device according to claim 14, wherein the electronic device is a thermoelectric conversion element . 16. The wristwatch according to claim 16, wherein said electronic device is a wristwatch.
The watch has the booster circuit, thermoelectric conversion element and
An IC having an IC, and
The electronic device according to claim 15, wherein the electronic device drives a clock IC .