KR100926677B1 - Unit charge pump - Google Patents

Abstract

The present invention discloses a unit charge pump which makes the voltage values of the boost node have the same voltage level during the initial operation, and prevents the overvoltage to the boost node when entering the standby mode. The unit charge pump may include a first PMOS charge transfer transistor, a second PMOS charge transfer transistor, a first NMOS charge transfer transistor, a second NMOS charge transfer transistor, a precharge control unit, a bulk bias supply unit, a pumping charge storage unit, and a boost strap node overvoltage protection unit. do.

Cross Coupled, Charge Pump, Boost Node Overvoltage, Precharge Control

Description

Unit Charge Pump

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a unit charge pump, and more particularly, to a unit charge pump in which a boost node operates symmetrically at an initial stage of charge pumping and prevents an overvoltage from being applied to a boost terminal when entering a standby mode.

BACKGROUND Small display devices used in cellular phones, digital cameras (DSCs), and portable mobile devices are among the technical fields that need to increase product competitiveness through miniaturization and light weight. In particular, in the case of a mobile phone terminal or an MP3 player, the size and thickness of the mobile phone is significantly reduced, so the development of SoC (System on a Chip) technology that can achieve miniaturization and low price is very competitive. QQVGA (128RGB × 160) TFT-LCD (Thin Film Transistor-Liquid Crystal Display) is mainly used as a small display device.

Table 1 shows the driving voltages used for the TFT-LCD panel.

division Usage DDVDH Source Line Power VGH Gate Line High Voltage VGL Gate Line Low Voltage

Referring to Table 1, the voltage sources used to drive the TFT-LCD panel are the source line voltage (DDVDH), the gate line high voltage (VGH), and ground, which are positive high voltages higher than the input power supply voltage (VCI). There is a boosted voltage such as the gate line low voltage VGL, which is a negative low voltage lower than the voltage GND. [M. Hirata et al., "New Plus- and Minus-Voltage Generator for TFT-LCD Panels," Proceedings of the 2nd IEEE Asia-Pacific Conference on ASIC, pp. 17-20, Aug. 2000.] Here, the source line voltage DDVDH is used as the driving voltage of the source line of the TFT-LCD pixel, and the gate line high voltage VGH and the gate line low voltage VGL are the gate line. Used as the driving voltage of.

As a DC-DC converter that supplies the voltage required to drive the gate line and the source line in a TFT-LCD integrated circuit, a pulse width modulation (PWM) method using an inductor and a switched capacitor circuit It can be implemented by the charge pump (Charge Pump) method. The charge pump method by a switch-capacitor circuit combining a plurality of switches and a plurality of capacitors has advantages such as miniaturization of a driving IC module. However, in case of using an external pumping capacitor in a switch-capacitor charge pump method, a pumping capacitor and a charge storage capacitor must be used externally for each pumping stage, thus the TFT-LCD module Has difficulty in miniaturization [E. Bayer et al., “A High Efficiency Single-Cell Cascaded Charge Pump Topology,” Proc. IEEE Power Electronics Specialists Conference, vol. 1, pp. 290-295, Aug. 2001.]. Recently, a charge pump method using an internal pumping capacitor has been studied to solve this disadvantage.

As a charge pump using a built-in pumping capacitor, a cross-coupled charge pump circuit is mainly used. [P. Favrat et al., "A high-efficiency CMOS voltage doubler," IEEE JSSC, vol. 33, pp. 410-416, Mar. 1998.]

1 is an example of a conventional two-phase cross coupled unit charge pump circuit diagram.

Referring to FIG. 1, the cross-coupled unit charge pump 100 removes the threshold voltage loss during charge transfer using the PMOS cross-coupled charge transfer switches MP1 and MP2. However, parasitic PNP Bi-polar Junction Transistors (BJTs) exist in the PMOS cross-coupled charge transfer switches (MP1, MP2), and these BJTs are charge pumping at the boost trap terminals (N1, N2). Because of its operation in the active region, there is a charge loss problem in which the pumped charges escape to the substrate. In addition, each time the number of pumping stages is increased for the high voltage, the threshold voltage V _TH is increased due to the body effect of the NMOS charge transfer switches MN1 and MN2, thereby reducing the pumping current.

Here, two phases means that two clock signals CLK1 and CLK2 do not overlap each other (Non Overlap). That is, it means that the time period when one clock signal of the two clock signals is enabled and the time period when the other clock signal is enabled do not overlap each other.

2 is another example of a conventional two-phase cross coupled unit charge pump circuit diagram.

Referring to FIG. 2, the two-phase cross coupled unit charge pump circuit 200 includes cross-coupled NMOS charge transfer switches MN1 and MN2 and cross-coupled PMOS charge transfer switches MP1 and MP2. And MOS transistors MN3, MN4, MN5, MN6, MP3, MP4, MP5 and MP6 used as the bulk potential bias circuits 210, 220, 230, and 240, and the charge pumping capacitors C1 and C2. [S. I. Cho et al., "A Boosted Voltage Generator for Low-Voltage DRAMs," Current Applied Physics, vol. 3, pp. 501-505, Dec. 2003.]

The body voltages of the PMOS cross-coupled charge transfer switches MP1 and MP2 connected to the output terminal VOUT using the PMOS bulk potential bias circuits 230 and 240 (MP3 to MP6) are connected to the boost strap terminals N1 and N2. Solving the charge loss problem by having a higher voltage between the voltage and the output terminal (VOUT), and cross-coupled to the input terminal (VIN) using NMOS bulk potential bias circuits 210 and 220 (MN3 to MN6). The body voltage of each charge transfer switch (MN1, MN2) is electrically connected to the lower voltage between the voltage of the input terminal (VIN) and the voltage of the boost strap terminals (N1, N2), thereby preventing an increase in the threshold voltage due to the body effect. have.

Operation of the two phase cross coupled unit charge pump circuits 100 and 200 shown in FIGS. 1 and 2 is generally known and will not be described in detail here.

3 shows voltage waveforms of the boost straps N1 and N2 with time.

Referring to FIG. 3, in the conventional two-phase cross-coupled unit charge pump circuit 200 shown in FIG. 2, voltage values of the boost strap nodes N1 and N2 according to a change in time during an initial operation may be obtained. Since they do not have the same voltage level, the pumping efficiency is lowered.

In addition, when the stand-by mode is entered, the pumped charges of the boost nodes N1 and N2 do not discharge properly and maintain a high voltage, thereby causing a problem in the reliability of transistors connected to the boost nodes N1 and N2. Let's do it.

An object of the present invention is to provide a unit charge pump to make the voltage values of the boost strap node have the same voltage level during the initial operation, and to prevent overvoltage at the boost strap node when entering the standby mode.

According to an aspect of the present invention, a unit charge pump includes a first PMOS charge transfer transistor, a second PMOS charge transfer transistor, a first NMOS charge transfer transistor, a second NMOS charge transfer transistor, a precharge control unit, a bulk bias supply unit, and a pump. Ping charge storage and boost strap node overvoltage protection.

The first PMOS charge transfer transistor switches an input voltage applied from an input terminal to a first boost strap node. The second PMOS charge transfer transistor switches the input voltage to a second boost strap node. The first NMOS charge transfer transistor switches the voltage of the first boost strap node to an output terminal. The second NMOS charge transfer transistor switches the voltage of the second boost strap node to the output terminal. The precharge control unit applies a precharge control signal to gates of the first NMOS charge transfer transistor and the second NMOS charge transfer transistor. The bulk bias supply unit supplies a first bulk bias to the bulk of the first PMOS charge transfer transistor and a second bulk bias to the bulk of the second PMOS charge transfer transistor. The pumping charge storage unit stores charges pumped in the gate terminals of the first NMOS charge transfer transistor and the second NMOS charge transfer transistor, the first boost node and the second boost node in response to a plurality of control clock signals. . The boost strap node overvoltage prevention unit has one terminal connected to the first boost strap node and the other terminal connected to the second boost strap node. Gates of the first NMOS charge transfer transistor and the second NMOS charge transfer transistor are cross coupled.

According to another aspect of the present invention, a unit charge pump includes a first PMOS charge transfer transistor, a second PMOS charge transfer transistor, a first NMOS charge transfer transistor, a second NMOS charge transfer transistor, a bulk bias supply unit, and a pumping charge storage unit. And a boost node precharge unit and a boost node overvoltage protection unit.

The first PMOS charge transfer transistor switches an input voltage applied from an input terminal to a first boost strap node. The second PMOS charge transfer transistor switches the input voltage to a second boost strap node. The first NMOS charge transfer transistor switches the voltage of the first boost strap node to an output terminal. The second NMOS charge transfer transistor switches the voltage of the second boost strap node to the output terminal. The bulk bias supply unit includes a first bulk bias, a second bulk bias, and a third bulk bias to bulk of the first PMOS charge transfer transistor, the second PMOS charge transfer transistor, the first NMOS charge transfer transistor, and the second NMOS charge transfer transistor, respectively. And a fourth bulk bias, respectively. The pumping charge storage unit stores charges pumped to the first boosting node and the second boosting node in response to a plurality of control clock signals. The boost node precharge unit has one terminal connected to the first boost strap node and the other terminal connected to the second boost strap node. The boost strap node overvoltage prevention unit has one terminal connected to the first boost strap node and the other terminal connected to the second boost strap node. Gates of the first PMOS charge transfer transistor and the second PMOS charge transfer transistor are cross coupled, and gates of the first NMOS charge transfer transistor and the second NMOS charge transfer transistor are cross coupled.

In the unit charge pump according to the present invention, the boost strap terminals are precharged with the voltage (VIN-V _TN ) during initial operation so that the boost strap terminals operate symmetrically with each other during charge pumping. When | V _TP | is higher than the output terminal voltage, the output terminal is discharged through the PMOS diode so that the high voltage is not applied to each transistor.

Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a circuit diagram of a first type two phase cross coupled unit charge pump according to the present invention.

Referring to FIG. 4, the first type two phase cross coupled unit charge pump 400 includes precharge controllers 410 and 420, PMOS charge transfer switches MP1 and MP2, and cross coupled NMOS charge transfer switches MN1. , MN2, bulk bias supply units 430 and 440, boost node overvoltage protection unit 450, a plurality of charge pumping capacitors C0 to C3, and a plurality of inverters I0 to I3.

The PMOS charge transfer switches MP1 and MP2 receive the voltage VN0 of the first node N0, that is, the voltage 0V of the input terminal IN connected to one terminal in response to the first precharge control signal VN0. In response to the voltage VN3 of the first PMOS charge transfer transistor MP1 and the fourth node N3, that is, the second precharge control signal VN3 transferred to the first boost node N1 connected to the other terminal, The second PMOS charge transfer transistor MP2 transfers the voltage 0V of the input terminal IN connected to the terminal to the second boost strap node N2. The ground voltage 0V applied to the input terminal IN is applied to the bulk of the first PMOS charge transfer transistor MP1 and the second PMOS charge transfer transistor MP2.

The precharge control unit 410 or 420 precharges the first boosting node N1 and the second boosting node N2 to a predetermined initial voltage level, that is, a ground voltage (0V) or another input voltage (VCI), respectively. And a first precharge control circuit 410 and a second precharge control circuit 420.

The first precharge control circuit 410 includes a third PMOS precharge transistor having one terminal, a gate terminal, and a bulk connected to the input terminal IN, and generating the first precharge control signal VNO to the other terminal. MP3) and one terminal and bulk connected to the input terminal IN, the second precharge control signal VN3 is applied to a gate, and the other terminal generates the first precharge control signal VN0. A 4 PMOS precharge transistor MP4 is provided.

The second precharge control circuit 420 is connected to the input terminal IN at one terminal and bulk, the first precharge control signal VN0 is applied to a gate, and the second precharge control signal to the other terminal. A fifth PMOS precharge transistor MP5 for generating VN3 and a second precharge control signal VN3 connected to the input terminal IN at one terminal, a gate terminal, and a bulk, and generating the second precharge control signal VN3 at another terminal; A 6 PMOS precharge transistor MP6 is provided.

The precharge controllers 410 and 420 adjust the voltage levels of the first precharge control signal VN0 and the second precharge control signal VN3 applied to the gates of the two PMOS charge transfer transistors MP1 and MP2. As a result, the voltage levels of the first and second bootstrap nodes N1 and N2 may be divided by one of two voltage levels (-VCI, 0). For example, when the voltage level of the first boost node N1 is -VCI [V], the voltage node of the second boost strap node N2 is 0 [V].

The cross-coupled NMOS charge transfer switches MN1 and MN2 may have voltages of the first boost strap node N1 connected to one terminal according to the voltage level VN2 of the second boost strap node N2 applied to the gate terminal. A second boost node connected to one terminal according to the voltage level VN1 of the first NMOS charge transfer transistor MN1 for transmitting VN1 to the output terminal OUT and the first boost node N1 applied to the gate terminal. A second NMOS charge transfer transistor MN2 is provided to transfer the voltage VN2 of N2 to the output terminal OUT.

The bulk bias supply units 430 and 440 may bias the bulk of the first bulk bias circuit 430 and the second NMOS charge transfer transistor MP2 that supply a bias to the bulk of the first NMOS charge transfer transistor MN1. A second bulk bias circuit 440 is provided.

The first bulk bias circuit 430 includes a third NMOS bias transistor MN3 and one terminal connected to the first boost strap node N1 and an output terminal OUT connected to the gate terminal, and one terminal connected to the output terminal OUT. A first terminal connected to a bulk of the first NMOS charge transfer transistor MN1 and a second terminal of the third bias transistor MN3 and a bulk, and a gate terminal connected to the first boost node N1. 4NMOS bias transistor MN4 is provided.

The second bulk bias circuit 440 includes a fifth NMOS bias transistor MN5 having one terminal connected to the second boost strap node N2 and an output terminal OUT connected to the gate terminal, and one terminal connected to the output terminal OUT. The other terminal and the bulk are connected in common to the bulk of the second NMOS charge transfer transistor MN2 and the other terminal and the bulk of the fifth NMOS transistor MN5, and the gate terminal is connected to the second boost node N2. A 6NMOS bias transistor MN6 is provided.

The first charge pumping capacitor C0 has one terminal connected to an output terminal of the first inverter I0 inverting the phase of the first control clock signal CLK0 and the other terminal connected to the first node N0. . The second charge pumping capacitor C1 has one terminal connected to the output terminal of the second inverter I1 which inverts the phase of the second control clock signal CLK1 and the other terminal connected to the first boost node N1. Connected. The third charge pumping capacitor C2 has one terminal connected to the output terminal of the third inverter I2 which inverts the phase of the third control clock signal CLK2 and the other terminal of the third boost strap node N2. Connected. The fourth charge pumping capacitor C3 is connected to the output terminal of the fourth inverter I3 which has one terminal inverting the phase of the fourth control clock signal CLK3 and the other terminal is connected to the fourth node N3. .

The boost node overvoltage protection unit 450 has one terminal connected to the first boost node N1, the other terminal and the gate terminal connected to the output terminal OUT, and the bulk of the first NMOS charge transfer transistor MN1. The seventh NMOS transistor MN7 and one terminal commonly connected to the bulk are connected to the second boost strap node N2, the other one terminal and the gate terminal are connected to the output terminal OUT, and the bulk is connected to the second NMOS charge transfer transistor MN2. Eighth NMOS transistor (MN8) commonly connected to the bulk of).

The boost strap node overvoltage protection unit 450 includes two boost strap nodes N1 and N2 when the first type two-phase cross coupled unit charge pump 400 enters a standby mode. When the voltage level VOUT is higher than | V _TN |, the high voltage applied to the boost nodes N1 and N2 is discharged through the output terminal OUT. As a result, high voltages are not applied to the plurality of transistors connected to the boost nodes N1 and N2, thereby ensuring reliability of the devices. Here, V _TP refers to the threshold voltage values of the NMOS charge transfer transistors MN1 and MN2.

FIG. 5 is a waveform diagram in steady-state of internal terminals of the first type two phase cross coupled unit charge pump illustrated in FIG. 4.

Referring to FIG. 5, a first control clock signal CLK0, a second control clock signal CLK1, a third control clock signal CLK2, and a fourth of the four control clock signals CLK0, CLK1, CLK2, and CLK3. The control clock signals CLK3 do not overlap each other, but transition between the voltage level of the ground voltage 0V and the supply voltage VCI. The first control clock signal CLK0, the third control clock signal CLK2, the second control clock signal CLK1, and the fourth control clock signal CLK3 have the same phase. The first control clock signal CLK0 and the second control clock signal CLK1 do not overlap each other in a time interval other than t3, and the third control clock signal CLK2 and the fourth control clock signal CLK3 do not overlap each other. In time intervals, they do not overlap each other. The phases of the first control clock signal CLK0, the second control clock signal CLK1, the third control clock signal CLK2, and the fourth control clock signal CLK3 are 180 ° different from each other.

Table 2 summarizes the voltage levels of the waveforms in the steady state shown in FIG.

node name node voltage t4 t1 CLK0 VCI 0 V CLK1 0 V 0 V CLK2 VCI VCI CLK3 0 V VCI VN0 0 V -VCI VN3 -VCI 0 V VN1 -VCI 0 V VN2 0 V -VCI

The voltages of the four nodes N0 to N3 are also determined according to the voltage levels of the four control clock signals CLK0, CLK1, CLK2, and CLK3. The negative voltages of the ground voltage (0V) and the power supply (VCI) are respectively determined. It has one of the voltage levels (-VCI).

Referring to Table 2, the voltages VN1 and VN2 of the two nodes N1 and N2 of the first unit charge pump are precharge control circuits 410 and 420, pumping capacitors C1 and C2 and four control clocks. The signals CLK0 to CLK3 swing between the input voltage 0V and the negative voltage level -VCI of the supply voltage VCI.

Since the first control clock signal CLK0 and the third control clock signal CLK2 have a voltage level of VCI [V] during the first t4 period shown in FIG. 5, the first node N0 and the second boost strap. The node N2 has a voltage level of 0V, and the first control node N1 and the fourth node because the second control clock signal CLK1 and the fourth control clock signal CLK3 have a voltage level of 0V. (N3) has a voltage level of -VCI.

Since the voltage level of the first node N0 connected to the gate of the first PMOS charge transfer transistor MP1 is 0V and the voltage level of the input voltage IN connected to one terminal is 0V, the first PMOS charge transfer transistor MP1 is in this period. ) Is turned off. On the contrary, since the voltage level of the fourth node N3 connected to the gate of the second PMOS charge transfer transistor MP2 is -VCI and the voltage level of the input voltage IN connected to one terminal is 0V, the second PMOS charge transfer transistor MP2 is It is turned on.

Since the voltage of the first bootstrap node N1 is -VCI and the voltage of the second bootstrap node N2 is 0V, the second NMOS charge transfer transistor MN2 is turned off and the first NMOS charge transfer transistor MN1 is turned off. When turned on, the voltage -VCI of the first boost strap node N1 is transferred to the output terminal OUT.

The voltage levels of the four control clock signals CLK0 to CLK3 during the second t1 time period shown in FIG. 5 have a voltage level opposite to that of the first t4. Since all the transistors operate on the same principle except that the phases of the control clock signals in the t1 section are opposite to the phases of the control clock signals in the t4 section, the following describes the operation of the transistors in the t1 section. Explain only about.

Referring to FIG. 5, the first bootstrap node N1 has a voltage level of 0V and the second bootstrap node N2 has a voltage level of -VCI. At this time, the voltage (-VCI) of the second boost strap node N2 pumped with -VCI is transferred to the output terminal OUT via the second NMOS charge transfer transistor MN2 turned on.

As described above, two charge pumpings occur during one cycle of the control clock signal, and the voltage VOUT of the output terminal OUT is continuously boosted by using a clock signal that switches between 0 [V] and VCI [V]. Maintains the voltage level of the VCI.

On the other hand, charge pumping occurs by the second charge pumping capacitor C1 after the first PMOS charge transfer transistor MP1 is turned off, and after the second PMOS charge transfer transistor MP2 is turned off, the third charge pumping capacitor C2 is turned off. Since charge pumping occurs, the pumped positive charge may be prevented from escaping through the first PMOS charge transfer transistor MP1 and the second PMOS charge transfer transistor MP2 which are precharging transistors, thereby increasing the pumping current.

6 is a circuit diagram of a second type two phase cross coupled unit charge pump according to the present invention.

Referring to FIG. 6, the second type 2 phase cross coupled unit charge pump 600 includes cross coupled NMOS charge transfer switches MN1 and MN2, cross coupled PMOS charge transfer switches MP1 and MP2, and a bulk bias. A supply unit 610 to 640, a plurality of charge pumping capacitors C1 and C2, a boost node precharge unit 650, and a boost node overvoltage protection unit 660 are provided.

The cross coupled PMOS charge transfer switch has two charge transfer transistors MP1 and MP2. The first PMOS charge transfer transistor MP1 connects the voltage level VIN of the input signal IN connected to one terminal to the other terminal according to the voltage level VN2 of the second boost strap node N2 applied to the gate. Switch to the first bootstrap node N1. The second PMOS charge transfer transistor MP2 connects the voltage level VIN of the input signal IN connected to one terminal to the other terminal according to the voltage level VN1 of the first boosting node N1 applied to the gate. The second NMOS charge transfer transistor MN2 switches to the second boost strap node N2.

The cross coupled NMOS charge transfer switch has two charge transfer transistors MN1 and MN2. The first NMOS charge transfer transistor MN1 outputs the voltage level VN1 of the first boost node N1 connected to one terminal according to the voltage level VN2 of the second boost node N2 applied to the gate. Switch to (OUT). The second NMOS charge transfer transistor MN2 outputs the voltage level VN2 of the second boost strap node N2 connected to one terminal according to the voltage level VN1 of the first boost strap node N1 applied to the gate. Switch to (OUT).

The bulk bias supply unit 610 to 640 may include the transistors MP1, MP2, MN1, and MN2 used as the cross coupled PMOS charge transfer switches MP1 and MP2 and the cross coupled NMOS charge transfer switches MN1 and MN2. The bias is supplied to the bulk respectively.

In the first bulk bias circuit 610, a third PMOS bias transistor MP3 and one terminal of which one terminal is connected to an input terminal IN and a voltage VN1 of the first boosting node N1 is applied to a gate thereof are formed. The first boost node N1 is connected, the other terminal and the bulk, the other terminal and the bulk of the third PMOS bias transistor MP3, and the bulk of the first PMOS charge transfer transistor MP1 are connected in common, and the input voltage ( And a fourth PMOS bias transistor MP4 to which VIN is applied.

The second bulk bias circuit 620 includes a fifth PMOS bias transistor MP5 and one terminal of which one terminal is connected to the input terminal IN and a voltage VN2 of the second boost strap node N2 is applied to the gate. The other terminal and the bulk, the other terminal and the bulk of the fifth PMOS bias transistor (MP5) and the bulk of the second PMOS charge transfer transistor (MP2) are commonly connected and the input voltage ( And a sixth PMOS bias transistor MP6 to which VIN is applied.

The third bulk bias circuit 630 has a third NMOS bias transistor MN3 and one terminal connected to the first boost strap node N1 and an output voltage VOUT applied to a gate thereof, and one terminal connected to the output terminal OUT. The other terminal and the bulk, the other terminal and the bulk of the third NMOS bias transistor MN3 and the bulk of the first NMOS charge transfer transistor MN1 are connected in common and the voltage of the first boost node N1 to the gate ( And a fourth NMOS bias transistor MN4 to which VN1 is applied.

The fourth bulk bias circuit 640 has a fifth NMOS bias transistor MN5 having one terminal connected to the second boost strap node N2 and an output voltage VOUT applied to a gate thereof, and one terminal connected to the output terminal OUT. The other terminal and the bulk, the other terminal and the bulk of the fifth NMOS bias transistor (MN5) and the bulk of the second NMOS charge transfer transistor (MN2) are commonly connected and the voltage of the second boost node (N2) to the gate ( VN2) includes a sixth NMOS bias transistor MN6.

The first charge pumping capacitor C1 is connected to the output terminal of the first inverter I1 for inverting the phase of the first control clock signal CLK1 and the other terminal is connected to the first boost node N1. The second charge pumping capacitor C2 is connected to the output terminal of the second inverter I2 which inverts the phase of the second control clock signal CLK2, and the other terminal thereof is connected to the second boost node N2.

The boost node precharge unit 650 has one terminal connected to the first boost node N1, an input terminal IN connected to the other terminal and the gate terminal, and a bulk of the first NMOS charge transfer transistor MN1. The first precharge transistor MN7 and one terminal commonly connected to the bulk are connected to the second boost strap node N2, the input terminal IN is connected to the other one terminal and the gate terminal, and the bulk is the second NMOS charge transfer transistor. A second precharge transistor MN8 is commonly connected to the bulk of the MN2.

The boost node overvoltage protection unit 660 has one terminal connected to the first boost node N1, the other terminal and the gate terminal connected to the output terminal OUT, and the bulk of the first NMOS charge transfer transistor MN1. The first overvoltage protection transistor MN7 and one terminal commonly connected to the bulk are connected to the second boost strap node N2, the other one terminal and the gate terminal are connected to the output terminal OUT, and the bulk is the second NMOS charge transfer transistor. The second overvoltage prevention transistor MN8 is commonly connected to the bulk of the MN2.

FIG. 7 is a waveform diagram in a steady state of internal nodes of the second type two phase cross coupled unit charge pump illustrated in FIG. 6.

Referring to FIG. 7, the first control clock signal CLK1 and the second control clock signal CLK2 have voltage levels of 0 V [V] and VCI [V], respectively, during the first time period t4. At this time, the voltage levels of the first and second strap nodes N1 and N2 are VIN-VCI and VIN, respectively.

Therefore, when VIN is 0 [V], 0V is applied to one terminal connected to the input terminal IN, but since VCI is applied to the gate, the first PMOS charge transfer transistor MP1 is turned off and the input terminal IN is turned on. 0V is applied to one terminal connected to the second PMOS charge transfer transistor MP2 to which VIN-VCI [V], that is, -VCI [V] is applied to the gate. Since the second control clock signal CLK2 applied to one terminal of the second charge pumping capacitor C2 is VCI [V], the charge corresponding to the voltage 0 [V] applied from the input terminal IN is pumped on the second charge. The voltage of the second boost strap node N2 constituting the other terminal of the capacitor C2 is precharged to 0 [V].

As the voltage level of the first control clock signal CLK1 becomes 0 [V], the first boost strap node N1 is boosted to the voltage of -VCI [V]. The first NMOS charge transfer transistor MN1 whose one terminal has a voltage level of -VCI and 0 [V] is applied to the gate is turned on, and one terminal has a voltage level of 0 [V] and -VCI is applied to the gate. The second NMOS charge transfer transistor MN2 is turned off. Therefore, the -VCI voltage of the first boost node N1 is transferred to the output terminal OUT via the first NMOS charge transfer transistor MN1.

During the time interval indicated by the second t1, the first boost strap N ... has a voltage level of 0 [V] and the second boost node N2 has a VIN-VCI [V], that is, a -VCIì ~~ voltage level. In this case, the first NMOS charge transfer transistor MN1 is turned off and the second NMOS charge transfer transistor MN2 is turned on. Therefore, the pumped charge of the second boost strap node N2 is transferred to the output terminal OUT through the second NMOS charge transfer transistor MN2.

The above operation can be easily understood by referring to the description of the operation of the unit charge pump illustrated in FIG. 4, and thus a detailed description thereof will be omitted.

Since the operation and effect of the boost node overvoltage protection unit 660 has already been described in the description of the boost node overvoltage protection unit 450 of the unit charge pump illustrated in FIG. 4, the boost node precharge unit 650 will be described below. ) Operation and effects will be described.

During the initial operation of the unit charge pump 600 circuit, the first boost node N1 and the second boost node N2 are (VIN + V _TP ) [V] by the boost node precharge unit 650. Precharged to Here, V _TP means threshold voltages of the PMOS charge transfer transistors MP1 and MP2. Since one terminal and the gate terminal of the two precharge MOS transistors MP7 and MP8 constituting the boost node precharge unit 650 are connected to the input terminal IN to which the input voltage VIN is applied, The first boost strap node N1 and the second boost strap node N2 connected to the other terminals of the precharge morph transistors MP7 and MP8 are respectively precharged (VIN + V _TP ) [V] and have a constant short moment. After this, the voltage values of the two nodes operate symmetrically with each other.

Here, the two control clock signals CLK1 and CLK2 generally use non-overlap signals, but they may be overlapped.

FIG. 8 shows the voltage of the boost strap node of the second type two phase cross coupled unit charge pump according to the present invention shown in FIG. 6.

Referring to FIG. 8, in the case of the second type two-phase cross coupled unit charge pump according to the present invention, the first bootstrap node N1 and the second portion are formed by the action of the boost node precharge unit 650 embedded therein. It can be seen that the voltages of the strap nodes N2 shift symmetrically with each other.

FIG. 9 illustrates the voltage of the boost strap node in the standby mode of the second type two phase cross coupled unit charge pump according to the present invention shown in FIG. 6.

Referring to FIG. 9, when the unit charge pump enters the standby mode in a normal state, a conventional cross-coupled charge pump has a high voltage applied between the output terminal and the pumping node for a predetermined time (about 0.3 ms). Type 2 two-phase cross-coupled unit charge pump (Proposed) according to | V _TN | It can be seen that the voltages N1 and N2 of the pumping node follow the output voltage VOUT with the voltage difference of the degree.

In the above description, the technical idea of the present invention has been described with the accompanying drawings, which illustrate exemplary embodiments of the present invention by way of example and do not limit the present invention. In addition, it is apparent that any person having ordinary knowledge in the technical field to which the present invention belongs may make various modifications and imitations without departing from the scope of the technical idea of the present invention.

1 is an example of a conventional two-phase cross coupled unit charge pump circuit diagram.

2 is another example of a conventional two-phase cross coupled unit charge pump circuit diagram.

3 shows voltage waveforms of the boost straps N1 and N2 with time.

4 is a circuit diagram of a first type two phase cross coupled unit charge pump according to the present invention.

FIG. 5 is a waveform diagram in steady-state of internal terminals of the first type two phase cross coupled unit charge pump illustrated in FIG. 4.

6 is a circuit diagram of a second type two phase cross coupled unit charge pump according to the present invention.

FIG. 7 is a waveform diagram in a steady state of internal nodes of the second type two phase cross coupled unit charge pump illustrated in FIG. 6.

FIG. 8 shows the voltage of the boost strap node of the second type two phase cross coupled unit charge pump according to the present invention shown in FIG. 6.

FIG. 9 illustrates the voltage of the boost strap node in the standby mode of the second type two phase cross coupled unit charge pump according to the present invention shown in FIG. 6.

Claims (8)

A first PMOS charge transfer transistor MP1 for switching the input voltage VIN applied from the input terminal IN to the first boost node N1; A second PMOS charge transfer transistor (MP2) for switching the input voltage (VIN) to a second boost strap node (N2); A first NMOS charge transfer transistor (MN1) for switching the voltage of the first boost strap node to an output terminal (OUT); A second NMOS charge transfer transistor (MN2) for switching the voltage of the second boost strap node to the output terminal (OUT); A precharge control unit (410, 420) for applying a precharge control signal to the gates of the first PMOS charge transfer transistor and the second PMOS charge transfer transistor; A bulk bias supply unit (430, 440) for supplying a first bulk bias to the bulk of the first NMOS charge transfer transistor and a second bulk bias to the bulk of the second NMOS charge transfer transistor; A pumping charge storage unit configured to store charges pumped to the gate terminals of the first PMOS charge transfer transistor and the second PMOS charge transfer transistor, the first boost node and the second boost node in response to a plurality of control clock signals ( C0 to C3); And A boost strap node overvoltage protection unit 450 having one terminal connected to the first bootstrap node and the other terminal connected to the second bootstrap node; The unit charge pump of claim 1, wherein the gates of the first NMOS charge transfer transistor and the second NMOS charge transfer transistor are cross-coupled. The method of claim 1, wherein the precharge control unit (410, 420), A first precharge control circuit 410 for applying a first precharge control signal VN0 to a gate of the first PMOS charge transfer transistor; And A second precharge control circuit 420 for applying a second precharge control signal VN3 to the gate of the second PMOS charge transfer transistor; The first precharge control circuit 410, A third PMOS precharge transistor (MP3) for applying the input voltage to one terminal, the gate terminal, and the bulk and generating the first precharge control signal to the other terminal; And A fourth PMOS precharge transistor (MP4) configured to apply the input voltage to one terminal and the bulk, the second precharge control signal to a gate, and generate the first precharge control signal to the other terminal; The second precharge control circuit 420, A fifth PMOS precharge transistor (MP5) for applying the input voltage to one terminal and the bulk, the first precharge control signal to a gate, and generating the second precharge control signal to the other terminal; And And a sixth PMOS precharge transistor (MP6) for applying the input voltage to one terminal, the gate terminal, and the bulk and generating the second precharge control signal to the other terminal. The method of claim 1, wherein the boost node overvoltage protection unit 450, A first NMOS overvoltage protection transistor (MN7) having one terminal connected to the first boost node (N1), the other terminal and gate connected to the output terminal, and the first bulk bias applied to a bulk; And And a second NMOS overvoltage protection transistor MN8 having one terminal connected to the second boost strap node N2, the other terminal and gate connected to the output terminal, and the second bulk bias applied to a bulk. Unit charge pump. The method of claim 1, wherein the pumped charge storage unit (C0 ~ C3), A first pumping capacitor C0 having a first control clock signal CLK0 applied to one terminal and the other terminal connected to a gate of the first PMOS charge transfer transistor; A second pumping capacitor C1 having a second control clock signal CLK1 applied to one terminal and the other terminal connected to the first boost strap node; A third pumping capacitor C2 having a third control clock signal CLK2 applied to one terminal and the other terminal connected to the second boost strap node; And And a fourth pumping capacitor (C3) having a fourth control clock signal (CLK3) applied to one terminal and the other terminal connected to a gate of the second PMOS charge transfer transistor. A first PMOS charge transfer transistor MP1 for switching the input voltage VIN applied from the input terminal IN to the first boost node N1; A second PMOS charge transfer transistor (MP2) for switching the input voltage (VIN) to a second boost strap node (N2); A first NMOS charge transfer transistor (MN1) for switching the voltage of the first boost strap node to an output terminal (OUT); A second NMOS charge transfer transistor (MN2) for switching the voltage of the second boost strap node to the output terminal (OUT); A first bulk bias, a second bulk bias, a third bulk bias, and a fourth bulk bias for the bulk of the first PMOS charge transfer transistor, the second PMOS charge transfer transistor, the first NMOS charge transfer transistor, and the second NMOS charge transfer transistor, respectively. Bulk bias supply unit for supplying each (610 ~ 640); A pumping charge storage unit (C1, C2) for storing charges pumped to the first boosting node and the second boosting node in response to a plurality of control clock signals; A boost node precharge unit (650) having one terminal connected to the first boost strap node and the other terminal connected to a second boost strap node; And A boost strap node overvoltage protection unit 660 having one terminal connected to the first bootstrap node and the other terminal connected to the second bootstrap node; The gate of the first PMOS charge transfer transistor and the second PMOS charge transfer transistor is cross-coupled, the unit charge pump, characterized in that the gate of the first NMOS charge transfer transistor and the second NMOS charge transfer transistor is also cross-coupled. The method of claim 5, wherein the boost node precharge unit 650, A first PMOS precharge transistor (MP7) having one terminal connected to the first boost strap node (N1), the other terminal and gate connected to the input terminal (IN), and the first bulk bias applied to a bulk; And And a second PMOS precharge transistor MP8 to which one terminal is connected to the second boost strap node N2, the other terminal and gate are connected to the input terminal, and the second bulk bias is applied to the bulk. Unit charge pump. The method of claim 5, wherein the boost node overvoltage protection unit 660, A first NMOS overvoltage prevention transistor (MN7) having one terminal connected to the first boost strap node (N1), the other terminal and gate connected to the output terminal (OUT), and the third bulk bias applied to a bulk; And And a second NMOS overvoltage protection transistor MN8 having one terminal connected to the second boost strap node N2, the other terminal and gate connected to the input terminal, and the fourth bulk bias applied to the bulk. Unit charge pump. The method of claim 7, wherein the pumped charge storage unit (C1, C2), A first pumping capacitor C1 having a first control clock signal CLK1 applied to one terminal and the other terminal connected to the first boost strap node N1; And And a second pumping capacitor (C2) having a second control clock signal (CLK2) applied to one terminal and the other terminal connected to the second boost strap node (N2).

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