KR100452636B1 - Clock generator for semiconductor memory device, which improves pumping efficiency by increasing switching width of clock - Google Patents

Abstract

PURPOSE: A clock generator is provided to achieve improved pumping efficiency by increasing the swing width of a clock required for a charge pump. CONSTITUTION: A clock generator comprises a capacitor(C), and first to third units. The capacitor has a terminal connected to an output terminal, and the other terminal for receiving a third clock signal. The first unit charges power voltages to the capacitor in accordance with the first and second clock signals. The second unit raises the potential of the output terminal to the double power voltage in accordance with the third clock signal supplied to the capacitor. The second unit drops the potential of the output terminal by the amount of shifted voltage, when the third clock signal is shifted from a high state to a low state. The third unit discharges the voltage charged in the capacitor in accordance with the second clock delayed over a predetermined time.

Description

Clock Generators for Semiconductor Memory Devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generator for a semiconductor memory device, and more particularly, to a clock generator for a semiconductor memory device capable of improving pumping efficiency by increasing a swing width of a clock required for a charge pump.

Conventional clock generators with boost traps have a maximum swing width of 2V _cc , which limits pumping efficiency, especially in low voltage pump circuits. I need a clock.

Accordingly, an object of the present invention is to provide a clock generator for a semiconductor memory device capable of improving pumping efficiency by increasing a swing width of a clock.

According to the present invention for achieving the above object, a terminal is connected to an output terminal, and the other terminal is configured to receive a third clock signal, and a first voltage for occupying a power supply voltage to the capacitor according to the first and second clock signals. Means and raises the potential of the output terminal to a double power supply voltage in accordance with the third clock signal supplied to the capacitor, the voltage amount being transitioned when the third clock signal transitions from a high state to a low state. And a second means for lowering the potential of the output terminal and a third means for discharging the voltage occupied by the capacitor according to the second clock signal delayed for a predetermined time.

1 is a circuit diagram of a clock generator for a semiconductor memory device according to the present invention.

2 is a timing diagram of respective signals for driving a clock generator for a semiconductor memory device according to the present invention.

<Description of the symbols for the main parts of the drawings>

P1: first PMOS transistor P2: second PMOS transistor

P3: third PMOS transistor P4: fourth PMOS transistor

P5: fifth PMOS transistor N1: first NMOS transistor

N2: second NMOS transistor N3: third NMOS transistor

I1: first inverter I2: second inverter

I3: third inverter C: capacitor

K1: first node K2: second node

The present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram of a clock generator for a semiconductor memory device according to the present invention, and FIG. 2 is a timing diagram of respective signals for driving the same.

The clocks used in the present invention operate with the period shown in FIG. 2. In the initial state, the voltage of the well is subtracted from the power supply voltage by the first NMOS transistor N1 having a diode form (V _cc −). V _t ), and the junction of each PMOS transistor maintains the level below the well voltage, so that the pn junction is reverse biased and there is no charge transfer to the outside.

In this state, the clock signal is applied to drive the circuit. First, the circuit driving during the T1 time will be described.

The second NMOS transistor N2 is turned on by the first clock signal (hereinafter referred to as "CLK1") transitioned to the HIGH state. The well voltage is turned to the ground level by the inverted signal of the first clock signal inverted to the LOW state through the second inverter I2 (hereinafter referred to as “CLK1b”) to turn on the second PMOS transistor P2. . At this time, the third PMOS transistor P3 is turned off by the second clock signal (hereinafter referred to as "CLK2") transitioned to the high state, and is inverted to the low state through the third inverter I3 through the delay means. The third NMOS transistor N3 is turned off by the delay inversion signal of the two clock signals (hereinafter referred to as "DCLK2b"). The first clock signal (hereinafter referred to as "CLK3") is inverted by the inverted signal (hereinafter referred to as "CLK3b") of the third clock signal which is inverted to the high state through the first inverter I1 (hereinafter referred to as "CLK3b"). Since the PMOS transistor P1 and the fifth PMOS transistor P5 are turned off, the fourth PMOS transistor P4 is also turned off. Accordingly, the power supply voltage V _cc is supplied through the second PMOS transistor P2 to charge the capacitor C, and the potential of the first node K1 becomes high.

The circuit driving during the T2 time is explained as follows.

The second NMOS transistor N2 is turned off by the CLK1 transitioned to the low state, and the third PMOS transistor P3 is turned on by the CLK2 transitioned to the low state. The third NMOS transistor N3 is turned on by the high state DCLK2b in which the low state CLK2 passes through the delay means and is inverted through the third inverter I3. In addition, the first PMOS transistor P1 and the fifth PMOS transistor P5 are turned off by the high state CLK3b in which the low state CLK3 is inverted through the first inverter I1. Therefore, since the charges occupied in the capacitor C are applied to the gate of the second PMOS transistor P2 through the turned-on third PMOS transistor P3, the second PMOS transistor P2 is turned off, and the well voltage is reduced. The power supply voltage V _cc is the same as that of the first node K1.

The circuit driving during the T3 time is explained as follows.

The second NMOS transistor N2 is turned off by the CLK1 in the low state, the third PMOS transistor P3 is turned off by the CLK2 in the high state, and the second PMOS transistor P2 is turned on. The third NMOS transistor N3 is turned off by the DCLK2b in which the high state CLK2 passes through the delay means and is inverted to the low state through the third inverter means I3. On the other hand, the voltage of the first node (K1), which maintained to V _cc by a transition to a high state CLK3 are raised by V _cc + ΔV. Since the value of ΔV is determined by the coupling ratio of the capacitor C at the first node K1, the maximum voltage of the first node K1 is increased to 2V _cc and thus the capacitor ( C) is also accounted for 2V _cc .

The operation so far is described in more detail as follows. Well voltage of the ground level by the CLK1 at time T1 is the CLK1 is held by the V _cc to claim 3 PMOS transistor (P3), while transitions to the low state at time T2. Thus, when CLK3 transitions to the high state at the time T3 in the state of being precharged to V _cc , the voltage of the first node K1 increases to 2 V _cc , and the well voltage is connected to the pn junction of the first PMOS transistor P1. As a result, the voltage rises to 2V _cc like the first node K1. Meanwhile, gates of the second PMOS transistor P2, the third PMOS transistor P3, and the fourth PMOS transistor P4 having a junction portion connected to the first node K1 have the same voltage as that of the first node K1, that is, 2V. _cc is applied to maintain the voltage of the first node K1 at 2V _cc .

The circuit driving during the T4 time is explained as follows.

Since the DCLK2b, the delay signal of CLK2, transitions to the high state, the third NMOS transistor N3 is turned on to form a pass to ground. Therefore, the fourth PMOS transistor P4 is turned on by the second node K2 transitioned to the low state. Since the path is formed to the ground by the turned-on fourth PMOS transistor P4, the voltage of 2V _cc held by the first node K1 is discharged to be low. On the other hand, the well voltage is maintained at V _cc .

The circuit driving during the T5 time is explained as follows.

As the delay signal DCLK2b of CLK2 transitions to the low state and the CLK3 transitions from the high state to the low state, the potential of the first node K1 drops by the amount of CLK3 transition to -V _cc + V _tp . At this time, the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, and the fourth PMOS transistor P4 are all turned off, and the voltage of the first node K1 is -V _cc +. Is maintained at V _tp . On the other hand, the well voltage is maintained at V _cc .

By repeating this series of cycles, the voltage of the first node K1 swings from -V _cc + V _tp to 2V _cc , thus having a swing width of up to 3V _cc -V _tp .

On the other hand, no path is formed to another ground, and the potentials of the first NMOS transistor N1 and the first node K1 in the form of diodes for maintaining the voltage at the well node at the V _cc -V _t level are always V _cc −. If it is higher than V _t , the nature of the pn junction allows the first PMOS transistor P1 to automatically follow the high voltage without the need for another control signal.

As described above, according to the present invention, a clock larger than the conventional clock width can be used as an input clock, thereby increasing the efficiency of the pump and preventing the efficiency of the low voltage pump from being lowered.

Claims (4)

A terminal connected to the output terminal and the other terminal for receiving a third clock signal; First means for occupying a power supply voltage in said capacitor in accordance with first and second clock signals; A potential of the output terminal is increased to a power voltage of twice according to the third clock signal supplied to the capacitor, and the potential of the output terminal is increased by an amount of voltage that is transitioned when the third clock signal transitions from a high state to a low state Second means for lowering And third means for discharging the voltage occupied by said capacitor in response to said second clock signal delayed for a predetermined time. 2. The apparatus of claim 1, wherein the first means comprises: a first NMOS transistor turned on in response to a first clock signal; A first PMOS transistor turned on according to a second clock signal; And a second PMOS transistor which is turned on in response to an inversion signal of the first clock signal from the turned on first NMOS transistor to occupy a power supply voltage in the capacitor. The semiconductor device of claim 1, wherein the second means comprises: an NMOS transistor in the form of a diode for maintaining a voltage at a well node at a power supply voltage level; And a PMOS transistor which is turned on according to the inverted signal of the third clock signal and maintains the well voltage at a high voltage regardless of the third clock signal when the potential of the output terminal is higher than the power supply voltage level. Clock generator. The first NMOS transistor of claim 1, wherein the third means comprises: a first NMOS transistor turned on according to an inverted signal of a second clock signal delayed for a predetermined time and forming a path to ground; A first PMOS transistor turned on according to an inverted signal of the third clock signal; And a second PMOS transistor connected between the first NMOS transistor and the first PMOS transistor, the second PMOS transistor being turned on according to the potential therebetween to reduce the potential of the output terminal to the ground level. .

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