KR19990060848A - Clock generator for semiconductor memory devices - Google Patents

Abstract

The present invention relates to a clock generator for a semiconductor memory device.

Conventionally, a clock generator using a boostrap has a swing width of a maximum of 2V _cc , which limits the pumping efficiency. In particular, a low-voltage pump requires a clock having a higher swing width than a conventional clock.

In the present invention, the swing width of the clock is increased up to 3V _cc -V _t to be used as the input of the pump, thereby increasing the efficiency of the pump and preventing the efficiency of the low-voltage pump from being lowered.

Description

Clock generator for semiconductor memory devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generator for a semiconductor memory device, and more particularly, to a clock generator for a semiconductor memory device capable of increasing swing width of a clock required for a charge pump to improve pumping efficiency.

Conventional clock generators using boostrap have limited pumping efficiency because the swing width of the clock is 2V _{cc at} maximum. Especially, in the pump circuit for low voltage, the swing width is higher than that of the conventional clock I need a clock.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a clock generator for a semiconductor memory device capable of increasing the swing width of a clock to improve the pumping efficiency.

According to an aspect of the present invention, there is provided a method of driving a plasma display panel including a capacitor having one terminal connected to an output terminal and the other terminal receiving a third clock signal, And a third clock signal supplied to the capacitor to increase the potential of the output terminal to a power supply voltage twice that of the first clock signal and to increase the potential of the output terminal by a voltage amount that is changed when the third clock signal transitions from a high state to a low state, And a third means for discharging the voltage charged in the capacitor in accordance with the second clock signal delayed by a predetermined time.

1 is a circuit diagram of a clock generator for a semiconductor memory device according to the present invention.

2 is a timing diagram of signals for driving a clock generator for a semiconductor memory device according to the present invention.

DESCRIPTION OF THE DRAWINGS FIG.

P1: first PMOS transistor P2: second PMOS transistor

P3: third PMOS transistor P4: fourth PMOS transistor

P5: fifth PMOS transistor N1: first NMOS transistor

N2: second NMOS transistor N3: third NMOS transistor

I1: First inverter I2: Second inverter

I3: Third inverter C: Capacitor

K1: first node K2: second node

The present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram of a clock generator for a semiconductor memory device according to the present invention, and FIG. 2 is a timing diagram of respective signals for driving the clock generator.

The clocks used in the present invention operate with the period shown in FIG. 2. In the initial state, the voltage of the well is decreased by the first NMOS transistor N1 having the diode shape (V _cc - V _t ). At this time, since the junction of each PMOS transistor maintains a level equal to or lower than the well voltage, reverse bias of the pn junction is applied, so that charge transfer to the outside is prevented.

In this state, a clock signal is applied to drive the circuit. First, the circuit operation during the T1 time will be described.

The second NMOS transistor N2 is turned on by the first clock signal (hereinafter referred to as CLK1) which transited to the HIGH state. The well voltage becomes the ground level by the inverted signal of the first clock signal inverted to the LOW state through the second inverter I2 (hereinafter referred to as CLK1b), and the second PMOS transistor P2 is turned on. At this time, the third PMOS transistor P3 is turned off by the second clock signal (hereinafter referred to as CLK2) which has transitioned to the high state, and the second clock signal, which is inverted to the low state through the third inverter I3, The third NMOS transistor N3 is turned off by the delay inversion signal of the signal (hereinafter referred to as DCLK2b). The third clock signal CLK3 is supplied to the first PMOS transistor P1 (hereinafter, referred to as " CLK3b ") by the inverted signal of the third clock signal inverted to the high level through the first inverter I1 And the fifth PMOS transistor P5 are turned off, so that the fourth PMOS transistor P4 is also turned off. Accordingly, the second voltage supply source through the PMOS transistor (P2) is the power supply voltage (V _cc) charge the capacitor (C) (charge) and a first node (K1) is in a high state.

Circuit operation during T2 time will be described as follows.

The second NMOS transistor N2 is turned off by the CLK1 transitioned to the low state and the third PMOS transistor P3 is turned on by the CLK2 transitioned to the low state. The third NMOS transistor N3 is turned on by the high level DCLK2b whose CLK2 in the low state passes through the delay means and inverted through the third inverter I3. In addition, the first PMOS transistor P1 and the fifth PMOS transistor P5 are turned off by the high-level CLK3b in which the CLK3 in the low state is inverted through the first inverter I1. Therefore, since the charge stored in the capacitor C is applied to the gate of the second PMOS transistor P2 through the turned-on third PMOS transistor P3, the second PMOS transistor P2 is turned off, the first node is a supply voltage (V _cc) level, such as (K1).

Circuit operation during T3 time will be described as follows.

The second NMOS transistor N2 is turned off by the CLK1 in the low state and the third PMOS transistor P3 is turned off by the CLK2 in the high state to turn on the second PMOS transistor P2. CLK2 in the high state passes through the delay means and the third NMOS transistor N3 is turned off by the DCLK2b inverted to the low state through the third inverter means I3. On the other hand, the voltage of the first node (K1), which maintained to V _cc by a transition to a high state CLK3 are raised by V _cc + ΔV. Since the value of DELTA V is a value determined by the coupling ratio by the capacitor C at the first node K1, the maximum voltage of the first node K1 rises to 2V _cc , C) is also occupied by 2V _cc .

The operation up to this point will be described in more detail as follows. Well voltage of the ground level by the CLK1 at time T1 is the CLK1 is held by the V _cc to claim 3 PMOS transistor (P3), while transitions to the low state at time T2. In this state, the state in which the precharge to V _cc to the T3 time CLK3 is transitions to a high state the voltage of the first node (K1), and rises up to 2V _cc, well voltage to the pn junction of the first PMOS transistor (P1) The voltage of the first node K1 rises to 2V _cc . The gates of the second PMOS transistor P2, the third PMOS transistor P3 and the fourth PMOS transistor P4 to which the junction is connected to the first node K1 are connected to the same voltage as the first node Kl, _cc is applied and the voltage of the first node K1 is maintained at 2V _cc .

Circuit operation during T4 time will be described as follows.

Since the delay signal DCLK2b of CLK2 transitions to a high state, the third NMOS transistor N3 is turned on and a path is formed to the ground. Therefore, the fourth PMOS transistor P4 is turned on by the second node K2 that has transitioned to the low state. Since the path is formed to the ground by the fourth PMOS transistor P4 turned on, the voltage of 2V _cc that the first node K1 maintains is discharged and becomes a low state. On the other hand, the well voltage is held at V _cc.

Circuit operation during T5 time will be described as follows.

The potential of the first node K1 falls to -V _cc + V _tp by the amount of the CLK3 transition as the delay signal DCLK2b of the CLK2 transits to the low state and the signal CLK3 transitions from the high state to the low state. At this time, the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3 and the fourth PMOS transistor P4 are all turned off so that the voltage of the first node K1 becomes -V _cc + V _tp . On the other hand, the well voltage is held at V _cc.

The voltage of the first node K1 swings from -V _cc + V _tp to 2V _cc while repeating this series of cycles, so that it has a swing width of 3V _cc -V _tp .

On the other hand, the potential of the diode of the first NMOS transistor (N1) and the first node (K1) for not pass is formed of a different ground, holding the voltage at the node is always well to V _cc -V _t level V _cc - is higher than V _t, the store allows claim 1 PMOS transistor (P1) by the nature of the pn junction along the high-voltage automatically without the need for other control signals.

As described above, according to the present invention, since a clock greater than the conventional clock width can be used as the input clock, the efficiency of the pump can be increased and the efficiency of the low voltage pump can be prevented from being lowered.

Claims (4)

One terminal connected to the output terminal and the other terminal connected to the third clock signal, First means for charging the power supply voltage to the capacitor in accordance with the first and second clock signals, A third clock signal supplied to the capacitor to increase the potential of the output terminal to a power source voltage twice that of the third clock signal, A second means for lowering the temperature, And a third means for discharging the voltage charged in the capacitor according to the second clock signal delayed by a predetermined time. 2. The semiconductor memory device according to claim 1, wherein the first means comprises: a first NMOS transistor which is turned on according to a first clock signal; A first PMOS transistor that is turned on in response to a second clock signal, And a second PMOS transistor that is turned on in response to an inverted signal of the first clock signal from the first NMOS transistor and charges the capacitor with a power supply voltage. 2. The semiconductor device according to claim 1, wherein the second means comprises: a diode-type NMOS transistor for maintaining a voltage of a well node at a power supply voltage level; And a PMOS transistor which is turned on in response to the inverted signal of the third clock signal and maintains the well voltage at a high voltage regardless of the third clock signal when the potential of the output terminal is higher than the power supply voltage level. Clock generator. 2. The semiconductor memory device according to claim 1, wherein the third means comprises: a first NMOS transistor which is turned on according to an inverted signal of a second clock signal delayed by a predetermined time to form a path to ground; A first PMOS transistor which is turned on in response to an inverted signal of the third clock signal, And a second PMOS transistor connected between the first NMOS transistor and the first PMOS transistor and being turned on according to a potential between the first and second PMOS transistors to reduce the potential of the output terminal to a ground level. .