KR100203867B1 - Signal delay circuit using charge pump circuit - Google Patents

Abstract

1. the technical field to which the invention described in the claims belongs;

A signal delay circuit using a charge pump is provided.

2. The technical problem to be solved by the invention;

The present invention provides a signal delay circuit using a charge pump circuit for delaying an input signal by a predetermined period and providing a stable output signal.

3. Summary of the Solution of the Invention;

A signal delay circuit using a charge pump circuit; A delay unit for delaying the input clock signal by a preset frequency corresponding to the control signal; A delay detecting unit detecting a signal delay of the delay unit; A charge pump unit for feeding back the DC voltage to the delay unit; The present invention also includes a current fixing circuit unit for providing a current having a fixed current value in the charge pump unit.

4. Significant use of the invention;

A signal delay circuit using a charge pump circuit is provided.

Description

Signal delay circuit using charge pump circuit

1 is a block diagram of a signal delay circuit having a charge pump circuit according to the prior art.

FIG. 2 is a detailed circuit diagram of FIG.

3 is the timing of FIG.

4 is a simulation diagram of FIG.

5 is a block diagram of a signal delay circuit having a charge pump circuit according to the present invention.

FIG. 6 is a detailed circuit diagram of FIG.

7 is the timing of FIG.

FIG. 8 is a simulation diagram of FIG.

The present invention relates to a signal delay circuit using a charge pump circuit, and more particularly, to a signal delay circuit using a charge pump circuit for delaying an input signal by a predetermined period and providing a stable output signal.

In general, a signal delay circuit for delaying an input clock signal by a predetermined period includes a multiplier and a voltage controlled oscillator in a semiconductor integrated circuit. In this case, the frequency converter outputs a clock signal having a frequency twice the input clock signal, and the voltage bare oscillator outputs a clock signal having a different frequency according to a control voltage. Typically, the above-described conventional signal delay circuits using devices such as resistors, capacitors and inverters vary with the process parameters and ambient temperature of the manufacturing stage. Therefore, in the conventional signal delay circuit, the signal delay amout is not uniform, and the width of the high or low level period is changed.

A circuit for solving this problem is described in detail in U.S. Patent No. 5,059,838, signal delay circuit using charge pump circuit, issued August 22, 1991. Applicant will describe the prior art of the present invention based on the above-mentioned citations.

1 is a block diagram of a signal delay circuit having a charge pump circuit according to an embodiment of the prior art. Referring to FIG. 1, the delay circuit 2 receives an input clock signal having a preset frequency and delays the input clock signal for a predetermined time. At this time, the delay time of the delay circuit 2 is fixed by the control signal to be described below. The delay detecting circuit 4 receives an output signal delayed by the delay circuit 2, or sometimes directly receives the input clock signal to detect a delay time according to the input clock signal. The charge pump circuit 6 receives the signal sensed by the delay detection circuit 4 and the input clock signal and charges as much as a predetermined capacitor for one pulse period of the input clock signal. By discharging one pulse period of the sensing signal output from (4) by a predetermined capacitor, the charge or discharge degree of the capacitor is matched with each other. At this time, the charge pump circuit 6 generates the control signal and fixes the delay time of the delay circuit 2 according to the ratio of the discharged power supply to the charged power supply current. The generated control signal is provided to the delay circuit 2 via the low pass filter circuit 8 when necessary.

FIG. 2 is a detailed circuit diagram of FIG. Referring to FIG. 2, the delay circuit 2, the delay sensing circuit 4, the charge pump circuit 6, the reference current fixing circuit 7, and the low pass filter circuit 8 include a plurality of PMOS transistors. , Enmos transistor, inverter, NAND gate and capacitor.

The reference current fixing circuit 7 is fixed in accordance with the current values of inflow and outflow current for the capacitor, which will be described later in the charge pump circuit 6. The reference current fixing circuit 7 has a configuration in which the PMOS transistor 50, the resistor 53 and the enMOS transistor 52 are connected in series between the power supply voltage VCC and the ground voltage VSS. A gate and a drain are commonly connected to the PMOS transistor 50, and a gate and a drain are also commonly connected to the NMOS transistor 52. In such a circuit, when the reference current flows through the PMOS transistor 50, the resistor 53, and the NMOS transistor 52, in order to reduce the current value charged or discharged in the charge pump circuit 6; The value of the resistor 53 is fixed higher than the turn-on resistance values of the PMOS transistor 50 and the NMOS transistor 52. Thus, the value of the reference current is determined by the resistor 53. The reference current is provided to the charge pump circuit 6 at a common connection point between the gate and the drain of the PMOS transistor 50 and the NMOS transistor 52 of the reference current fixing circuit 7.

In the charge pump circuit 6, the PMOS transistors 54 and 56 are connected in series between the power supply voltage and the output line 9. A channel of the enMOS transistors 58 and 60 is connected in series between the output line 9 and the ground voltage. The capacitor 62 constituting the drain capacitance of the PMOS transistor 56 and the NMOS transistor 58 is connected to the output line 9. The gates of the PMOS transistor 54 and the NMOS transistor 60 respectively receive the reference currents from the reference current fixing circuit 7.

Meanwhile, an input clock signal having a preset frequency is provided to the gate of the PMOS transistor 58, and an output signal of the delay detection circuit 4 is provided to the gate of the NMOS transistor 58. The PMOS transistor 54 forms a current mirror with the PMOS transistor 50 of the reference current fixing circuit 7, and the current flowing through the PMOS transistor 54 of the charge pump circuit 6 It is determined based on the value of the reference current, and is also determined as the size ratio between the PMOS transistors 50 and 54. The NMOS transistor 60 and the NMOS transistor 52 form a current mirror and are determined based on the value of the reference current flowing through the NMOS transistor 60. In addition, the NMOS transistors 54 and 56 charge the charge of the capacitor 62. While the PMOS transistor 56 is held based on the input clock signal, the capacitor 62 is charged by a current having a value preset by the PMOS transistor 54. The two PMOS transistors 58 and 60 discharge the charge of the capacitor 62. The capacitor 62 is discharged by a current having a value preset by the enmos transistor 60 while the enMOS transistor 58 is held based on the output signal of the delay sensing circuit 4.

The low pass filter circuit 8 composed of the resistor 64 and the capacitor 66 obtains the DC voltage by relaxing the terminal voltage of the capacitor 62 of the charge pump circuit 6. If the value of the capacitor 62 is large enough, the capacitor 66 and the resistor 64 of the low pass filter circuit 8 are not necessary. The output signal of the low pass filter circuit 8 is provided to the delay circuit 2.

The delay circuit 2 is formed by a cascade junction of a first delay end, a second delay end, and a third delay end including the PMOS transistors 10 and 14 and the inverters 12 and 14. At the output node 72 of the delay circuit 2, a NAND gate 36 for receiving the output of the inverter 34 and an input clock signal and an inverter 38 for inverting the output signal of the NAND gate 36 are provided. Connected. An input clock signal is provided to the first delay end, and the signals output from the first delay end and the second delay end are provided to a third delay end that follows as an input signal. The signal output from the third delay stage is output to the output clock terminal through the inverter 34, the NAND gate 36, and the inverter 38.

The delay detection circuit 4 is an inverter 40, 46, 48 for inverting the output signals of the first and second delay stages, and a NAND gate 42 for receiving an output signal of the inverters 40, 48. And an inverter 44 for inverting the output signal of the NAND gate 42.

3 is a timing diagram according to FIG. 1. Referring to FIG. 3, timing diagrams are shown for the input signal clock, node 68, node 70, node 72, node 74 and output clock.

4 is a simulation diagram of FIG. Referring to FIG. 4, the clock change of the charge pump circuit 6 is shown when the power supply voltage VDD changes.

In the signal delay circuit using the conventional charge pump having the structure as described above, the PMOS transistor 50 and the charge pump circuit 6 of the reference current fixing circuit 7 connected to the charge pump circuit 6 The pumping capability is represented by the word line ratio of the PMOS transistor 54 and the word line ratio of the NMOS transistor 52 of the reference current fixing circuit 7 and the NMOS transistor 60 of the charge pump circuit 6. The capacitor is charged or discharged through the capacitor 62 to adjust the voltage level of the output line 9 to gate the PMOS transistors 10, 14, 18, 22, 26, and 30 of the delay circuit 2. . As described above, the word line ratio of the PMOS transistor 50 of the reference current fixing circuit 7 and the NMOS transistor 56 of the charge pump circuit 6 and the enmos of the reference current fixing circuit 7 are conventionally described. The delay circuit 2 is controlled by the word line ratio of the transistor 52 and the enMOS transistor 60 of the charge pump circuit 6. Therefore, when the supply voltage and temperature change occurs, there is a problem that the pulse width of the output clock is changed. In addition, for example, when applied to a synchronous DRAM, skew between signals occurs during an internal circuit operation in which a supply voltage changes.

Accordingly, an object of the present invention is to provide a signal delay circuit using a charge pump circuit for delaying an input signal by a predetermined period and providing a stable output signal.

Another object of the present invention is to provide a signal delay circuit using a charge pump circuit for ensuring a stable output frequency even when supply voltage and temperature change.

It is still another object of the present invention to provide a signal delay circuit using a charge pump for removing delay skew generated while the input signal clock passes through the delay circuit.

According to the technical idea of the present invention for achieving the object of the present invention as described above, in the signal delay circuit using the charge pump circuit; A delay unit having at least one delay stage and delaying the input clock signal by a preset frequency in response to the control signal; A delay detecting unit for detecting a signal delay degree of the delay unit; The DC signal corresponding to the pulse width ratio of the detection signal and the input clock signal is generated by receiving the detection signal and the input clock signal of the delay detection unit, and supplying the DC signal to the delay unit to supply a suggestion signal to the delay unit. A charge pump unit for feeding back a voltage; And a current fixing circuit unit for providing a current having a current value fixed to the charge pump unit.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

5 is a block diagram of a signal delay circuit having a charge pump circuit according to the present invention. Referring to FIG. 5, the delay circuit 78 receives an input clock signal having a preset frequency and delays the input clock signal by a predetermined time in response to a control signal. The delay detecting circuit 80 receives a delayed output signal from the delay circuit 78 or sometimes directly receives the input clock signal to detect a delay time according to the input clock signal. The charge pump circuit 82 receives the signal sensed by the delay detection circuit 80 and the input clock signal to charge one pulse period of the input clock signal by a predetermined capacitor, and one pulse of the detection signal. The cycle is discharged by a predetermined capacitor so that the charge and the discharge degree of the capacitor coincide with each other. At this time, the charge pump circuit 82 generates the control voltage and fixes the delay time of the delay circuit 2 according to the power supply current ratio between the power supply current being discharged and the power supply storage being charged. The reference current fixing circuit 86 is composed of a pair of current mirrors and provides a predetermined current to the charge pump circuit 82 to maintain a constant pumping efficiency according to temperature change. The control voltage of the charge pump circuit 82 is provided to the delay circuit 78 through the low pass filter circuit 84 when a control signal is required.

FIG. 6 is a detailed circuit diagram of FIG. Referring to FIG. 6, the reference current fixing circuit 86 includes a first current mirror composed of PMOS transistors 134 and 136 and a second current mirror composed of enMOS transistors 138 and 140 between a power supply voltage and a ground voltage. Is formed. Resistors 135 and 137 having a predetermined resistance value are connected between the first current mirror and the second current mirror. At one end of the first current mirror and one end of the second current mirror, a fixed first reference current and a second reference current are provided to the charge pump circuit 82.

The charge pump circuit 82 includes a pumping efficiency determiner 92 in which PMOS transistors 150 and 152 and NMOS transistors 154, 156 and 158 are connected in series between a power supply voltage and a ground voltage. do. That is, the first reference current is input to the gate of the PMOS transistor 150, and the second reference current is input to the gate of the NMOS transistor 158. Therefore, the pumping efficiency of the PMOS transistor 150 and the NMOS transistor 158 is determined. On the other hand, an input clock signal is input to the gate of the PMOS transistor 152 and output from the first fixed voltage supply unit 88 and the second fixed voltage supply unit 90 to the gate of the NMOS transistor 154. Input constant voltage. The first fixed voltage supply unit 88 includes an NMOS transistor 142, and the second fixed voltage supply unit 90 includes NMOS transistors 144 and 146 having a channel connected in series between a power supply voltage and a ground voltage. 148). In addition, the NMOS transistor 156 of the charge pump circuit 82 is connected to the output terminal of the delay detection circuit 8, which will be described later, and is gated. In addition, the capacitor 160 of the charge pump circuit 82 is commonly connected to the PMOS transistor 152 and the NMOS transistor 154. In this case, it is known that the capacitor 160 is not a parasitic capacitor. Therefore, the current of the PMOS transistors 150 and 152 flows to the capacitor 160. Meanwhile, while the PMOS transistor 152 is maintained based on the input clock signal, the capacitor 160 is charged by a current having a value preset by the PMOS transistor 150. The capacitor 160 is discharged by a current having a value preset by the NMOS transistor 158 while the NMOS transistor 156 is held based on the output signal of the delay sensing circuit 80.

The low pass filter circuit 84 is composed of a resistor 162 and a capacitor 164 to obtain a DC voltage by relaxing the terminal voltage of the capacitor 160 of the charge pump circuit 6. The output signal by the low pass filter circuit 8 is provided to the delay circuit 78.

The delay circuit 78 is formed by a cascade junction of a first delay stage, a second delay stage, and a third delay stage including the PMOS transistors 94 and 100 and the inverters 96 and 98. A source of the PMOS transistor 100 is a load transistor connected to a power supply voltage and a drain connected to the inverter 98. The output node 170 of the third delay stage has an inverter 118, an inverter for inverting the output of the NAND gate 120 and the NAND gate 120 that receive the output signal and the input clock signal of the inverter 118. 122 is connected. The input clock signal is provided to the first delay end through the PMOS transistor 94 and the output signal from the first delay end and the second delay end is provided to the third delay end that is followed by the input signal. The signal output from the last stage, that is, the third delay stage, is output through the inverter 118, the NAND gate 120, and the inverter 122.

The delay detection circuit 80 may include inverters 124, 130, and 132 for inverting the output signals of the first and second delay stages, and a NAND gate having an output of the inverters 124 and 132. 126 and an inverter 128 for inverting the output signal of the NAND gate 126 and providing the inverted signal to the gate of the NMOS transistor 156 of the charge pump circuit 82.

FIG. 7 is a timing diagram of FIG. Referring to FIG. 7, waveforms of an input clock signal, a node 166, a node 168, a node 170, a node 172, and a final output clock signal having a constant frequency are shown.

8 is a simulation diagram of FIG. Referring to FIG. 8, the clock change of the charge pump circuit 6 is shown when the power supply voltage VDD changes. In the present invention, as shown in FIG. 8, even if the power supply voltage is changed, it can be seen that the pulse width is constant from the second cycle regardless.

As described above, in the signal delay circuit according to the present invention, it is possible to ensure a stable output frequency irrespective of supply voltage or temperature change, and to efficiently delay delay skew generated while an input signal clock having a predetermined frequency passes through the delay circuit. It can be removed by the effect.

Claims (10)

In a signal delay circuit using a charge pump circuit; A delay unit 78 having a plurality of delay stages and delaying the input clock signal by a predetermined frequency in response to the control signal; A delay detecting unit 80 for detecting a signal delay degree of the delay unit; The DC signal corresponding to the pulse width ratio of the detection signal and the input clock signal is generated by receiving the detection signal and the input clock signal of the delay detection unit, and the DC unit is supplied to the delay unit to supply a control signal to the delay unit. A charge pump unit 82 for feeding back a voltage; And a reference current fixing circuit section (86) for providing a current having a fixed current value in the charge pump section. The control circuit of claim 1, wherein the delay stage includes a first PMOS transistor 94 gated with the control signal, a first inverter 96 for inverting the output of the PMOS transistor 94, and the control signal. And a source is connected to a power supply voltage and a drain is composed of a second PMOS transistor 100 connected to a second inverter 98 which receives the output of the first inverter 96 to delay the input clock signal. Signal delay circuit characterized in that. According to claim 1, wherein the delay detecting unit 80 is the third inverter 166 and the fourth inverter 130 connected to the output terminal of the delay stage and the fourth inverter for inverting the output of the fourth inverter (130) And a fifth inverter 132, a first NAND gate 126, and a sixth inverter 128 that inverts the output of the first NAND gate 126 to output a detection signal to the charge pump circuit. A signal delay circuit. The first current mirror including the PMOS transistors 134 and 136 having gates connected to each other between a power supply voltage and a ground voltage, and an NMOS transistor having gates connected to each other. 138 and 140, and second and second resistors 135 and 137 are provided between the first and second current mirrors, thereby providing a first reference current and a second reference current. Signal delay circuit, characterized in that for outputting to the charge pump circuit (82). The charge pump circuit 82 of claim 1 is provided between the PMOS transistors 150 and 152 having a channel connected in series to a power supply voltage terminal, and between the drain terminal of the PMOS transistor 152 and the ground voltage terminal. Channels are provided with first, second and third en-MOS transistors 154, 156 and 158 connected in series, and gates of the en-MOS transistor 154 are gated through the first and second fixed voltage supply units 88 and 90. And a capacitor for charge and discharge between the PMOS transistor 152 and the NMOS transistor 154. The method of claim 5, wherein the PMOS transistor 150 and the NMOS transistor 158 determines the pumping efficiency of the charge pump circuit portion 82, respectively output from the first current mirror of the current fixing circuit portion 86 And a second reference current output from the first reference current and the second current mirror. The signal delay circuit of claim 5, wherein the PMOS transistor 152 inputs the input clock signal, and the NMOS transistor 156 inputs a detection signal of the delay detection unit 80. . 6. The signal delay circuit according to claim 5, wherein the first fixed voltage supply unit (88) comprises an enMOS transistor (142) whose gate and drain are commonly connected to a power supply voltage. The method of claim 5, wherein the second fixed voltage supply unit 90 is made of a second, third, fourth enMOS transistor (144, 146, 148) connected in series between the power supply voltage and the ground voltage, characterized in that Signal delay circuit. The method of claim 5, wherein the charge-only capacitor 160 is driven by a current having a value preset by the PMOS transistor 150 while the PMOS transistor 152 is maintained based on the input clock signal. And while the NMOS transistor 156 is held based on the output signal from the delay detecting unit 80, the NMOS transistor 156 is discharged by a current having a predetermined value determined by the NMOS transistor 158. Signal delay circuit.