JP2008027509A - Booster circuit and nonvolatile memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a booster circuit efficiently testing a section applied with high voltage. <P>SOLUTION: The booster circuit includes: a booster circuit block 12 generating boosting voltage; a limiter circuit 60 for limiting voltage difference between boosting voltage VPP of an output node NQ of the booster circuit block 12 and voltage of a power source node NV to limit voltage VLM; and a test circuit 80 in which, in a normal operation mode, the power source node NV is set to a first voltage level, in a test mode, the power source node NV is set to a second voltage level higher than the first voltage level. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a booster circuit and a nonvolatile memory device.

  Conventionally, a booster circuit for generating a boosted voltage is known. This booster circuit is used to generate a high voltage necessary for a write operation of a nonvolatile memory device such as an EEPROM or a flash memory, or to generate a high voltage necessary for an operation of an LCD driver or a DRAM.

  In such a booster circuit, a high boosted voltage is applied to the booster circuit itself or a circuit to which the boosted voltage is supplied. When such a high voltage is applied in this way, there arises a problem that the life of the circuit element is shortened.

  Further, the transistor and the capacitor to which the boosted voltage is applied are formed by a high voltage transistor and a high voltage capacitor having a high breakdown voltage. In such a high breakdown voltage transistor or a high breakdown voltage capacitor using the gate capacitance of the transistor, the gate oxide film is thickened to increase the breakdown voltage. However, when the gate oxide film is made thick in this manner, impurity defects and the like are likely to occur, and the occurrence rate of initial defects is increased.

  In this case, in order to screen for such an initial failure, a method of realizing a stress test by applying a high voltage for a long time can be considered.

However, this method increases the test time for screening and increases the cost of the product.
Japanese Patent Application Laid-Open No. 2004-247689

  The present invention has been made in view of the technical problems as described above, and an object of the present invention is to provide a booster circuit that enables an efficient test of a high voltage application portion, and a nonvolatile circuit including the booster circuit. It is to provide a memory device.

  The present invention relates to a booster circuit block for generating a boosted voltage, a limiter circuit for limiting the voltage difference between the boosted voltage at the output node of the booster circuit block and the voltage at the first power supply node to a limit voltage, In the operation mode, the first power supply node is set to a first voltage level, and in the test mode, the first power supply node is set to a second voltage level higher than the first voltage level. Is related to a booster circuit including

  In the present invention, in the test mode, the first power supply node is set to a second voltage level higher than the first voltage level. The limiter circuit operates so that a voltage difference between the voltage of the output node and the voltage of the first power supply node set to the second voltage level becomes a limit voltage. Therefore, according to the present invention, the operation of such a limiter circuit can be effectively used to set the output node of the booster circuit block to a higher voltage than the boosted voltage in the normal operation mode. Efficient testing is possible.

  In the present invention, the test circuit includes a buffer circuit to which a test instruction signal is input, and the buffer circuit receives the test instruction signal, and when the test instruction signal becomes active in a test mode, The voltage setting signal of the second voltage level may be output to the first power supply node.

  In this way, the first power supply node can be set to the second voltage level simply by activating the test instruction signal in the test mode.

  In the present invention, the test circuit includes a transfer circuit that is provided between a test input terminal and the first power supply node and is in a transfer state in a test mode, and the transfer circuit includes the test circuit in the test mode. The voltage setting signal of the second voltage level input to the input terminal may be output to the first power supply node to set the first power supply node to the second voltage level.

  In this way, the first power supply node can be set to an arbitrary second voltage level by the voltage setting signal input to the test input signal.

  In the present invention, the test circuit may include a voltage setting circuit that sets the first power supply node to the first voltage level in a normal operation mode.

  This makes it possible to operate the limiter circuit normally by setting the first power supply node to the first voltage level in the normal operation mode.

  In the present invention, the limiter circuit includes a diode element for setting a limit voltage provided between the output node and the detection node of the booster circuit block, and between the detection node and the first power supply node. And a limit level adjusting circuit for adjusting the level of the limit voltage.

  In this way, the limit voltage can be adjusted to a desired voltage by the limit level adjustment circuit while the main part of the limit voltage is set by the diode element.

  In the present invention, the limit level adjusting circuit includes a P-type first limit level adjusting transistor having a gate to which a first power supply is input and a drain connected to the first power supply node. Also good.

  In this way, the P-type first limit level adjusting transistor can function as a limit level adjusting transistor not only in the normal operation mode but also in the test mode.

  In the present invention, the limit level adjustment circuit is provided between the detection node and the first limit level adjustment transistor, and has at least one N-type second limit level connected to the drain and gate thereof. An adjustment transistor may be included.

  In this way, the limit voltage can be set to a desired voltage by using the threshold voltage of the second limit level adjusting transistor.

  The present invention also includes a clock supply circuit that generates a charge pump clock and supplies the clock to a charge pump circuit that is the booster circuit block, and a limit operation detection circuit that detects a limit operation of the limiter circuit, and the limit operation When detecting a limit operation of the limiter circuit, the detection circuit may activate a stop signal for stopping clock generation of the clock supply circuit and output the active stop signal to the clock supply circuit.

  According to the present invention, when the limit operation of the limiter circuit is detected, the clock generation of the clock supply circuit is stopped, whereby the charge pump operation of the charge pump circuit that is the booster circuit block can be stopped. Therefore, it is possible to prevent a situation in which the charge pump circuit operates wastefully and wastes power is consumed during the limit operation. Further, overshoot of the output node of the charge pump circuit can be suppressed, and reliability can be improved.

  In the present invention, the limit operation detection circuit may deactivate the stop signal when the test circuit sets the first power supply node to the second voltage level in the test mode. Also good.

  In this way, in the test mode, it is possible to deactivate the stop signal, permit clock generation of the clock supply circuit, and operate the charge pump circuit. Accordingly, in the test mode, a high stress test can be realized while the charge pump circuit is in an operating state, and the test efficiency can be improved.

  According to the present invention, the limit operation detection circuit is connected to a detection circuit connected to a detection node of the limiter circuit and a first output node of the detection circuit, and outputs the stop signal to a second output node. The detection circuit includes a load circuit provided between a second power source and the first output node, a drain connected to the first output node, and a gate connected to the limiter. An N-type detection transistor connected to the detection node of the circuit may be included.

  In this way, even when an intermediate potential is output to the detection node of the limiter circuit, this intermediate potential can be reliably detected.

  In the present invention, the test circuit sets the source of the detection transistor to the second voltage level when the first power supply node is set to the second voltage level in the test mode. It may be.

  In this way, in the test mode, a high stress test can be realized while deactivating the stop signal, permitting clock generation, and setting the charge pump circuit in an operating state.

  Further, in the present invention, when the limit operation of the limiter circuit is detected, the output circuit activates the stop signal, the limit operation of the limiter circuit is not detected, and the boosted voltage is supplied. The stop signal may be deactivated when a write signal to the non-volatile memory device is active.

  This makes it possible to provide a booster circuit suitable for generating a boosted voltage for writing data to the nonvolatile memory device.

  In the present invention, the charge pump circuit as the booster circuit block includes first to Nth (N is an integer of 2 or more) charge pump units connected in series, and the first to Nth charge pump units. Each charge pump unit includes a charge transfer circuit for transferring charges between charge pump capacitors, a first capacitor for charge pump whose one end is connected to the charge transfer circuit, and one end for the charge transfer circuit. A second capacitor for a charge pump connected to the charge transfer circuit, a first clock supply node to which a first clock is supplied, and the other end of the first capacitor; A first voltage conversion circuit that outputs a first conversion clock obtained by boosting the voltage of the first clock to the other end of the first capacitor; and a second clock A second conversion clock provided between the supplied second clock supply node and the other end of the second capacitor and obtained by boosting the voltage of the second clock is converted into the second conversion clock. A second voltage conversion circuit that outputs to the other end of the capacitor may be included.

  According to the present invention, each charge pump unit can generate a boosted voltage by performing a charge pump operation based on the first and second conversion clocks whose voltage has been boosted. Accordingly, it is possible to provide a charge pump circuit capable of improving the boosting efficiency while suppressing the circuit scale.

  In the present invention, the first voltage conversion circuit includes a first voltage conversion capacitor provided between the first charge storage node and a first voltage change node whose voltage level changes based on a clock; A first precharge circuit provided between a second power source and the first charge storage node for precharging the first charge storage node; the first charge storage node; A first charge transfer circuit provided between the first output node and the first charge transfer circuit for transferring the charge accumulated in the first charge accumulation node to the first output node in a first charge transfer period; A first discharge circuit that is provided between one output node and a first power supply and discharges the first output node in a first discharge period, and the second voltage conversion circuit includes: The second Between a charge storage node and a second voltage change node provided with a second voltage change node whose voltage level changes based on a clock, and between a second power supply and the second charge storage node And a second precharge circuit for precharging the second charge storage node, and provided between the second charge storage node and the second output node, and a second charge transfer period The second charge transfer circuit transferring the charge stored in the second charge storage node to the second output node; and between the second output node and the first power supply, The second discharge period may include a second discharge circuit that discharges the second output node.

  If a circuit having such a configuration is used as the first and second voltage change circuits, first and second conversion clocks obtained by boosting the voltages of the first and second clocks can be obtained with a small circuit configuration. As a result, the boosting efficiency of the charge pump circuit can be improved while reducing the circuit scale.

  In the present invention, the second charge transfer circuit of the first voltage conversion circuit performs the charge transfer from the first charge storage node to the first output node. The second discharge circuit of the second voltage conversion circuit discharges the second output node, and the second charge transfer circuit of the second voltage conversion circuit starts from the second charge storage node. The first discharge circuit of the first voltage conversion circuit may discharge the first output node during a period in which charge transfer to the second output node is performed.

  In this way, it is possible to prevent such a situation that the charge of the first charge storage node is discharged to the first power supply side, or the charge of the second charge storage node is discharged to the first power supply side. Is possible.

  In the present invention, the first voltage and the second voltage conversion circuit are supplied with the first clock and the second clock having a non-overlap relationship with the first clock, When the first clock is at the second voltage level and the second clock is at the first voltage level, the first charge transfer circuit is connected to the first charge storage node from the first charge storage node. Charge transfer to an output node, the second discharge circuit discharges the second output node, the first clock is at a first voltage level, and the second clock is a second voltage When it is at the voltage level, the second charge transfer circuit performs charge transfer from the second charge storage node to the second output node, and the first discharge circuit transfers the first charge circuit. Output node It may be carried out charge.

  In this case, the first and second clocks are effectively utilized in the non-overlapping relationship, so that the charge on the first charge storage node is discharged to the first power source side, It is possible to prevent such a situation that the charge of the charge storage node is discharged to the first power supply side.

  Further, the present invention provides a memory cell array in which a plurality of nonvolatile memory cells are arranged, and writing, reading, and erasing of data in the nonvolatile memory cells based on a boosted voltage generated by any of the boosting circuits described above. And an access control circuit for performing at least one of the following.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Test of Booster Circuit FIG. 1 shows a configuration example of the booster circuit of this embodiment. The booster circuit of this embodiment includes a booster circuit block 12 that generates a boosted voltage. Specifically, the booster circuit block 12 boosts the power supply voltage VDD by, for example, a charge pump method to generate the boosted voltage VPP. More specifically, the booster circuit block 12 can be realized by, for example, a charge pump circuit having a plurality of charge pump units connected in series. A smoothing circuit for smoothing the boosted voltage may be provided between the output of the booster circuit block 12 and the output node NQ of the boosted voltage VPP.

  The booster circuit includes a limiter circuit 60 and a test circuit 80. Here, the limiter circuit 60 is a circuit for limiting (clamping) the boosted voltage VPP generated by the booster circuit block 12. Specifically, the limiter circuit 60 converts the voltage difference between the boosted voltage VPP at the output node NQ of the booster circuit block 12 and the voltage at the VSS power supply node NV (first power supply node in a broad sense) to the limit voltage VLM. This is a circuit for limiting. That is, the boosted voltage VPP is limited so that this voltage difference does not exceed the limit voltage VLM.

  The test circuit 80 is a circuit for performing a test such as a high stress test. Specifically, in the normal operation mode, the test circuit 80 sets the power supply node NV of VSS (first power supply in a broad sense) to, for example, 0 V (first voltage level in a broad sense) that is a voltage level of VSS. Set. On the other hand, in the test mode, the power supply node NV is set to a voltage V2 (second voltage level in a broad sense) higher than 0V. For example, the power supply node NV is set to V2 = VDD (second power supply in a broad sense).

  In this way, in the normal operation mode, the boosted voltage VPP is limited to satisfy VPP ≦ VLM, for example. On the other hand, in the test mode, this limit is released and, for example, VPP ≦ VLM + V2.

  The high boosted voltage VPP generated by the booster circuit block 12 is applied to circuit elements such as transistors and capacitors of the booster circuit itself, and circuit elements to which the boosted voltage VPP is supplied (for example, a circuit of a nonvolatile memory device). Applied. When such a high boosted voltage VPP is applied to the circuit element, there arises a problem that the life of the circuit element is shortened.

  Transistors and capacitors to which boosted voltage is applied are formed by high breakdown voltage transistors and high breakdown voltage capacitors with high breakdown voltage. In such high breakdown voltage transistors and high breakdown voltage capacitors, the gate oxide film is thickened to increase the breakdown voltage. ing. If the gate oxide film becomes thick in this way, impurity defects and the like are likely to occur, and the initial failure rate increases.

  In the present embodiment, the test circuit 80 of FIG. 1 is used to screen for such initial defects and the like.

  That is, in the present embodiment, in the normal operation mode in which the booster circuit normally generates the boosted voltage, the test circuit 80 outputs the 0V voltage setting signal VSET to the power supply node NV. In this way, the limiter circuit 60 operates so that the voltage difference between the boosted voltage VPP and VSET = 0V becomes the limit voltage VLM. Therefore, even if the booster circuit block 12 outputs a voltage higher than the limit voltage VLM, the boosted voltage VPP can be clamped to the limit voltage VLM. As a result, it is possible to prevent a high voltage exceeding the limit voltage VLM from being applied to the circuit elements of the booster circuit and the circuit to which the VPP is supplied in the normal operation mode, and it is possible to suppress the life reduction and destruction of the circuit elements. .

  On the other hand, in a test mode such as a high stress test, test circuit 80 outputs a voltage setting signal VSET having a voltage V2 higher than 0V to power supply node NV. Specifically, for example, a voltage setting signal VSET in which V2 = VDD is output. At this time, the limiter circuit 60 operates so that the voltage difference between the output node NQ and the power supply node NV becomes the limit voltage VLM. Therefore, during this high stress test, the boosted voltage VPP can be set to a higher voltage than the limit voltage VLM as shown in FIG. Specifically, the boost voltage VPP can be set to a voltage of about VLM + V2. Therefore, during a high stress test, a voltage higher than VLM can be applied to the circuit elements of the booster circuit and the circuit to which VPP is supplied as shown in FIG. As a result, a high stress test for screening an initial failure of a high voltage transistor or a high voltage capacitor can be realized in a short time, and a reliability test of a booster circuit or an integrated circuit device including the same can be realized in a short test time. become.

2. Test Circuit FIG. 3 shows a first configuration example of the test circuit 80. In FIG. 3, the test circuit 80 includes a buffer circuit BUF to which a test instruction signal TSI is input. The test instruction signal TSI is output from a test decoder 82 that decodes the test signal and outputs various test instruction signals. That is, the test decoder 82 decodes a test signal input from a pad (input terminal in a broad sense) of an integrated circuit device including a booster circuit. If it is determined from the decoding result that the integrated circuit device is set to the test mode and a high stress test (limiter release) is instructed, the test instruction signal TSI for the high stress test is activated. Specifically, for example, the test instruction signal TSI is set to a voltage level of VDD which is an H level.

  Buffer circuit BUF receives test instruction signal TSI. When the test instruction signal TSI No. becomes active in the test mode, the voltage setting signal VSET of the voltage V2 is output to the power supply node NV. Specifically, a voltage setting signal VSET having a voltage level of VDD is output. In this way, the voltage of the output node NQ is set to VPP = VLM + V2 = VLM + VDD, thereby realizing a high stress test.

  FIG. 4 shows a second configuration example of the test circuit 80. In FIG. 4, the test circuit 80 includes a transfer circuit 84. The transfer circuit 84 is provided between the test pad TPD (test input terminal in a broad sense) and the power supply node NV. In the test mode, the transfer state (ON state, conduction state) is established.

  Specifically, the transfer circuit 84 includes a transfer gate including an N-type transistor TH1 and a P-type transistor TH2. When the test mode signal TM becomes active, the transistors TH1 and TH2 are turned on, and the transfer circuit 84 enters the transfer state. In FIG. 4, the transfer circuit 84 is configured by a transfer gate, but may be configured by only an N-type transistor, for example.

  In the test mode, the transfer circuit 84 outputs the signal VSETI of the voltage V2 input to the test pad TPD (test input terminal) to the power supply node NV as the voltage setting signal VSET, whereby the power supply node NV becomes the voltage V2 Set to That is, when the test mode signal TM becomes active and the transfer circuit 84 enters the transfer state, the power supply node NV is set to a voltage level corresponding to the voltage level of the input signal VSETI of the pad TPD.

  In the first configuration example of FIG. 3, the power supply node NV is set to the voltage level of VDD in the test mode. On the other hand, in the second configuration example of FIG. 4, the voltage V2 of the power supply node NV can be variably controlled by the input signal VSETI. Therefore, the boosted voltage VPP = VLM + V2 during the high stress test can be variably controlled, and a test with a high degree of freedom and flexibility can be realized.

  In FIG. 4, the test circuit 80 includes a transistor TH3 that functions as a voltage setting circuit that sets the power supply node NV to 0 V (first voltage level) in the normal operation mode. Specifically, the inverted signal of the test mode signal TM is input to the gate of the transistor TH3, and the power supply VSS is connected to the source. Therefore, when the normal operation mode is entered, the test mode signal TM becomes L level, and the inverted signal thereof becomes H level, the transistor TH3 is turned on and the power supply node NV is set to 0V. Note that a transistor that pulls down the power supply node NV to VSS may be provided as the voltage setting circuit regardless of the voltage level of the test mode signal TM.

3. Limiter Circuit FIG. 5 shows a configuration example of the limiter circuit 60. The limiter circuit 60 includes a diode element DI and a limit level adjustment circuit 62.

  The diode element DI is provided between the output node NQ and the detection node NDT of the booster circuit block 12. The diode element DI can be realized by, for example, a PN junction formed by a P-type well and an N + impurity layer formed in the P-type well. The main part of the limit voltage VLM is set by the breakdown voltage VBD (breakdown voltage) when the diode element DI is reversely biased.

  The limit level adjusting circuit 62 is provided between the detection node NDT and the power supply node NV, and is a circuit for adjusting the level of the limit voltage VLM. That is, when the desired limit voltage VLM is larger than the breakdown voltage VBD of the diode element DI, the level is adjusted by the limit level adjustment circuit 62. For example, if the adjustment voltage of the limit level adjustment circuit 62 is VAJ, the relationship VLM = VBD + VAJ is established.

  In FIG. 5, the limit level adjusting circuit 62 includes a P-type first limit level adjusting transistor TJ1 and an N-type second limit level adjusting transistor TJ2.

  Here, VSS (first power supply) is input to the gate of the transistor TJ1, and the drain thereof is connected to the power supply node NV. The transistor TJ2 is provided between the detection node NDT and the transistor TJ1, and its drain and gate are connected. That is, the transistor TJ2 is diode-connected and functions as a diode.

  In FIG. 5, when the threshold voltage of the transistors TJ1 and TJ2 is VTH, it can be expressed as VAJ = 2VTH. Therefore, it can be expressed as VLM = VBD + VAJ = VBD + 2VTH. In FIG. 5, only one diode-connected transistor TJ2 is provided, but a plurality of diode-connected transistors may be provided. In this case, the adjustment voltage VAJ increases as the number of diode-connected transistors increases, and the limit voltage VLM can be increased.

  This embodiment is characterized in that a P-type transistor TJ1 whose gate is connected to VSS is provided as a limit level adjusting transistor as shown in FIG.

  That is, when the power supply node NV is VSS = 0V, the transistor TJ1 functions as a normal P-type diode-connected transistor whose gate and drain are connected, and functions as a limit level adjusting transistor. .

  On the other hand, even when the test mode is set and the voltage of the power supply node NV is increased by the test circuit 80, the transistor TJ1 is turned on because VSS is input to the gate of the transistor TJ1. Therefore, also in this test mode, the transistor TJ1 functions as a limit level adjusting transistor, and the relationship of VLM = VBD + VAJ = VBD + 2VTH can be established. This makes it possible to realize a high stress test as shown in FIG.

4). Clock Stop by Limiter Operation Detection In the present embodiment, a method of detecting the limit operation of the limiter circuit 60 and stopping the charge pump clock is adopted.

  For example, the booster circuit of FIG. 6 includes a charge pump circuit 10 that is the booster circuit block 12 of FIG. A clock supply circuit 50 that supplies a clock to the charge pump circuit 10 is also included. That is, the clock supply circuit 50 generates and supplies the charge pump clocks CK11, CK12, CK21, CK22,... CKN1, CKN2 to the charge pump circuit 10.

  Here, the clocks CK11 and CK12, CK21 and CK22,... CKN1 and CKN2 have a non-overlapping relationship. That is, in the period when the clock CK11 is active (second voltage level, for example, H level), the clock CK12 is inactive (first voltage level, for example, L level), and in the period where the clock CK12 is active, CK11 becomes inactive. The relationship between other clocks such as CK21 and CK22 or CKN1 and CKN2 is similar.

  The clock supply circuit 50 can include a ring oscillator 54 (clock generation circuit in a broad sense). The ring oscillator 54 includes, for example, inverters (buffers) connected in series, and generates and outputs multiphase clocks RCK1, RCK2, RCK3,... RCKJ (J is an integer of 2 or more). These clocks RCK1, RCK2, RCK3,... RCKJ are clocks output from the output nodes of the inverters included in the ring oscillator 54.

  The clock supply circuit 50 can include a decoder 52. The decoder 52 decodes the multiphase clocks RCK1 to RCKJ from the ring oscillator 54 to generate clocks CK11, CK12, CK21, CK22,... CKN1, CKN2, and outputs them to the charge pump circuit 10. .

  The booster circuit of FIG. 6 includes a limit operation detection circuit 70 that detects a limit operation. The limit operation detection circuit 70 is connected to the detection node NDT of the limiter circuit 60 and detects the limit operation of the limiter circuit 60. That is, when the boosted voltage VPP rises by the charge pump operation by the charge pump circuit 10 and VPP> VLM, the limiter circuit 60 performs the VPP limit operation. The limit operation detection circuit 70 detects the limit operation of the limiter circuit 60 by detecting the voltage of the detection node NDT at this time or the current flowing through the limiter circuit 60.

  When the limit operation detection circuit 70 detects a limit operation of the limiter circuit 60, the limit operation detection circuit 70 stops the clock generation of the clock supply circuit 50 (ring oscillator), and a stop signal STX ("X" means negative logic). Is output to the clock supply circuit 50. That is, when VPP> VLM and the limit operation of the limiter circuit 60 is detected, the stop signal STX becomes active (for example, 0 V). Then, clock generation by the ring oscillator 54 of the clock supply circuit 50 is stopped. As a result, the supply of the charge pump clocks CK11 to CKN2 to the charge pump circuit 10 is also stopped, and the operation of the charge pump circuit 10 is stopped. As a result, it is possible to prevent the charge pump circuit 10 from operating wastefully and consuming wasteful power.

  After the operation of the charge pump circuit 10 stops, when the charge of the output node NQ is consumed by the circuit to which the boosted voltage VPP is supplied, the voltage of the output node NQ gradually decreases. For example, when VPP <VLM, the limit operation of the limiter circuit 60 is stopped. Then, the limit operation detection circuit 70 detects the voltage (current) of the detection node NDT at this time, and makes the stop signal STX inactive (VDD). As a result, clock generation of the clock supply circuit 50 is started and supply of the clocks CK11 to CKN2 to the charge pump circuit 10 is also resumed, so that the charge pump operation by the charge pump circuit 10 is resumed.

  FIG. 7 shows a signal waveform example of the boosted voltage VPP for explaining the operation of the booster circuit of FIG. In E1 of FIG. 7, the boosted voltage VPP is increased by the charge pump operation of the charge pump circuit 10. When VPP> VLM as in E2, the limiter circuit 60 performs a VPP limit operation. Then, the limit operation detection circuit 70 detects this limit operation and activates the stop signal STX. As a result, as indicated by E3, the clock is stopped and the charge pump operation of the charge pump circuit 10 is stopped.

  In FIG. 7, as indicated by E3 to E8, the operation of the charge pump circuit 10 is stopped. Therefore, the charge pump circuit 10 and the clock supply circuit 50 need only operate intermittently as indicated by E9 to E14. Therefore, power consumption can be greatly reduced as compared with the method in which the charge pump circuit 10 and the clock supply circuit 50 are operated over the entire period. In particular, the power consumption of the ring oscillator 54 represents most of the power consumption of the booster circuit. Therefore, by stopping the ring oscillator 54 at E3 to E8 in FIG. 7, the power consumption of the entire booster circuit can be significantly reduced.

  Further, in FIG. 7, since the clock operation is stopped immediately when the limit operation of the limiter circuit 60 is detected, it is possible to prevent the boosted voltage VPP of the charge pump circuit 10 from overshooting and to improve the reliability. .

  In FIG. 6, limit operation detection circuit 70 deactivates stop signal STX when test circuit 80 sets power supply node NV at voltage V2 (second voltage level) in the test mode. That is, the limit operation detection circuit 70 receives the voltage setting signal VSET from the test circuit 80. When VSET is set to the voltage V2 in the test mode, the stop signal STX is deactivated, and the clock generation of the clock supply circuit 50 is permitted.

  In this manner, even in the test mode in which the boosted voltage VPP is set to VLM + V2, the clock is generated by the clock supply circuit 50 and the charge pump operation by the charge pump circuit 10 is performed. Therefore, the test can be performed with the charge pump circuit 10 operating.

  That is, in the normal operation mode of FIG. 7, the charge pump circuit 10 performs an intermittent operation for reducing power consumption as indicated by E9 to E14. Therefore, it is difficult to measure the power consumption when the charge pump circuit 10 performs a continuous operation.

  In this regard, in the present embodiment, when the voltage setting signal VSET becomes the voltage V2 in the test mode, clock generation of the clock supply circuit 50 is permitted, and the charge pump circuit 10 performs continuous operation. Therefore, it is possible to measure the power consumption of the booster circuit during continuous operation that is not intermittent operation such as E9 to E14 in FIG. That is, in the test mode, not only the high stress test but also the power consumption of the booster circuit during the continuous operation can be measured, and the test efficiency can be improved.

5. Limit Operation Detection Circuit FIG. 8A shows a detailed configuration example of the limit operation detection circuit 70. Limit operation detection circuit 70 includes a detection circuit 72 and an output circuit 74. The detection circuit 72 is connected to the detection node NDT of the limiter circuit 60. The output circuit 74 is connected to the first output node NDQ1 of the detection circuit 72, and outputs a stop signal STX to the second output node NDQ2.

  The detection circuit 72 includes a load circuit 73. The load circuit 73 includes P-type detection transistors TK11 and TK12 provided between VDD (second power supply) and the output node NDQ1. The detection node NDT of the limiter circuit 60 is connected to the gates of the transistors TK11 and TK12.

  In FIG. 8A, the load circuit 73 includes two P-type transistors TK11 and TK12, but the number of transistors may be one or three or more. Further, instead of the transistors TK11 and TK12, a high resistance element may be provided, or a diode-connected N-type transistor may be provided.

  Detection circuit 72 includes an output node NDQ1 connected to its drain and an N-type detection transistor TK2 connected to the detection node NDT of limiter circuit 60 at its gate.

  A power supply node NV is connected to the source of the detection transistor TK2. Therefore, in the test mode, when the power supply node NV is set to the voltage V2 by the test circuit 80, the source of the detection transistor TK2 is also set to the voltage V2. When the source of the transistor TK2 is set to a high voltage V2 (for example, VDD), the output node NDQ1 is set to the high voltage level VH, and the node NK1 becomes 0V. Therefore, by making the write signal WRX active (0 V) in the test mode, the stop signal STX becomes inactive (VDD), and the clock generation of the clock supply circuit 50 is permitted. As a result, the charge pump circuit 10 operates continuously in the test mode, and the power consumption of the booster circuit during the continuous operation can be measured while performing the high stress test as described above.

  As shown in FIG. 8B, the output circuit 74 sets the stop signal STX ("X" means negative logic) to active (0 V) when the limit operation of the limiter circuit 60 is detected. . As a result, the operation of the ring oscillator 54 is stopped. On the other hand, when the limit operation of the limiter circuit 60 is not detected and a write signal WRX ("X" means negative logic) to a nonvolatile memory device to be described later to which a boosted voltage is supplied is active. The stop signal STX is made inactive (VDD). That is, when the output node NK1 of the inverter IVK is 0V and the write signal WRX is 0V (active), the stop signal STX is deactivated. As a result, the ring oscillator 54 operates normally.

  Ring oscillator 54 includes an odd number of inverters IV1 to IVJ. A NANDL for clock control is also included. When the stop signal STX becomes 0 V (active), the output of NADNL is fixed to VDD, so that the clock generation operation of the ring oscillator 54 is stopped.

  As shown in FIG. 8B, when the limit operation of the limiter circuit 60 is detected, the voltage of the detection node NDT is about 2 VTH, for example. Here, VTH is a threshold voltage of the transistors TJ1 and TJ2. When the detection node NDT becomes 2VTH, since 2VTH is higher than the threshold voltage of the transistor TK2 of the detection circuit 72, the transistor TK2 is turned on and the output node NDQ1 becomes a low voltage level VL close to 0V. Since VL is set to a voltage lower than the threshold voltage of the inverter IVK of the output circuit 74, the output node NK1 of the inverter IVK becomes VDD, the stop signal STX becomes 0V, and the ring oscillator 54 Stopped.

  On the other hand, when the limit operation is not detected, the detection node NDT becomes the low voltage level VL (2VTH> VL ≧ 0V). As a result, the P-type transistors TK11 and TK12 of the detection circuit 72 are turned on, and the output node NDQ1 becomes the high voltage level VH. The voltage level of VH is determined by a resistance ratio between the on-resistances of the transistors TK11 and TK12 and the on-resistance of the transistor TK2. Since the high voltage level VH is set to a voltage higher than the threshold voltage of the inverter IVK of the output circuit 74, the output node NK1 of the inverter IVK becomes 0V. Accordingly, if the write signal WRX becomes 0V at this time, the stop signal STX becomes VDD, and the ring oscillator 54 enters an operating state.

6). Booster Circuit FIG. 9 shows a detailed configuration example of the booster circuit of this embodiment. The booster circuit of this embodiment includes a charge pump circuit 10 (boost circuit block in FIG. 1). The charge pump circuit 10 includes a plurality of charge pump units 20-1 to 20-N (first to Nth charge pump units in a broad sense, where N is an integer of 2 or more) connected in series. The power supply voltage VDD is input to the first-stage charge pump unit 20-1, and the last-stage charge pump unit 20-N outputs the boosted voltage VPP by the charge pump. A smoothing circuit may be provided at the output of the charge pump unit 20-N.

  The charge pump unit 20-1 includes a charge transfer circuit 30-1, charge pump capacitors CA11 and CA12 (first and second capacitors), and voltage conversion circuits 40-11 and 40-12 (first and second capacitors). Voltage conversion circuit). The same applies to the charge pump units 20-2... 20-N.

  The charge transfer circuit 20-1 (20-2 to 20-N) is a circuit for performing charge transfer between charge pump capacitors (and preventing backflow of charges between capacitors). Specifically, for example, charge transfer from the previous stage charge pump unit or charge transfer to the next stage charge pump unit is performed. In addition, the charge is prevented from flowing back from the capacitors CA12 to CA11.

  One ends (upper electrodes) of the charge pump capacitors CA11 and CA12 are connected to the charge transfer circuit 30-1. That is, the capacitors CA11 and CA12 are provided between the charge transfer circuit 30-1 and the voltage conversion circuits 40-11 and 40-12.

  The first voltage conversion circuit 40-11 (40-21 to 40-N1) is provided between the first clock supply node to which the first clock CK11 is supplied and the other end (lower electrode) of the capacitor CA11. Provided. The voltage conversion circuit 40-11 (sub boost circuit, level shifter) outputs a clock CK11 ′ (first conversion clock) obtained by boosting (level shifting) the voltage of the clock CK11 to the other end of the capacitor CA11. . Specifically, as shown in FIG. 10, when the clock CK11 is at the L (Low) level (first voltage level in a broad sense), the voltage conversion circuit 40-11 has the L level voltage clock CK11 ′. Is output to the other end of the capacitor CA11. When the clock CK11 is at the H (High) level (second voltage level in a broad sense), the voltage difference (VDD) between the L level and the H level (first and second voltage levels) is doubled, for example. A clock CK11 ′ of a voltage boosted to (2VDD) or about twice (2VDD−VTH) (a voltage boosted to M times (M> 1 in a broad sense)) is output to the other end of the capacitor CA11.

  The second voltage conversion circuit 40-12 (40-22 to 40-N2) is provided between the second clock supply node to which the second clock CK12 is supplied and the other end (lower electrode) of the capacitor CA12. Provided. Then, the clock CK12 '(second conversion clock) obtained by boosting the voltage of the clock CK12 is output to the other end of the capacitor CA12. Specifically, when the clock CK12 is at the L level (eg, 0 V), the voltage conversion circuit 40-12 outputs the clock CK12 'having the L level voltage to the other end of the capacitor CA12. When the clock CK12 is at the H level, the clock CK12 ′ having a voltage obtained by boosting the voltage difference (VDD) between the L level and the H level to, for example, twice (2VDD) or about twice (2VDD−VTH) Output to the other end of CA12.

  In recent years, power supply voltage tends to decrease with process miniaturization. Therefore, in order to obtain the boosted voltage VPP necessary for writing into the nonvolatile memory device using the conventional method when the power supply voltage is lowered in this way, it is necessary to increase the number of stages of the charge pump unit. This leads to an increase in circuit scale and power consumption.

  In this regard, in the present embodiment, the voltage conversion circuits 40-11 and 40-12 boost the voltages of the clocks CK11 and CK12, and the clocks CK11 ′ and CK12 ′ (first and second conversion clocks) whose voltages are boosted. ) Is output to capacitors CA11 and CA12. Therefore, the charge pump unit 20-1 can perform a charge pump operation using the capacitors CA11 and CA12 based on the clocks CK11 'and CK12' having an amplitude of 2VDD. Therefore, the boosting efficiency can be improved as compared with the conventional method in which the charge pump is performed with the clock having the amplitude of VDD, and a high boosted voltage VPP can be obtained with the charge pump unit having a small number of stages. In addition, since the increase in circuit scale is not so large as compared with the method of supplying the original power supply voltage twice in advance, the desired boosted voltage VPP can be achieved while minimizing the increase in circuit scale and power consumption. Can be obtained.

  In the booster circuit in which the charge pump units are connected in series, the boosted voltage VPP corresponding to the magnitude of VDD-VTH and the number of stages of the charge pump unit is generated. However, in the N-type transistor of the charge pump unit close to the final stage, the threshold voltage VTH increases due to the substrate bias effect. Therefore, in the conventional booster circuit, the closer to the final stage the charge pump unit, the smaller the VDD-VTH voltage difference becomes, and the boosting efficiency deteriorates.

  In contrast, in the present embodiment, the charge pump operation is performed based on a clock whose amplitude is converted from VDD to about 2VDD. Therefore, even in a charge pump unit that can raise the saturation level of boosting, the voltage difference of 2VDD-VTH is not so small, and deterioration of boosting efficiency can be minimized.

7). Voltage Conversion Circuit FIG. 11A shows a configuration example of the voltage conversion circuit 40 (40-11 to 40-N2). The voltage conversion circuit 40 includes a voltage conversion capacitor CC, a precharge circuit 42, a charge transfer circuit 44, and a discharge circuit 46.

  The voltage conversion capacitor CC is provided between the charge storage node NC and the voltage change node ND. The voltage change node ND is a node whose voltage level changes based on the clock CK (CK11 to CKN2).

  The precharge circuit 42 is provided between VDD (second power supply in a broad sense) and the charge storage node NC, and precharges the charge storage node NC based on VDD. Specifically, the precharge circuit 42 is provided between the VDD and the charge storage node NC, and has a P type (second conductivity type in a broad sense) whose gate, drain, and substrate are connected to the charge storage node NC. A precharge transistor TC is included. The charge storage node NC is precharged to VDD-VTH by the precharge transistor TC.

  The charge transfer circuit 44 is provided between the charge storage node NC and the output node NF. Then, in the charge transfer period (for example, the period in which CK is at the H level), the charge stored in the charge storage node NC is transferred to the output node NF. Specifically, the charge transfer circuit 44 includes a P-type charge transfer transistor TD that is provided between the charge storage node NC and the output node NF and is turned on during the charge transfer period. That is, the node NE is connected to the gate of the charge transfer transistor TD, and an inverted signal of the clock CK is supplied. Therefore, when the clock CK is at H level, the node NE is at L level, the charge transfer transistor TD is turned on, and charge transfer is performed. The substrate of the charge transfer transistor TD is connected to the charge storage node NC.

  The discharge circuit 46 is provided between the output node NF of the voltage conversion circuit 40 and VSS (first power supply in a broad sense), and discharges the output node NF in a discharge period (for example, a period in which CK is at L level). I do. Specifically, the discharge circuit 46 includes an N-type (first conductivity type in a broad sense) discharge transistor TE that is provided between the output node NF and VSS and is turned on during the discharge period. That is, the node NE is connected to the gate of the discharge transistor NE, and an inverted signal of the clock CK is supplied. Therefore, when the clock CK is at L level, the node NE becomes H level, the discharge transistor TE is turned on, and charge is discharged.

  As shown in FIG. 11B, when the voltage level of the clock CK is 0 V (first voltage level, VSS), the charge storage node NC is precharged to VDD-VTH by the precharging transistor TC. The At this time, since the charge transfer transistor TD is off, it is possible to prevent a situation where the charge of the charge storage node NC is discharged. Further, since the discharge transistor TE is on, the charge of the output node NF is discharged, and thereby the output node NF becomes 0V.

  On the other hand, when the voltage level of the clock CK becomes VDD (second voltage level), the voltage level of the charge storage node NC is boosted by VDD due to capacitive coupling by the capacitor CC, and becomes 2VDD−VTH. At this time, since the charge transfer transistor TD is on and the discharge transistor TE is off, the charge precharged to the charge storage node NC is transferred to the output node NF. As a result, the output node NF can be boosted from 0V to 2VDD−VTH, and clocks CK ′ (CK11 ′, CK12 ′) having signal waveforms as shown in FIG. 10 can be generated.

  When the voltage level of the clock CK becomes VDD and the charge accumulation node NC becomes 2VDD−VTH, the precharging transistor TC is a diode whose reverse bias direction is the direction from the charge accumulation node NC to the power supply VDD. Functions as a diode-connected transistor. Therefore, it is possible to prevent a situation in which the charge accumulated in the charge accumulation node NC flows backward to the power supply VDD side, and the boosting efficiency of the voltage conversion circuit 40 can be improved.

  According to the voltage conversion circuit 40 of FIG. 11A, the amplitude of the clock CK can be converted to about 2VDD only by using the voltage conversion capacitor CC and the transistors TC, TD, TE, and the like. Therefore, voltage conversion with high boosting efficiency can be realized with a simple and small circuit configuration.

  In FIG. 11A, only a voltage difference of about VDD is applied to the voltage conversion capacitor CC and the transistors TC and TD. Therefore, the voltage conversion capacitor CC can be formed of a low breakdown voltage (LV) capacitor, and the transistors TC and TD can be formed of a low breakdown voltage (LV) transistor. Accordingly, the layout area of these capacitors and transistors can be reduced, and the circuit scale can be reduced.

  The discharge transistor TE is formed of a high breakdown voltage (HV) transistor having a higher breakdown voltage than the low breakdown voltage capacitor and the low breakdown voltage transistor because a voltage difference of about 2VDD is applied.

  In FIG. 11A, the precharge transistor TC of the precharge circuit 42 is formed of a P-type transistor. Therefore, it is possible to prevent a substrate bias effect which becomes a problem when the precharge transistor TC is formed of an N-type transistor. Therefore, it is possible to prevent the threshold voltage VTH from becoming high due to the substrate bias effect and the output voltage at the output node NF from becoming small, and boost efficiency can be improved.

8). Detailed Configuration Example of Charge Pump Unit FIG. 12 shows a detailed configuration example of the charge pump unit. In FIG. 12, the charge transfer circuit 30-1 (30-2 to 30-N) of the charge pump unit 20-1 includes N-type first and second transistors TA1 and TB1.

  Here, the first transistor TA1 is provided between the input node NA11 of the charge pump unit 20-1 and the output node NA12 to which one end (upper electrode) of the capacitor CA12 is connected. The gate of the capacitor CA11 is connected to the node NB11 which is one end (upper electrode) of the capacitor CA11. The second transistor TB1 is provided between the input node NA11 and the node NB11 which is one end of the capacitor CA11. The gate is connected to the output node NA12 of the charge pump unit 20-1.

  The output node NF11 of the voltage conversion circuit 40-11 is connected to the other end (lower electrode) of the capacitor CA11. The output node NF12 of the voltage conversion circuit 40-12 is connected to the other end (lower electrode) of the capacitor CA12.

  12, the clock CK11 ′ obtained by boosting the voltage of the clock CK11 by about twice is applied to the other end of the capacitor CA11, and the clock CK12 ′ obtained by boosting the voltage of the clock CK12 by about twice is applied to the capacitor CA12. Applied to the other end, a charge pump operation is performed. Therefore, the boosting efficiency in each charge pump unit can be improved, and a high boosted voltage VPP can be obtained with a charge pump unit having a small number of stages.

  In FIG. 12, the capacitor CA11 functions as a sub capacitor for controlling the gate of the transistor TA1 with respect to the main capacitor CA12. For this reason, the capacitance value of the capacitor CA11 is smaller than that of the capacitor CA12.

  In FIG. 12, the capacitors CC11 and CC12 of the voltage conversion circuits 40-11 and 40-12 are formed of low withstand voltage (LV) capacitors. The transistors TC11, TD11, TC12, and TD12 are also formed of low breakdown voltage transistors. On the other hand, the charge pump capacitors CA11 and CA12 are formed of high withstand voltage (HV) capacitors having a higher withstand voltage than the low withstand voltage capacitors. The transistors TA1 and TB1 are also formed of high voltage transistors having a higher breakdown voltage than the low voltage transistors. The charge transfer circuit 30-1 (30-2 to 30-N) of the present embodiment is not limited to the configuration of FIG. 12, and various modifications can be made.

9. Drive Waveform FIG. 13 shows an example of the drive waveform of the charge pump circuit. FIG. 13 shows a case where the clocks generated by the ring oscillator 54 of FIG. 9 are five-phase clocks RCK1 to RCK5 and the number of stages of the charge pump units 20-1 to 20-N is five (N = 5). It is an example. That is, the decoder 52 decodes the five-phase clocks RCK <b> 1 to RCK <b> 5 from the ring oscillator 54, generates clocks CK <b> 11, CK <b> 12, CK <b> 21, CK <b> 22,.

  In the drive waveform of FIG. 13, the clock supply circuit 50 has the second voltage conversion circuit of the Kth (1 ≦ K <N) charge pump unit among the charge pump units 20-1 to 20 -N. In the period in which the second clock pulse is supplied as the second clock, the second clock pulse is applied to the first voltage conversion circuit of the (K + 1) th charge pump unit next to the Kth charge pump unit. The first clock pulse having a shorter pulse width is supplied as the first clock.

  That is, during the period indicated by A1 in FIG. 13, the clock is supplied to the voltage conversion circuit 40-12 (second voltage conversion circuit) of the charge pump unit 20-1 (Kth charge pump unit) as indicated by A2. A second clock pulse having a long pulse width is supplied as CK12 (second clock). During the period indicated by A1, the voltage conversion circuit 40-21 (first voltage conversion circuit) of the charge pump unit 20-2 (K + 1th charge pump unit) subsequent to the charge pump unit 20-1 is supplied to the voltage conversion circuit 40-21. On the other hand, the first clock pulse A3 having a shorter pulse width than the second clock pulse A2 is supplied as the clock CK21 (first clock).

  Similarly, in the period indicated by A4, the clock CK22 having a long pulse width is supplied to the voltage conversion circuit 40-22 of the charge pump unit 20-2 as indicated by A5. During the period indicated by A4, the pulse width of the voltage conversion circuit 40-23 (not shown) of the charge pump unit 20-3 subsequent to the charge pump unit 20-2 is larger than that of the clock CK22 of A5. Is supplying a short clock CK31 as indicated by A6.

  As shown in the drive waveform of FIG. 13, in this embodiment, the clocks CK11 and CK12 have a non-overlapping relationship (a relationship in which the active periods do not overlap), and the clocks CK21 and CK22 also have a non-overlapping relationship. It has become. The clocks CK11 and CK21 are also non-overlapping, and the clocks CK12 and CK22 are also non-overlapping.

  According to the driving waveform of FIG. 13, the clock CK21 (CK21 ') becomes H level as indicated by A3 within the period indicated by A1 when the clock CK12 (CK12') becomes H level. Accordingly, the voltage of the node NB21 on the upper electrode side of the capacitor CA21 in FIG. 12 is increased, and the transistor TA2 is turned on. Thereby, the electric charge accumulated in the capacitor CA12 is efficiently transferred to the capacitor CA22 via the transistor TA2. At this time, since the transistor TB2 can be set off, it is possible to prevent the charge from the capacitor CA12 from leaking to the capacitor CA21 side through the transistor TB2, thereby improving the boosting efficiency.

  That is, in the drive waveform of FIG. 13, the voltage of the node NB21 is pushed up by the clock CK21 for a short period in the period in which the voltage of the node NA12 of FIG. 12 is pushed up by the clock CK12. Thus, in this short period, the transistor TA2 is turned on, and efficient charge transfer from the capacitor CA12 of the previous stage charge pump unit 20-1 to the capacitor CA22 of the next stage charge pump unit 20-2 is performed. It becomes possible. That is, since the charge transfer efficiency can be improved as compared with the method in which the clocks CK11, CK12, CK21, and CK22 in FIG. 12 are all non-overlapping, the boosting efficiency can be improved. In particular, in the method of boosting the voltage of the clock by the voltage conversion circuit as in this embodiment, the boosting efficiency can be further improved by adopting the drive waveform as shown in FIG. Note that the drive waveform of the present embodiment is not limited to that shown in FIG. 13, and various modifications can be made.

10. First Modification of Voltage Conversion Circuit FIG. 14A shows a first modification of the voltage conversion circuit 40 (40-11 to 40-N2). In FIG. 14A, the precharge circuit 42 is provided between the VDD (second power supply) and the charge storage node NC, and a P-type precharge transistor TC2 whose gate is connected to the output node NF. including. Other than that, the circuit configuration is similar to that of FIG. The substrate of the transistor TC2 is connected to the charge storage node NC. The transistor TC2 is formed of a low breakdown voltage transistor.

  In FIG. 11A, the voltage of the charge storage node NC is VDD-VTH in the precharge period in which the clock CK is 0V. That is, in FIG. 11A, since the transistor TC needs to be turned on in the precharge period, the voltage of the charge storage node NC is lower than VDD by the threshold voltage VTH.

  On the other hand, in FIG. 14A, the discharge transistor TE is turned on in the precharge period in which the clock CK becomes 0V, so that the output node NF becomes 0V. Therefore, since the P-type precharge transistor TC2 to which the voltage of 0 V is input to the gate is completely turned on, the charge storage node NC is precharged to VDD instead of VDD-VTH. . Therefore, in the charge transfer period in which the clock CK is set to VDD and the charge transfer transistor TD is turned on, the voltage of the output node NF is boosted to 2VDD instead of 2VDD−VTH. At this time, since the P-type precharge transistor TC2 to which the voltage of 2VDD is inputted to the gate is completely turned off, the backflow of charges from the charge storage node NC to the VDD power supply can be prevented.

  Thus, in FIG. 11A, only the clock CK ′ having an amplitude of 2VDD−VTH was obtained, whereas according to the first modification of FIG. 14A, the clock CK having an amplitude of 2VDD was obtained. 'Can be obtained, so the boosting efficiency can be improved.

11. Second Modification of Voltage Conversion Circuit FIG. 14B shows a second modification of the voltage conversion circuit 40 (40-11 to 40-N2). In FIG. 14B, the discharge circuit 46 is provided between the output node NF and VSS (first power supply), and is for N-type voltage difference adjustment in which VDD (second power supply) is input to the gate. Includes a transistor TF. The discharge circuit 46 includes an N-type discharge transistor TG that is provided in series with the voltage difference adjusting transistor TF between the output node NF and VSS and is turned on during the discharge period.

  In FIG. 14B, the output node NF is connected to the gate of the precharge transistor TC2 as in FIG. 14A, but the gate of the transistor TC2 is charged as shown in FIG. Variations connected to the storage node NC are also possible.

  According to the second modification of FIG. 14B, the N-type transistors TF and TG constituting the discharge circuit 46 can be formed by low breakdown voltage transistors. Therefore, the layout area of the voltage conversion circuit 40 can be reduced as compared with the case where the transistor TE constituting the discharge circuit 46 is formed of a high voltage transistor as shown in FIG. That is, in FIG. 14B, the capacitor CC and the transistors TC2, TD, TF, and TG constituting the voltage conversion circuit 40 can all be formed by low voltage transistors. Accordingly, the gate area of the transistors TF and TG can be reduced to reduce the layout area, and the capacitor CC and the transistors TC2, TD, TF, and TG can be laid out collectively in a low withstand voltage region. Compared to the layout area, the layout area can be reduced.

12 Third Modification Example of Voltage Conversion Circuit FIG. 15A shows a third modification example of the voltage conversion circuit and the booster circuit including the voltage conversion circuit.

  In the voltage conversion circuit of FIG. 11A, the same node NE is connected to the transistors TD and TE. Therefore, in the transition period of the voltage level of the node NE, a situation occurs in which both the transistors TD and TE are turned on, and a through current is generated. When such a through current is generated, the charge stored in the storage node NC is discharged to the VSS side, and the boosting efficiency is deteriorated. According to the third modification of FIG. 15A, such a problem can be solved.

  In FIG. 15A, a first voltage conversion circuit 40-11 includes a capacitor CC11 as a first voltage conversion capacitor, a first precharge circuit, a first charge transfer circuit, and a first discharge circuit, respectively. , Transistor TC11, transistor TD11, transistors TF11 and TG11. The second voltage conversion circuit 40-12 includes a capacitor CC12, a transistor TC12, and a transistor as a second voltage conversion capacitor, a second precharge circuit, a second charge transfer circuit, and a second discharge circuit, respectively. Includes TD12, transistors TF12 and TG12.

  FIG. 15A shows the case where the configuration of FIG. 14B is adopted as each of the voltage conversion circuits 40-11 and 40-12, but FIG. 11A and FIG. A configuration or the like may be adopted.

  In FIG. 15A, as indicated by B1 in FIG. 15B, the transistor TD11 (first charge transfer circuit) of the voltage conversion circuit 40-11 is changed from the charge storage node NC11 (first charge storage node). In a period (first charge transfer period) in which charge is transferred to the output node NF11 (first output node), as shown by B2, the transistor TG12 (second discharge circuit) of the voltage conversion circuit 40-12 Discharges the output node NF12 (second output node). That is, during the period in which the charge transfer transistor TD11 of the voltage conversion circuit 40-11 is turned on, the discharge transistor TG12 of the voltage conversion circuit 40-12 is turned on and discharge is performed.

  Further, as indicated by B3 in FIG. 15B, the transistor TD12 (second charge transfer circuit) of the voltage conversion circuit 40-12 is connected to the output node NF12 (second charge storage node) from the charge storage node NC12 (second charge storage node). In the period (second charge transfer period) during which charge is transferred to the output node of the output node), the transistor TG11 (first discharge circuit) of the voltage conversion circuit 40-11 is connected to the output node NF11 (first discharge circuit) as indicated by B4. The first output node) is discharged. That is, during the period in which the charge transfer transistor TD12 of the voltage conversion circuit 40-12 is turned on, the discharge transistor TG11 of the voltage conversion circuit 40-11 is turned on and discharge is performed.

  As shown at B5 and B6 in FIG. 15B, the voltage conversion circuits 40-11 and 40-12 include a clock CK11 (first clock) and a clock that is non-overlapping with respect to the clock CK11. CK12 (second clock) is supplied.

  The charge transfer circuit 40-11 is provided between the charge storage node NC11 and the output node NF11, and turns on when the clock CK11 is at the H level (second voltage level). A transistor TD11 is included. Also included is an N-type discharge transistor TG11 which is provided between the output node NF11 and VSS (first power supply) and is turned on when the clock CK12 is at the H level. That is, the inverted signal of the clock CK11 is input to the gate of the transistor TD11, and the non-inverted signal of the clock CK12 is input to the gate of the transistor TG11.

  The charge transfer circuit 40-12 includes a P-type charge transfer transistor TD12 which is provided between the charge storage node NC12 and the output node NF12 and is turned on when the clock CK12 is at the H level. Also included is an N-type discharge transistor TG12 which is provided between the output node NF12 and VSS and is turned on when the clock CK11 is at the H level. That is, an inverted signal of the clock CK12 is input to the gate of the transistor TD12, and a non-inverted signal of the clock CK11 is input to the gate of the transistor TG12.

  When the clock CK11 is at H level (second voltage level) and the clock CK12 is at L level (first voltage level) as shown at B5, the inverted signal of CK11 is shown at B1. The transistor TD11 (first charge transfer circuit) input to the gate is turned on, and charge transfer from the charge storage node NC11 to the output node NF11 is performed. As indicated by B2, the transistor TG12 (second discharge circuit) to which the non-inverted signal of the clock CK11 is input is turned on, and the output node NF12 is discharged.

  On the other hand, when the clock CK12 is at the H level (second voltage level) as shown at B6 and the clock CK11 is at the L level (first voltage level), the inverted signal of CK12 is shown at B3. The transistor TD12 (second charge transfer circuit) that is input to the gate is turned on, and charge transfer from the charge storage node NC12 to the output node NF12 is performed. As indicated by B4, the transistor TG11 (first discharge circuit) to which the non-inverted signal of the clock CK12 is input is turned on, and the output node NF11 is discharged.

  As described above, according to the third modification, as shown by B1 and B4 in FIG. 15B, the period in which the charge transfer transistor TD11 of the voltage conversion circuit 40-11 is turned on and the discharge transistor TG11 are The on period is non-overlapping, and an off period as shown in B7 always exists between these periods. Therefore, it is possible to prevent a situation in which the accumulated charge of the charge accumulation node NC11 is discharged to the VSS side due to the through current through the transistors TD11 and TG11. Similarly, as indicated by B2 and B3 in FIG. 15B, the period in which the charge transfer transistor TD12 of the charge transfer circuit 40-12 is turned on and the period in which the discharge transistor TG12 is turned on are non-overlapping. Between these periods, an off period as indicated by B8 always exists. Therefore, it is possible to prevent a situation in which the accumulated charge of the charge accumulation node NC12 is discharged to the VSS side due to the through current through the transistors TD12 and TG12, and the boosting efficiency can be improved.

  In particular, the third modification focuses on the existence of non-overlapping clocks CK11 and CK12 necessary for the charge pump operation, and effectively utilizes these non-overlapping clocks CK11 and CK12 to prevent a through current. There is a feature. That is, the clocks CK11 and CK12 are mutually used between the voltage conversion circuits 40-11 and 40-12, and the transistor TD11 of the voltage conversion circuit 40-11 and the transistor TG12 of the voltage conversion circuit 40-12 are driven by the clock CK11. ON / OFF control. The transistor TG11 of the voltage conversion circuit 40-11 and the transistor TD12 of the voltage conversion circuit 40-12 are controlled to be turned on / off by the clock CK12 having a non-overlapping relationship with the clock CK11. In this way, the non-overlap relationship between the clocks CK11 and CK12 as shown in B5 and B6 can be effectively used to prevent the through current through the transistors TD11 and TG11 and the through current through the transistors TD12 and TG12. Boosting efficiency can be improved.

13. FIG. 16 shows a layout example (circuit pattern arrangement example) of the booster circuit of this embodiment. In FIG. 16, the charge pump units 20-1 to 20-N (first to Nth charge pump units) are arranged (laid out) along the direction D1 (first direction). For example, in the charge pump unit 20-1 (each charge pump unit), charge pump capacitors CA11 and CA12 (first and second capacitors) are arranged along the direction D1. That is, the capacitor CA12 is disposed adjacent to the capacitor CA11 on the D1 direction side. When the direction orthogonal to the D1 direction is the D2 direction (second direction), the capacitor CA11 and the voltage conversion circuit 40-11 are arranged along the D2 direction, and the capacitor CA12 and the voltage conversion circuit 40-12 are Arranged along the direction D2. The same applies to the other charge pump units 20-2 to 20-N.

  In FIG. 16, a circuit other than the capacitor CC11 of the voltage conversion circuit 40-11 (for example, the transistor of FIG. 15A) is provided between the capacitor CA11 (first capacitor) and the capacitor CC11 (first voltage conversion capacitor). TC11, TD11, TF11, TG11) are arranged. Further, a circuit other than the capacitor CC12 of the voltage conversion circuit 40-12 (for example, the transistors TC12 and TD12 in FIG. 15A) is provided between the capacitor CA12 (second capacitor) and the capacitor CC12 (second voltage conversion capacitor). , TF12, TG12) are arranged. The same applies to the other charge pump units 20-2 to 20-N.

  Here, the capacitors CA11 and CA12 are formed of high voltage capacitors. Similarly, the charge transfer circuit 30-1 is formed by a high voltage transistor. On the other hand, the voltage conversion capacitors CC11 and CC12 are formed of a low breakdown voltage capacitor having a breakdown voltage lower than that of the high breakdown voltage capacitor. Similarly, circuits other than CC11 and CC12 of the voltage conversion circuits 40-11 and 40-12 are formed by low breakdown voltage transistors having a breakdown voltage lower than that of the high breakdown voltage transistors. The same applies to the other charge pump units 20-2 to 20-N.

  In FIG. 16, a clock supply circuit 50 that generates and supplies a charge pump clock is arranged. For example, in the charge pump unit 20-1, voltage conversion circuits 40-11 and 40-12 are arranged between the capacitors CA11 and CA12 and the clock supply circuit 50. A wiring region is provided between the clock supply circuit 50 and the voltage conversion circuits 40-11 and 40-12. In this wiring area, signal lines including signal lines of clocks (CK11 to CKN2) supplied by the clock supply circuit 50 are wired. The same applies to the other charge pump units 20-2 to 20-N.

  According to the layout of FIG. 16, capacitors CA11 and CA12 are arranged along the direction D1. When the direction opposite to the D2 direction is the D4 direction (fourth direction), the voltage conversion circuit 40-11 is disposed on the D4 direction side of the capacitor CA11, and the voltage conversion circuit 40-12 is disposed on the D4 direction side of the capacitor CA12. Is placed. In this way, the voltage conversion circuits 40-11 and 40-12 can be arranged by effectively utilizing the space on the D4 direction side of the capacitors CA11 and CA12. The layout efficiency can be improved.

  Further, according to the layout of FIG. 16, high breakdown voltage elements (high breakdown voltage capacitors, high breakdown voltage transistors) such as capacitors CA11 and CA12 are arranged together in a high breakdown voltage region, and low breakdown voltage elements such as capacitors CC11 and CC12 (low With regard to the breakdown voltage capacitor and the low breakdown voltage transistor, they can be arranged together in the low breakdown voltage region. Then, only the distance relationship between the high withstand voltage region and the low withstand voltage region in FIG. Therefore, the layout efficiency can be improved and the layout area of the booster circuit can be reduced as compared with the method in which the high breakdown voltage element and the low breakdown voltage element are mixedly arranged.

  In FIG. 16, circuits other than CC11 and CC12 of the voltage conversion circuits 40-11 and 40-12 are arranged between the capacitors CA11 and CA12 and the capacitors CC11 and CC12. Therefore, an efficient layout along the signal flow becomes possible. That is, in FIG. 15A, signals corresponding to the clocks CK11 and CK12 are input to the lower electrodes of the capacitors CC11 and CC12. Transistors TC11, TD11, TC12, TD12, etc. are connected to the upper electrodes of the capacitors CC11, CC12. Therefore, according to the layout of FIG. 16, signal lines can be routed along the signal flow of the circuit of FIG. Therefore, it is possible to shorten the wiring length of the nodes NC11, NF11, NC12, and NF12 and connect them by a short path, and the parasitic capacitance of these nodes can be reduced. Thereby, the adverse effect of these parasitic capacitances on the boosting operation can be minimized.

  In FIG. 16, a wiring region is provided between the clock supply circuit 50 and the voltage conversion circuits 40-11 and 40-12. Therefore, the distance between the clock supply circuit 50 and the voltage conversion circuits 40-11 and 40-12 and the capacitors CA11 and CA12 can be further increased by at least the width of the wiring region in the direction D2. As a result, it is possible to prevent the clock noise generated in the clock supply circuit 50 from adversely affecting the charge storage nodes in the voltage conversion circuits 40-11 and 40-12 and the capacitors CA11 and CA12, thereby reducing the boosting efficiency. Can be prevented.

  In FIG. 16, when the direction opposite to the D1 direction is the D3 direction (third direction), the charge transfer circuit 30-1 is on the D2 direction side of the capacitor CA11 and on the D3 direction side of the capacitor CA12. Thus, layout efficiency can be further improved.

  That is, in FIG. 15A, since CA11 is a capacitor for controlling the gate of the transistor TA1, its capacitance value is smaller than that of the main capacitor CA12. For this reason, as shown in FIG. 16, the layout area of the capacitor CA11 is smaller than that of the main capacitor CA12. Therefore, in FIG. 16, the charge transfer circuit 30-1 is arranged by effectively utilizing the space on the D2 direction side of the capacitor CA11. In this way, the capacitors CA11 and CA12 and the charge transfer circuit 30-1 can be efficiently laid out so that no empty space is generated, and the layout efficiency can be improved.

  In FIG. 15A, the capacitor CC11 is provided corresponding to the capacitor CA11 having a small capacitance value, and the capacitor CC12 is provided corresponding to the main capacitor CA12 having a large capacitance value. For this reason, the capacitance value of the capacitor CC11 can be smaller than that of the capacitor CC12, and the layout area of the capacitor CC11 is smaller than that of the capacitor CC12.

  Therefore, in FIG. 16, the capacitors CC11 and CC12 are arranged so as to match the width of the capacitors CA11 and CA12 in the D2 direction. Then, the arrangement pitch of capacitors CA11, CA12, CA21, CA22... CAN1, CAN2 in the D1 direction is made to coincide with the arrangement pitch of capacitors CC11, CC12, CC21, CC22... CCN1, CCN2 in the D1 direction. Yes. By doing so, a layout without waste is possible, and the booster circuit can be reduced in size.

  In FIG. 16, a smoothing circuit and a limiter circuit 60 are disposed on the D1 direction side of the charge pump unit 20-N. A limit operation detection circuit 70 is disposed on the D4 direction side of the limiter circuit 60. In this case, the diode element DI of the limiter circuit 60 is set to a large size and has a large layout area. The P-type transistor TJ1 is also set to a large size and has a large layout area.

  17A and 17B show an example of a low breakdown voltage transistor and a high breakdown voltage transistor, and FIGS. 17C and 17D show an example of a low breakdown voltage capacitor and a high breakdown voltage capacitor.

  In FIG. 17A, a P-type well PWEL is formed on a P-type substrate PSUB. Then, an N-type low breakdown voltage transistor composed of the source and drain of an N + impurity layer (diffusion region), a gate oxide film, and a gate is formed in this PWEL. Note that the P-type low breakdown voltage transistor can be configured by, for example, forming an N-type well and forming a P + impurity layer, a gate oxide film, and a gate formed in the N-type well.

  On the other hand, in FIG. 17B, the P-type well PWEL is not formed in the P-type substrate PSUB. Then, an N-type high breakdown voltage transistor including a source and drain of an N + impurity layer, a gate oxide film, and a gate is formed directly on the PSUB. That is, in FIG. 17A, since PWEL has a high impurity concentration, the breakdown voltage of the PN junction is lowered, and a low breakdown voltage transistor is formed. On the other hand, in FIG. 17B, since PSUB has a low impurity concentration, the breakdown voltage of the PN junction can be increased and a high breakdown voltage transistor can be formed.

  The transistors TC11, TD11, TF11, TG11, TC12, TD12, TF12, and TG12 in FIG. 15A can be formed by a P-type low withstand voltage transistor (not shown) or an N-type low withstand voltage transistor in FIG. On the other hand, the transistors TA1 and TB1 can be formed by the high voltage transistor shown in FIG.

  In FIG. 17C, a P-type well PWEL is formed on a P-type substrate PSUB. In addition, a low breakdown voltage capacitor including an N + impurity layer serving as a lower electrode (clock CK input side) and a gate of a transistor serving as an upper electrode (clock CK ′ output side) is formed on the PWEL. . That is, a capacitor is formed using the gate capacitance of the transistor. An N + cross under impurity layer is provided below the gate and the gate oxide film in order to increase the capacitance value with a small layout area.

  On the other hand, in FIG. 17D, a high breakdown voltage capacitor including an N + impurity layer serving as a lower electrode and a gate of a transistor serving as an upper electrode is formed directly on a P-type substrate PSUB. That is, in FIG. 17C, since PWEL has a high impurity concentration, the breakdown voltage of the PN junction is lowered, and a low breakdown voltage capacitor is formed. On the other hand, in FIG. 17D, since PSUB has a low impurity concentration, the breakdown voltage of the PN junction can be increased and a high breakdown voltage capacitor can be formed. An N + cross under impurity layer is provided below the gate and the gate oxide film.

  The voltage conversion capacitors CC11 and CC12 in FIG. 15A can be formed by the low voltage capacitor in FIG. On the other hand, the charge pump capacitors CA11 and CA12 can be formed by the high voltage capacitors shown in FIG.

14 Nonvolatile Memory Device FIG. 18 shows a configuration example of a nonvolatile memory device including the booster circuit 540 of this embodiment. Note that the configuration of the nonvolatile memory device is not limited to that shown in FIG. 18, and various modifications such as omitting some of the components or adding other components are possible.

  In the memory cell array 500 (EEPROM), a plurality of nonvolatile memory cells are arranged in a matrix, for example. The address decoder 510 performs an address decoding process for selecting a word line of the memory cell array 500 and the like. The input / output unit 520 is a circuit for reading and outputting data stored in the nonvolatile memory cell of the memory cell array 500 and inputting data to be stored in the nonvolatile memory cell.

  The access control circuit 530 is a circuit for performing access control of the memory cell array 500. That is, at least one of writing, reading, and erasing of data in the nonvolatile memory cell of the memory cell array 500 is performed. The booster circuit 540 generates the boosted voltage VPP necessary for this access control. That is, the access control circuit 530 uses the boosted voltage VPP generated by the booster circuit 540 to control data writing to the nonvolatile memory cell.

  Note that the nonvolatile memory device in FIG. 18 can be incorporated in various electronic devices. For example, it can be incorporated in an electronic device such as a personal computer, a portable information terminal, a mobile phone, a printer, a scanner, a digital camera, a video camera, or a car navigation system. Alternatively, the nonvolatile memory device of this embodiment may be built in an electronic device such as an ink cartridge that can monitor the remaining amount of ink. In this case, when the printer is turned off, the non-volatile memory device performs the operation of writing the remaining ink amount data into the non-volatile memory cell based on the electric charge stored in the capacity of the power supply device. For this reason, the nonvolatile memory device is desired to have low power consumption, and the nonvolatile memory device including the booster circuit according to the present embodiment having low power consumption is the optimum memory device for such an electronic device as an ink cartridge. become.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or the drawings, terms (L level) described at least once together with different terms (first voltage level, second voltage level, first power source, second power source, etc.) having a broader meaning or the same meaning. , H level, VSS, VDD, etc.) can be replaced by the different terms anywhere in the specification or drawings. Further, the configuration of the booster circuit, the voltage conversion circuit, the nonvolatile memory device, and the drive waveform of the charge pump are not limited to those described in this embodiment, and various modifications can be made.

2 is a configuration example of a booster circuit according to the present embodiment. Explanatory drawing of the method of setting VPP to a high voltage at the time of test mode. 1 is a first configuration example of a test circuit. 2 shows a second configuration example of a test circuit. The structural example of a limiter circuit. Another configuration example of the booster circuit. An example of a boosted voltage signal waveform. An example of the configuration of a limit operation detection circuit. 3 shows a detailed configuration example of a booster circuit. The signal waveform diagram for demonstrating operation | movement of a voltage converter circuit. 11A and 11B are a configuration example of a voltage conversion circuit and an operation explanatory diagram thereof. The detailed structural example of a charge pump unit. The example of the drive waveform of a charge pump circuit. 14A and 14B show first and second modifications of the voltage conversion circuit. 15A and 15B are a third modified example of the voltage conversion circuit and an operation explanatory diagram thereof. An example of the layout of the booster circuit. 17A to 17D illustrate examples of a low breakdown voltage transistor, a high breakdown voltage transistor, a low breakdown voltage capacitor, and a high breakdown voltage capacitor. 1 is a configuration example of a nonvolatile memory device according to an embodiment.

Explanation of symbols

10 charge pump circuit, 12 booster circuit block,
20-1 to 20-N charge pump unit, 30-1 to 30-N charge transfer circuit,
40, 40-11 to 40-N2 voltage conversion circuit,
CA11 to CAN2 charge pump capacitors,
CC, CC11 to CC22 capacitor for voltage conversion,
CK11 to CKN2, RCK1 to RCKJ clock, 42 precharge circuit,
44 charge transfer circuit, 46 discharge circuit, 50 clock supply circuit,
52 decoder, 54 ring oscillator, 60 limiter circuit,
62 limit level adjustment circuit, 70 limit action detection circuit,
72 detection circuit, 73 load circuit, 74 output circuit, 80 test circuit,
82 test decoder, 84 transfer circuit,
500 memory cell array, 510 address decoder, 520 input / output unit,
530 access control circuit, 540 booster circuit

Claims (17)

A booster circuit block for generating a boosted voltage;
A limiter circuit for limiting the voltage difference between the boosted voltage at the output node of the booster circuit block and the voltage at the first power supply node to a limit voltage;
In the normal operation mode, the first power supply node is set to a first voltage level, and in the test mode, the first power supply node is set to a second voltage level higher than the first voltage level. A booster circuit comprising: a circuit; In claim 1,
The test circuit includes:
Including a buffer circuit to which a test instruction signal is input;
The buffer circuit is
A booster circuit that receives the test instruction signal and outputs a voltage setting signal of the second voltage level to the first power supply node when the test instruction signal becomes active in a test mode. . In claim 1,
The test circuit includes:
A transfer circuit which is provided between a test input terminal and the first power supply node and enters a transfer state in a test mode;
The transfer circuit is
In the test mode, the voltage setting signal of the second voltage level input to the test input terminal is output to the first power supply node, and the first power supply node is set to the second voltage level. A booster circuit characterized by that. In claim 3,
The test circuit includes:
A booster circuit comprising: a voltage setting circuit for setting the first power supply node to the first voltage level in a normal operation mode. In any one of Claims 1 thru | or 4,
The limiter circuit is
A diode element for setting a limit voltage provided between the output node and the detection node of the booster circuit block;
A booster circuit, comprising: a limit level adjustment circuit provided between the detection node and the first power supply node for adjusting a level of a limit voltage. In claim 5,
The limit level adjustment circuit includes:
A booster circuit comprising: a P-type first limit level adjusting transistor whose gate is supplied with a first power supply and whose drain is connected to the first power supply node. In claim 6,
The limit level adjustment circuit includes:
A booster circuit comprising at least one N-type second limit level adjusting transistor provided between the detection node and the first limit level adjusting transistor, the drain and gate of which are connected. . In any one of Claims 1 thru | or 7,
A clock supply circuit for generating a charge pump clock and supplying the charge pump circuit which is the booster circuit block;
Including a limit operation detection circuit for detecting a limit operation of the limiter circuit;
The limit operation detection circuit is
A booster circuit, wherein when a limit operation of the limiter circuit is detected, a stop signal for stopping clock generation of the clock supply circuit is activated and output to the clock supply circuit. In claim 8,
The limit operation detection circuit is
In the test mode, when the test circuit sets the first power supply node to the second voltage level, the stop signal is deactivated. In claim 8 or 9,
The limit operation detection circuit is
A detection circuit connected to a detection node of the limiter circuit;
An output circuit connected to the first output node of the detection circuit and outputting the stop signal to a second output node;
The detection circuit includes:
A load circuit provided between a second power source and the first output node;
A booster circuit comprising: an N-type detection transistor having a drain connected to the first output node and a gate connected to the detection node of the limiter circuit. In claim 10,
The test circuit includes:
In the test mode, when the first power supply node is set to the second voltage level, the source of the detection transistor is set to the second voltage level. In claim 10 or 11,
The output circuit is
When the limit operation of the limiter circuit is detected, the stop signal is activated, the limit operation of the limiter circuit is not detected, and the write signal to the nonvolatile memory device to which the boosted voltage is supplied is A booster circuit characterized in that, when active, the stop signal is deactivated. In any one of Claims 1 to 12,
The charge pump circuit, which is the booster circuit block,
Including first to Nth (N is an integer of 2 or more) charge pump units connected in series;
Each charge pump unit of the first to Nth charge pump units is:
A charge transfer circuit for transferring charge between capacitors for a charge pump;
A first capacitor for a charge pump, one end of which is connected to the charge transfer circuit;
A second capacitor for a charge pump, one end of which is connected to the charge transfer circuit;
A first conversion clock is provided between a first clock supply node to which a first clock is supplied and the other end of the first capacitor, and is obtained by boosting the voltage of the first clock. A first voltage conversion circuit that outputs to the other end of the first capacitor;
A second conversion clock is provided between a second clock supply node to which a second clock is supplied and the other end of the second capacitor, and is obtained by boosting the voltage of the second clock. And a second voltage conversion circuit that outputs to the other end of the second capacitor. In claim 13,
The first voltage conversion circuit includes:
A first voltage conversion capacitor provided between the first charge storage node and a first voltage change node whose voltage level changes based on a clock;
A first precharge circuit provided between a second power supply and the first charge storage node and precharging the first charge storage node;
Provided between the first charge accumulation node and the first output node, and transfers charges accumulated in the first charge accumulation node to the first output node in a first charge transfer period. A first charge transfer circuit;
A first discharge circuit that is provided between the first output node and a first power supply and discharges the first output node in a first discharge period;
The second voltage conversion circuit includes:
A second voltage conversion capacitor provided between the second charge storage node and a second voltage change node whose voltage level changes based on a clock;
A second precharge circuit provided between a second power supply and the second charge storage node and precharging the second charge storage node;
Provided between the second charge storage node and the second output node, and transfers the charge stored in the second charge storage node to the second output node in the second charge transfer period. A second charge transfer circuit;
And a second discharge circuit that is provided between the second output node and the first power source and discharges the second output node in a second discharge period. . In claim 14,
In the period in which the first charge transfer circuit of the first voltage conversion circuit performs charge transfer from the first charge accumulation node to the first output node, the second voltage conversion circuit The second discharge circuit discharges the second output node;
In the period in which the second charge transfer circuit of the second voltage conversion circuit performs charge transfer from the second charge accumulation node to the second output node, the first voltage conversion circuit The booster circuit, wherein the first discharge circuit discharges the first output node. In claim 15,
The first and second voltage conversion circuits are supplied with the first clock and the second clock in a non-overlapping relationship with the first clock,
When the first clock is at a second voltage level and the second clock is at a first voltage level, the first charge transfer circuit is connected to the first charge storage node from the first charge storage node. The second discharge circuit discharges the second output node, and charges are transferred to the output node.
When the first clock is at a first voltage level and the second clock is at a second voltage level, the second charge transfer circuit is connected to the second charge storage node from the second charge storage node. The booster circuit is characterized in that charge transfer to the output node is performed, and the first discharge circuit discharges the first output node. A memory cell array in which a plurality of nonvolatile memory cells are arranged;
And an access control circuit for performing at least one of writing, reading, and erasing of data of the nonvolatile memory cell based on the boosted voltage generated by the booster circuit according to claim 1. A non-volatile memory device.

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