JPS5219058A - Exclusive logical sum circuit - Google Patents

Exclusive logical sum circuit

Info

Publication number
JPS5219058A
JPS5219058A JP50094166A JP9416675A JPS5219058A JP S5219058 A JPS5219058 A JP S5219058A JP 50094166 A JP50094166 A JP 50094166A JP 9416675 A JP9416675 A JP 9416675A JP S5219058 A JPS5219058 A JP S5219058A
Authority
JP
Japan
Prior art keywords
logical sum
exclusive logical
sum circuit
exclusive
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50094166A
Other languages
Japanese (ja)
Inventor
Noboru Hagiwara
Yukio Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP50094166A priority Critical patent/JPS5219058A/en
Publication of JPS5219058A publication Critical patent/JPS5219058A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors

Landscapes

  • Logic Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)

Abstract

PURPOSE:An exclusive logical sum circuit which is designed so as to promote the high speed of operation and the degree of integration.
JP50094166A 1975-08-04 1975-08-04 Exclusive logical sum circuit Pending JPS5219058A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50094166A JPS5219058A (en) 1975-08-04 1975-08-04 Exclusive logical sum circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50094166A JPS5219058A (en) 1975-08-04 1975-08-04 Exclusive logical sum circuit

Publications (1)

Publication Number Publication Date
JPS5219058A true JPS5219058A (en) 1977-01-14

Family

ID=14102768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50094166A Pending JPS5219058A (en) 1975-08-04 1975-08-04 Exclusive logical sum circuit

Country Status (1)

Country Link
JP (1) JPS5219058A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4417161A (en) * 1980-09-04 1983-11-22 Matsushita Electric Industrial Co., Ltd. Complementary channel type MOS transistor exclusive OR/NOR logic gate circuit
JPS5916404A (en) * 1982-07-19 1984-01-27 Nippon Telegr & Teleph Corp <Ntt> Amplifying circuit
JPS6195617A (en) * 1984-10-17 1986-05-14 Hitachi Ltd Cmos logic circuit
JPS62106400U (en) * 1985-12-20 1987-07-07
US4749887A (en) * 1987-06-22 1988-06-07 Ncr Corporation 3-input Exclusive-OR gate circuit
JPH04154313A (en) * 1990-10-18 1992-05-27 Kikusui Electron Corp Band width limiting circuit
JP2012525774A (en) * 2009-04-30 2012-10-22 テラ イノヴェイションズ インコーポレイテッド XOR and XNOR logic circuit and layout

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50140255A (en) * 1974-04-30 1975-11-10

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50140255A (en) * 1974-04-30 1975-11-10

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4417161A (en) * 1980-09-04 1983-11-22 Matsushita Electric Industrial Co., Ltd. Complementary channel type MOS transistor exclusive OR/NOR logic gate circuit
JPS5916404A (en) * 1982-07-19 1984-01-27 Nippon Telegr & Teleph Corp <Ntt> Amplifying circuit
JPH0131327B2 (en) * 1982-07-19 1989-06-26 Nippon Telegraph & Telephone
JPS6195617A (en) * 1984-10-17 1986-05-14 Hitachi Ltd Cmos logic circuit
JPH0622328B2 (en) * 1984-10-17 1994-03-23 株式会社日立製作所 Semiconductor integrated circuit device having CMOS logic circuit
JPS62106400U (en) * 1985-12-20 1987-07-07
US4749887A (en) * 1987-06-22 1988-06-07 Ncr Corporation 3-input Exclusive-OR gate circuit
JPH04154313A (en) * 1990-10-18 1992-05-27 Kikusui Electron Corp Band width limiting circuit
JP2012525774A (en) * 2009-04-30 2012-10-22 テラ イノヴェイションズ インコーポレイテッド XOR and XNOR logic circuit and layout

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