JPH01307315A - Power-on reset circuit - Google Patents

Abstract

PURPOSE:To output a normal reset signal even if a hit takes place by discharging entirely the electric charge in a capacitor through a diode at the release of the reset signal. CONSTITUTION:If a potential of a positive power supply VDD is decreased, that is, a hit takes place in the positive power supply, the potential at a node (b) is lowered similarly and the potential at a node (a) is lowered, since the charge of the capacitor 5 is all discharged via a diode 2 at the release of the reset signal, almost no discharge time for the charge is required. When the positive power supply VDD rises again, the circuit state is similar to that at application of power and the reset signal is outputted to an output terminal 7 till the capacitor 5 is sufficiently charged by a resistor 1. Thus, the normal reset signal is outputted even to the decrease in the positive power supply for a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power-on reset circuit, and particularly to a power-on reset circuit in a semiconductor integrated circuit.

[Conventional technology]

Some power-on reset circuits used in semiconductor integrated circuits and the like consist of a resistor and a capacitor. An example of such a power-on reset circuit is shown in FIG.

In this conventional power-on reset circuit, a series-connected resistor 2L and capacitor 22 are connected between power supply terminals 24 and 25. Power supply terminal 25 is negative power supply V
SS, but the negative power supply VSS is at ground potential.

When the circuit is powered on, the positive power supply ■ is connected to the power supply terminal 24. . The potential of increases. At this time, since the capacitor 22 is not charged, current flows to the capacitor 22 via the resistor 21. As a result, the capacitor 22 is charged, and a reset signal is output from the output terminal 23.

[Problem to be solved by the invention]

In the conventional power-on reset circuit described above, the positive power supply V. When the potential of the capacitor 22 temporarily decreases, that is, when a momentary interruption occurs, the electric charge stored in the capacitor 22 is discharged to the positive power supply vDD only through the resistor 21, so that the discharge time becomes longer. For example, if the instantaneous interruption time of the positive power supply vDD is shorter than the discharge time, there is a drawback that the potential of the output terminal 23 does not drop sufficiently and a normal or cent signal cannot be obtained.

An object of the present invention is to eliminate such drawbacks and provide a power-on reset circuit that can output a normal reset signal even if a momentary power outage occurs.

[Means to solve the problem]

The present invention provides a power-on reset circuit that outputs a reset signal when the power is turned on, and includes a resistor and a capacitor for charging, a diode for discharging current, an inverter having a threshold value, and a power-on reset circuit that outputs a reset signal when the power is turned on. A P-channel MIS transistor and an N-channel MIS transistor are turned off, and one end of the resistor, the cathode electrode of the diode, the source electrode of the P-channel MIS transistor, and the positive power supply terminal of the inverter are connected to a positive power supply. The other end of the resistor, the anode electrode of the diode, and one electrode of the capacitor are connected to the input terminal of the inverter, and the other electrode of the capacitor and the P-channel M I S
The drain electrode of the door/star is connected to the N-channel type M.
Connected to the drain electrode of the IS transistor and connected to the N(7
The source electrode of the Janel type Mis transistor and the negative power supply terminal of the inverter are connected to a negative power supply, and the output terminal of the inverter is connected to the gate electrode and output terminal of the P channel type Mis transistor and the N channel type MIS transistor. It is characterized by

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. This power-on reset circuit consists of a resistor l and a capacitor 5 for charging, a diode 2 for flowing a discharge current, an inverter 4 having a threshold voltage, and a P-channel type MO3 for turning "on" and "off". (Metal Oxide Sem
(1 conductor) transistor 3 and an N-channel MOS transistor 6.

In such a power-on reset circuit, the positive power supply v
The power supply terminal 8 to which DD is connected has a P-channel type M
The source of the OS transistor 3, the cathode of the diode 2, one end of the resistor 1, and the positive power supply terminal V of the impark 4 are connected.

The anode of the diode 2, the other end of the resistor l, one end of the capacitor 5, and the input terminal of the inverter 4 are connected to the node a.

The drain of the P-channel MO8 transistor 3, the drain of the N-channel MOS transistor 6, and the other end of the capacitor 5 are connected to the node S.

The output terminal 7 is connected to the gate of the P-channel MO3 transistor 3, the gate of the N-channel MO3 transistor 3, and the output terminal of the inverter 4.

The source of the N-channel MOS transistor 6 and the inverter 4 are connected to the power supply terminal 9 to which the negative power supply VSS is connected.
is connected to the negative power supply terminal G of.

Note that in this embodiment, the negative power supply VSS is at the ground potential.

Next, the operation of this embodiment will be explained.

When the circuit is powered on, the positive power supply ■. . is a logical value “
0" to "1". At this time, the capacitor 5 is not charged, the potential at the node a is a logical value of "0", and the diode 2 is in the off state. The output of inverter 4 is logical “1” due to the potential of
Then, a reset signal is output to the output terminal 7. A rising signal with a logic value of "L" is input to the gates of the P-channel type MO3 transistor 3 and the N-channel type MO3 transistor RO, so that the P-channel MOS transistor 3 is in the OFF state and the N-channel type MO3 transistor RO is in the OFF state. becomes. As a result, the node S becomes the same potential as the negative power supply VSS, that is, the logical value is "O", and the capacitor 5 is charged with charge from the positive power supply VDtl via the resistor 1. When capacitor 5 is sufficiently charged and the potential at node a becomes higher than the threshold potential of inverter 4, inverter 4
The output becomes logical "0" and the reset signal is released.

This signal with a logic value of "0" is input to the gates of the P-channel type MOS transistor 3 and the N-channel type MO3 transistor RO, so that the P-channel type MOS transistor 3 is turned on and the N-channel type MOS transistor 6 is turned off. , the potential of the node S becomes equal to the potential of the positive power supply vIID. For this reason, the potential at node a becomes positive power supply ■ as the potential at node i increases. . However, since the diode 2 is forward biased, the charge stored in the capacitor 5 is discharged through the diode 2, and the potential of the node a becomes equal to the potential of the positive power supply vEll.

Here, positive power supply ■. When the potential of node S decreases, that is, when a momentary interruption occurs in the positive power supply, the potential of node S decreases as well,
Therefore, the potential at node a also decreases. However, since all the charges in the capacitor 5 are discharged when the reset signal is released, almost no charge discharge time is required. Then, when the positive power supply VDD rises again, the state is the same as when the power is turned on, and a reset signal is outputted to the output terminal 7 until the capacitor 5 is sufficiently charged by the resistor 1 again.

In the above embodiments, MOS transistors were used, but -
It is clear that a MIS transistor can be used for a.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to output a reset signal when the power is turned on normally, and
This has the effect that a normal reset signal can be output even when the positive power supply potential drops for a short time.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 2 is a circuit diagram showing an example of a conventional power-on reset circuit. 1... Resistance element 2... Diode 3... P channel type MO5 transistor 4... Inverter 5... Capacitor 6... N channel type MO3 transistor F... Output terminal agent Patent attorney Iwa Yoshiyuki Sa

Claims (1)

[Claims] (1) When the power is turned on, the power-on reset circuit outputs a reset signal, which consists of a resistor and capacitor for charging, a diode for discharging current, an inverter with a threshold value, and an "on" and "off" circuit. a P-channel MIS transistor and an N-channel MIS transistor, and connect one end of the resistor, the cathode electrode of the diode, the source electrode of the P-channel MIS transistor, and the positive power supply terminal of the inverter to a positive power supply. The other end of the resistor, the anode electrode of the diode, and one electrode of the capacitor are connected to the input terminal of the inverter, and the other electrode of the capacitor and the drain electrode of the P-channel MIS transistor are connected to the N connected to the drain electrode of the channel type MIS transistor, and connected to the drain electrode of the channel type MIS transistor;
The source electrode of the IS transistor and the negative power supply terminal of the inverter are connected to a negative power supply, and the output terminal of the inverter is connected to the gate electrode and output terminal of the P-channel MIS transistor and the N-channel MIS transistor. power-on reset circuit.