JPS60206319A - Circuit and method for reset at power-on time - Google Patents

Abstract

PURPOSE:To prevent breakdown of the operation by discharging the electric charge of a capacitor to only a circuit to be supplied, which is operated by a power source voltage, not to flow out this electric charge to external circuits when the power source voltage is varied. CONSTITUTION:When a power source is turned on at a time t0, power is supplied from an external power supply line 2a through a diode 11, and a potential V2 of an internal power supply line 2b rises quickly. At this time, since a capacitor 6 is charged through a resistance 12 because an n-FET13 is turned off, a potential V8 of a signal line 8 rises slowly from a time t1. When the potential V8 exceeds the threshold of an inverter consisting of n-FETs 15 and 17 at a time t3, a terminal 18 goes to the low level to terminate reset, and the circuit to be supplied is set to the operation state. If an accident or the like occurs in a power supply circuit connected to a terminal 1 at a time t4 to cause momentary reduction of the power source voltage and the potential difference between V2 and V8 reaches a threshold VTH of the n-FET13 at a time t5, the n-FET13 is turned on, and the electric charge of the capacitor 6 is discharged to the circuit to be supplied through the internal power supply line 2b. Therefore, reduction of the potential V2 is held down as shown by a solid line in the figure.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a supplied circuit (an internal circuit on a chip, such as a MOS FE
This relates to a reset circuit and a reset method for resetting a logic circuit (consisting of T, etc.) when the power is turned on.
In particular, it is used by being incorporated into an MO8 type integrated circuit.

[Technical background of the invention]

As a conventional example of a power-on reset circuit that resets the internal circuit of the chip when the power is turned on, for example,
1222251C is known. A conventional device will be described with reference to FIGS. 1 to 3 of the accompanying drawings.

In the following description of the drawings, the same elements are designated by the same reference numerals.-1-6 FIG. 1 is a circuit diagram of a reset circuit disclosed in Japanese Patent Application Laid-open No. 56-122225. A power source line 2 (not shown) is connected to the terminal 1 side, and a supplied circuit (chip internal circuit) operated by this power source is connected to the terminal 3 side. P-channel MO8FET (hereinafter referred to as rl'-FETJ) 4, 5 is connected between the power supply line 2 and the ground.
Eleven columns of capacitors 6 having a capacitance of several pF are connected. In addition, P-FET 7 is connected in parallel with P-FETs 4 and 5.
is connected, and one end of the capacitor 6 is connected to an input terminal of an inverter 90 via a signal line 8. The output terminal of the inverter 9 is connected to the gate terminal of the P-FET 7 and also to the input terminal of the inverter 10. An output terminal of the inverter 10 is connected via a signal line O to a terminal for inputting a reset signal of the supplied circuit.

FIG. 2 is an explanatory diagram of the operation of the configuration example shown in FIG. 1 after the power is turned on, and the horizontal axis represents time and the vertical axis represents voltage. In addition,
V2. V8 indicates the potential of the power supply line 2 and the signal line 8, respectively. When the power is turned on at t=to, the potential v2 of the power line 2 rises rapidly, and when the P-FET 4.5 is turned on at 1=11, current flows from the power line 2 to the capacitor 6. The potential 8 of the signal ffM8 increases as the capacitor 6 is charged. At this time, P-FE
If the combined resistance of T4.5 when it is on is R1, and the capacitance of capacitor 6 is C, then the rise in potential 8 follows the time constant R1C. Since the output of the inverter 9 is at a high level (hereinafter referred to as l1l (I+)) until the i-th position ■8 exceeds the threshold voltage of the inverter 9 (time 12 to t3), a reset signal is issued from the inverter 0. F
Since the output of the inverter 9 is applied to the gate of the ET 7, it is turned off.

1=1, when the potential ■8 reaches the threshold value of the inverter 9, the output of the inverter 9 is inverted and the sending of the reset signal is stopped. At the same time, P-FET 7 is turned on and i-capacitor 6 is charged via P-FET 7. Here, if the resistance of P-FET 7 is R2, the rise in potential ■8 is due to the time constant R1R2C/(R1+1
2) Since it follows K, it quickly moves up the line compared to times 1, -18.

[Problems with background technology]

As mentioned above, (according to the conventional device, the reset can be performed accurately when the power is turned on), but if there is a sudden change in the potential of the power line after the reset is completed, the internal potential will change accordingly. Operation failure may occur.

The above situation will be explained with reference to FIG. After t-13, both relatively high resistance P-FETs 4 and 5 and relatively low resistance 1)-FET 7 are turned on.

When the potential ■2 suddenly decreases when 1=1, P-F
Since ET 4, 5, and 7 are both on, the charge in the capacitor 6 flows through them to the power supply line 2, and the potential ■
8 also decreases rapidly.

If the capacitance of the capacitor 6 is increased, the voltage drop in the power supply line 2 can be prevented to some extent, but the discharged charge will flow through the terminal 1fc- to an external circuit with a large capacitance, so small potential fluctuations will occur. It is powerless against anything else. Furthermore, it is difficult to form a capacitor with a large capacity large enough to withstand discharge to an external circuit on a four-capacity semiconductor substrate due to space constraints, and externally attaching a capacitor is not preferable in terms of cost and the like.

Moreover, as shown in FIG. 3, the P-FET of the circuit of FIG.
4, 5, and 7 are n-channel MO8FETs (hereinafter 1'
-n-FETJ) 4', 5', and 7', and in which the inverter 9 is replaced by a non-inverting buffer 9', the voltage stabilizing effect of the capacitor 6 cannot be expected at all. This is because there is an accident in the power line 2 and the potential V2
This is because when the voltage suddenly decreases, the n-FET 7' is turned off and the charge in the capacitor 6 is not released to the power supply line 2.

[Purpose of the invention]

The present invention has been made to overcome the above-mentioned drawbacks of the prior art, and is designed to prevent the operation of a supplied circuit operated by this power supply voltage from being disrupted even if instantaneous fluctuations occur in the power supply voltage. An object of the present invention is to provide a power-on reset circuit and a power-on reset method.

[Summary of the invention]

In order to achieve the above object, the present invention provides a capacitor that starts charging when power is turned on to a supplied circuit that operates with power supplied via a power line, and a capacitor that starts charging when the power supply voltage fluctuates after reset is completed. Release the charge of the capacitor to the supplied circuit! To provide a power-on reset circuit and a method thereof, which includes a discharging means such as a FET, and a blocking means such as a diode to prevent the discharged charge from flowing out to an external circuit via a power supply line. It is.

[Embodiments of the invention]

Hereinafter, some embodiments of the present invention will be described with reference to FIGS. 4 to 8 of the accompanying drawings. FIG. 4 is a circuit diagram of one embodiment. Between an external power supply line 2a connected to an external power supply circuit (not shown) via terminal 1 and an internal power supply line 2b connected to a supplied circuit (not shown) via terminal 3,
A diode 11 with the terminal 1 side as an anode is provided to prevent the discharged charge of the capacitor 6 from flowing out to an external circuit. Internal power supply line 2b and one end of capacitor 6 (
A resistor 12 and an n-FET 13 are connected in parallel to the signal line 8), and the gate terminal of the n-FET 13 is connected to the capacitor 6.
Connect to one end (signal line 8) of Here, the resistor 12 limits the charging current to the capacitor 6, and has a relatively high resistance. Also, n-FET 13it.

When the power supply voltage fluctuates, the charge in the capacitor 6 is transferred to the internal power supply line 2b.
It is for discharging from the source to the supplied circuit, and it is desirable to keep the threshold value small so that it can be turned on quickly when the power supply voltage fluctuates.

One end of the signal line 8 is connected to the gates of n-FETs 15 and 16, and this enhancement type n-FE
T15 and depression type n-FET17, Jl
1 inverter is configured. The output of this inverter is sent via terminal 18 as a reset signal to a supplied circuit (not shown).

FIG. 5 is an explanatory diagram of forming the capacitor 6 of FIG. 4 on a semiconductor chip. The circuit shown in FIG. 4 and the supplied circuit are formed on the semiconductor chip 121, and the remaining space 22~
A MOS capacitor is formed at 25, and this is designated as capacitor 6 in FIG. Here, we will consider the minimum capacitor capacity that can contribute to stabilizing the power supply against instantaneous power supply voltage fluctuations. Here, ``instant-1'' is the minimum unit of time in the system, which is 1 clock time (≧l0-7
sec). Recent n-channel MO8FET
Since the current consumption is at least about 50 mA (VDD = 5 V), the resistance seen from the internal power supply line 21 is about 100Ω. Assuming that no voltage is supplied from the external circuit for one clock and the charge in the capacitor 6 flows to the internal power supply line 2b without resistance, the voltage at the terminals of the capacitor 6 should not fall below 60% of the original voltage value during that period. In order to achieve this (to support the operation of the supplied circuit), the capacitance of the capacitor 6 must be 1 nF or more.

FIG. 6 is an explanatory diagram of the operation of the embodiment shown in FIGS. 4 and 5 when the power is turned on. When the power is turned on at i=i, , power is supplied from the external power line 2a through the diode 11, and the internal sI! The potential 2 of the source line 2b rises rapidly. At this time, since the n-FET 13Fi is off, the capacitor 6 is charged via the resistor 12, so the potential 8 of the signal line 8 slowly rises from 1=11. Here, if the resistance value of the resistor 12 is R3 and the capacitance of the capacitor 6 is C, the potential v8 will rise according to the time constant R3C.

1=1, the potential V8 is n −FET 15 , 1
When the threshold value of the inverter constituted by 7 is exceeded, the terminal 18 becomes IILll, the reset is completed, and the supplied circuit (not shown) becomes operational. In addition, n-FET13
remains off.

1 = 14, an accident or the like occurs in a power supply circuit (not shown) connected to terminal l, and an instantaneous voltage drop occurs in the power supply voltage. At this point, the potential (2) drops rapidly, but since the n-FET 13 is off and the resistor 12 has a high resistance, the charge in the capacitor 6 is only slightly discharged. Therefore, the drop in potential (18) can be suppressed to a small extent.

1=1. The potential difference between V2 and ■8 is n-FET
When the threshold VTI of 13 is reached, n-FET13
is turned on, and the charge in the capacitor 6 is released to the supplied circuit via the internal power supply line 2b. (Due to the diode 11, the discharged charge does not flow out to an external circuit with a large capacity). Therefore, the drop in the potential (2) is suppressed as shown by the solid line in the figure (if there is no discharge from the capacitor 6, the potential decreases significantly as shown by the broken line in the figure).

At 1=16, the fluctuation (decrease) in the power supply voltage recovers, and the difference between potentials ■2 and ■8 becomes the threshold value VTR' of n-FET13.
When the voltage drops below e, the n-FF, T]3 is turned off and the discharge of the capacitor 6 is stopped.

As described above, according to the embodiment shown in FIG. 4, even if there is a sudden drop in the power supply voltage, the voltage drop in the internal power supply line 2b and the signal line 8 can be suppressed to a small level.

Furthermore, when the supplied circuit is reset early, the reset can be completed based on the requested pressure.

In the embodiment shown in FIG. 4, the n-FWT 13 may be replaced with a diode whose cathode is on the internal power supply line 2b side. Furthermore, when using an SO8 substrate, leakage current to the substrate can be eliminated, so the resistor for charging the capacitor 6 is omitted and the n-FET for discharging is replaced by a diode 31, It can also be replaced with 32. Further, the resistor 12 can be formed of a diffused resistor or a MOS FET.

FIG. 8 is a circuit diagram of another embodiment of the present invention.

Resistor 12 for capacitor charging, n- for capacitor discharge
n-FET41 for capacitor charging in parallel with FET13
are provided, and the n-FETs 15 and 16 are connected in parallel to each other. Further, a control signal sent from a supplied circuit (not shown) is transmitted via a terminal 42 and a non-inverting buffer 43.
-FET 41. , 16 gates. Note that the n-FETs 15, 16, and 17 constitute a NOR circuit. The diode 11 may be provided outside the semiconductor substrate.

FIG. 9 is an explanatory diagram of the operation of the embodiment shown in FIG. 8 when the power is turned on. Two tons. When the power is turned on at
Power is supplied through the internal power supply line 2b, and the potential 2 of the internal power supply line 2b rises rapidly. At this time, n-FET 13
, 41 are both off, so the capacitor 6 is charged via the resistor 12, so the potential V8 of the % signal line 8 is 1.
It rises slowly from =11. Here, if the resistance value of the resistor 12 is R3 and the capacitance of the capacitor 6 is C, then
The potential (18) will rise according to the time constant R3C.

1=1, the potential V8 is n −FET 15 , 1
6.

When the threshold value of the NOR circuit composed of 17 is exceeded, the terminal 18 goes to ``L''K, the reset is completed, and the supplied circuit (not shown) becomes in the operating state.At this time, the supplied circuit becomes the II HI+ When a control signal is generated and applied to the non-inverting buffer 43 via the terminal 42, n
- The gate of FET 41 becomes 11) (II and turns on. Therefore, the charge of capacitor 6 is discharged through n-FET 41. When the on-state resistance of n-FET 41 is set to R4
Then, the potential ■8 has a time constant of 1 (3R4C/(R30R
4), it quickly approaches potential 2. Therefore, the circuit operation (especially n-FET 1
5, 16, 17, etc.) are less likely to become unstable (in the circuit shown in Figure 4, the time constants R and C are large and ■8 rises slowly, so the inverter is likely to reverse due to a small fluctuation in V3). .

When a momentary voltage drop occurs in the power supply voltage at 1=14, V
Cn-FET 13 turns on and internal power supply 11! !
2b and signal line 8 should be suppressed.

When an instantaneous voltage rise occurs in the power supply voltage 1 at 1=17, both n-FETs 13 and 41 are off, so the potential 2 rises rapidly, but the potential v8 rises only a little. .

Potential ■2 at 1=18. The difference in v8 is n-FET41
When the threshold voltage V'TH is exceeded, the gate of the n-FET 41 is inverted from the off state to the on state because II) (11 is applied from the non-inverting buffer 43).

Therefore, a charge of 6 VC flows into the capacitor from the internal power supply line 2b via the n-FET 41, and the rise in the potential 2 is suppressed.

1=1. The voltage fluctuation subsides at voltage v2. ■8
) Differential power n-FET 41 no L When the voltage falls below the key value voltage V'TH, the n-FET 41 is inverted from the on state to the off state.

As described above, according to the embodiment shown in FIG. 8, even when power fluctuation occurs in the direction of voltage increase, it is possible to effectively stabilize the power supply. In addition, in FIG. By connecting about 8 diodes in series with the ground side being n-type, or vice versa, connecting one diode in series between the external power supply line 2a will provide reliable protection against voltage increases on the external power supply line 2a. .

〔Effect of the invention〕

As described above, according to the present invention, when a fluctuation occurs in the power supply voltage, the load of the capacitor is released only to the supplied circuit operated by the power supply voltage, and does not leak to the external circuit. Therefore, it is possible to obtain a power-on reset circuit and a reset method that prevents the operation from failing even if there is an instantaneous voltage fluctuation in the power supply voltage. In addition, by providing a charging means that becomes conductive after the reset of the supplied circuit and supplies charge from the power supply line to the capacitor, it is possible to
NI) Due to power fluctuations near the threshold voltage of the circuit, etc.
This can reduce instability in circuit operation,
(2) The end of the reset can be determined at the request of the supplied circuit, and (2) the power supply can be stabilized even when the power supply voltage fluctuates in the direction of voltage rise.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of one configuration example of a conventional device, and FIG. 2 is an explanatory diagram of the operation of the configuration example shown in FIG. 1 when the power is turned on. 3 is a circuit diagram of another configuration example of the conventional device, FIG. 4 is a circuit diagram of an embodiment of the present invention, and FIG. 5 is an explanatory diagram of forming the capacitor 6 shown in FIG. 4 on a semiconductor chip. Figure 6 is the 4th
7 is a circuit diagram of another embodiment of the present invention, FIG. 8 is a circuit diagram of still another embodiment of the present invention, and FIG. FIG. 9 is an explanatory diagram of the operation of the embodiment shown in FIG. 8 when the power is turned on. 2...Power line, 2a...External power line, 2b...Internal power line, 4,5.7...P channel MO8FET
. 6... Capacitor, 9, 10... Inverter, 4'
. 5', 7', 13, 15, 16, 17.41...
・11 channel MO8FET0 Applicant's agent Kiyoshi Inomata

Claims (1)

[Scope of Claims] 1. When power is supplied to a circuit to be supplied which is operated by power supplied via a power supply line, a capacitor is charged by the voltage of the power supply line 17), and the charging voltage of this capacitor is set to a predetermined voltage. a reset signal sending means for sending a reset signal to the supplied circuit until a reset signal reaches the supplied circuit; and when a voltage fluctuation of the power supply line occurs after the reset of the supplied circuit is completed, the charge of the capacitor is discharged to the supplied circuit. A power-on reset circuit comprising a discharging means for discharging the capacitor, and a blocking means for preventing the discharged charge of the capacitor from flowing out to the power supply line. 2. In a power-on reset circuit for a supplied circuit that operates with power supplied via a power supply line, a capacitor having a sufficient capacity compared to the charge capacity of the supplied circuit; a resistance circuit for restricting the flow of charging charge supplied from the capacitor to the capacitor; a reset signal sending means for sending a reset signal to the supplied circuit until the charging voltage of the capacitor reaches a predetermined value; Discharging means for discharging the charge of the capacitor to the supplied circuit when a voltage fluctuation occurs in the power supply line after the reset of the supplied circuit connected in parallel, and the discharged charge of the capacitor flowing out to the power supply line. and a power-on reset circuit. 3. The reset signal sending means includes an inverter that inputs the terminal voltage of the capacitor.
The power-on reset circuit described in section. 4. The power-on reset circuit according to claim 2 or 3, wherein the discharge means includes an FET that inputs the terminal voltage of the capacitor to its gate. 5. The power supply according to any one of claims 2 to 4, wherein the blocking means is a diode inserted between the power supply line and a common connection point of the supplied circuit, the resistance circuit, and the discharge means. On-state reset circuit. 6. In a power-on reset circuit for a supplied circuit that operates with power supplied via a power supply line, a capacitor having a sufficient capacity compared to the charge capacity of the supplied circuit; a resistor circuit for restricting the flow of photoelectric charge supplied from the capacitor to the capacitor; a reset signal sending means for sending a reset signal to the supplied circuit until the charging voltage of the capacitor reaches a predetermined value; and the resistor circuit. a charging means that is connected in parallel to the resistor circuit and becomes conductive after the reset of the supplied circuit is completed to supply photoelectric charge from the power supply line to the capacitor; a power-on reset circuit comprising a discharging means for discharging the charge of the capacitor to the supplied circuit when a voltage fluctuation occurs; and a blocking means for preventing the discharged charge of the capacitor from flowing out to the power supply line. . 7. Claim box 6, wherein the reset signal sending means includes an inverter that inputs the terminal voltage of the capacitor.
The power-on reset circuit described in section. 8. The power-on reset circuit according to claim 6 or 7, wherein the discharging means includes an FET that inputs the terminal voltage of the capacitor to its gate. 9. According to any one of claims 6 to 8, the blocking means is a diode inserted between the power supply line and a common connection point of the supplied circuit, the resistance circuit, and the discharge means. Power-on reset circuit. 10. The photoelectric means inputs into a gate a reset end signal sent from the supplied circuit at the end of reset.
A power-on reset circuit according to any one of claims 6 to 9, comprising an ET. 11. In a power-on reset method for a supplied circuit operated by power supplied via a power supply line, after the power is turned on, a capacitor is charged by the voltage of the power supply line via a resistor circuit, and the supplied circuit A power-on reset method for discharging the charge of the capacitor to the supplied circuit when a voltage fluctuation occurs in the power supply line after the completion of the reset, and preventing the charge of the capacitor from flowing out to the power supply line. 12. In a power-on reset method for a supplied circuit operated by power supplied via a power supply line, after the power is turned on, a capacitor is photoelectrically charged by the voltage of the power supply line via a resistor circuit, and the supplied circuit After the reset is completed, a charging means connected in parallel to the resistor circuit is made conductive to charge the capacitor with the voltage of the power supply line, and when a voltage fluctuation occurs in the power supply line after the reset of the supplied circuit is completed, A power-on reset method that discharges the charge in the capacitor to the supplied circuit and prevents the charge in the capacitor from flowing out to the power supply line.