JPH01105612A - Complementary mos integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a logical circuit, in which the peak value of a transient current is suppressed to be the current value of a constant current source due to a current mirror, and in addition, a current does not flow in a logical part at the time of a stationary state, and the current is low, and in addition, the transient current is small as well by inserting the current mirror circuit constitution respectively on the ways to a positive and a negative power sources. CONSTITUTION:P-channel transistors(TRs) 16-18, N-channel TRs 20-22 and a resistor 19 are added. Then, the current proportional to a bias current to flow in the TRs 16, 20 and the resistor 19 is intended to flow in the respective positive and the negative power source terminals of an inverter 4 and a NAND 5 by the TRs 16, 17, 18 and the TRs 20, 21, 22 to constitute the current mirror. Thus, the maximum value of the transient power source current in the inverter 4 can be suppressed within the constant value of the TRs 17, 21. Besides, as for the NAND circuit 5 as well, in the similar way to the inverter 4, the maximum value of the transient power source current can be suppressed within the constant current value of the TRs 18, 22.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a complementary MOS logic circuit, and more particularly to a complementary MO3 integrated circuit that reduces unnecessary radiation due to power supply transient currents.

[Conventional technology]

Complementary MOS (hereinafter referred to as CMOS) integrated circuits have become finer and faster, and some can operate as fast as conventional bipolar integrated circuits. Although 0MOS generally has low power consumption, it is known that a transient current flows into the power supply during switching. Due to this transient current, considerable power is consumed during high-speed operation, and 100mV
This also caused a voltage drop in the power supply of the machine.

[Problem to be solved by the invention]

FIG. 5 is an example of a logic circuit. In the figure, the input terminal 1 is connected to the input of the inverter 4, and the output of the inverter 4 and the input terminal 2 are connected to the input of the NAND 5. The output of NAND5 is connected to output terminal 3.

FIG. 6 is a circuit diagram in which the above logic circuit is realized by a conventional 0MO3. In the same figure, inverters 4 and N
A stray capacitance of 10°l5 exists at each output of AND5. For example, when input 1 is high, transistor 8 is 0.
Since the transistor 9 is FF and the transistor 9 is ON, the output of the inverter 4 is 4-, and the stray capacitance 10 is discharged. The next time input 1 falls low, transistor 8 goes low.
At N, transistor 9 is turned off, and the output of inverter 4 rises to high. Therefore, since the stray capacitance 10 is rapidly charged from the power supply terminal 6 via the transistor 8, a transient current flows. Similarly, when the output of the inverter 4 falls, the discharge current of the stray capacitance 10 flows through the transistor 9. Furthermore, charging and discharging of the floating capacitor 15 occurs in accordance with changes in the output of the NAND circuit 5.

The collection of such transient currents generates a transient current at terminals 6 and 7, which causes a voltage drop due to the resistance or inductive inductance (hereinafter abbreviated) of the wiring and lead wires of the integrated circuit, and as described above. It may reach 100mV range. Normally, to prevent this, a bypass capacitor is inserted between the power supply terminals 6 and 7 (not shown), but the resistance of the lead wire, the wiring or the bypass capacitor's L
cannot be canceled out. In particular, as devices become faster, the influence of L is increasing, and at the terminals of integrated circuits
A voltage drop on the order of 0 mV occurs, and the voltage drop in the power supply wiring inside the integrated circuit may be several 100 mV.

Such large high frequency energy is easily radiated and T
The disadvantage is that not only does it cause interference to V and radios, but also the integrated circuit itself may malfunction.

The purpose of the present invention is to improve the above-mentioned drawbacks by providing a constant current source that suppresses the peak of transient current.
An object of the present invention is to provide a complementary MOS integrated circuit.

[Means to solve the problem]

The complementary MOS integrated circuit of the present invention is an integrated circuit having a complementary MOS logic circuit, and includes a P-channel MO3) transistor whose drain is connected to the positive power supply terminal of the logic circuit, and a P-channel MO3) transistor whose drain is connected to the positive power supply terminal of the logic circuit. an N-channel MOS transistor whose drains are connected, and a source of the P-channel MOS) transistor, the sources of the P-channel MOS) transistor are commonly connected to a positive power supply; The transistors are configured such that their sources are commonly connected to a negative power supply and a predetermined bias voltage is applied to the gates of each of the transistors.

〔Example〕

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. This figure is a circuit diagram in which the present invention is applied to the aforementioned logic circuit (see FIG. 5). The elements added according to the present invention are P channel transistors 16-18°, N channel transistors 20-22 and resistor 19. Transistor 1 constitutes a current mirror, and a current proportional to the bias current flowing through transistors 16, 20 and resistor 19.
6.degree. 17.18 and transistors 20, 21.22 to flow to the positive and negative power supply terminals of the inverter 4 and NAND 5.

When terminal 1 is high, transistor 8 is off and transistor 9 is on, and transistor 21 attempts to flow a constant current, but since the drain-source voltage is O, no current flows.

Next, when the terminal 1 is made low, the transistor 9 is turned off and the transistor 8 is turned on, and the stray capacitance 10 is charged with a constant current from the transistor 17 through the transistor 8, and the voltage across the floating capacitor 10 is brought close to the power supply voltage.

Then, the voltage between the drain and source of the transistor 17 becomes low, and this transistor enters the triode region, and the drain current decreases. When charging is completed, the voltage across the stray capacitance 100 becomes equal to the power supply voltage, so the voltage between the drain and source of the transistor 17 becomes 0, and no current flows. At this time, since transistor 9 is off, no current flows through transistor 21 either.

When the terminal l goes high again, the stray capacitance that was just charged is 10
The charge rises to the transistor 21 via the transistor 9 and is discharged at a constant current, and when the discharge is completed, the current becomes O.

In this way, the maximum value of the transient power supply current can be suppressed by the constant current value of the transistor 17.21. Therefore, a large current as in the conventional case does not flow.

Furthermore, when the input to terminal 1 rises slowly, transistors 8 and 9 are both turned on when an intermediate potential is taken midway through, so conventionally a large current flows from the positive power source to the negative power source, but the present invention Then, it is suppressed by transistors 17 and 21. The current at this time is the transistor 17
．． This is the smaller of the 21 currents. From this point of view as well, transient current can be suppressed.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. In this figure, a circuit for obtaining an oven drain output from a P-channel transistor 26 at a terminal 27 is added to the logic circuit described above (see FIG. 5). When discharging the charge accumulated in the floating capacitor 828, even if the transistor 26 is turned on, the transistor 25 has a constant current, so a constant current discharge is performed. Note that conventionally, since the transistor 25 is not provided, when the transistor 26 is turned on, a large current flows which is limited by its on-resistance.

In addition, in FIG. 2, a current proportional to the current flowing through the resistor 23 is transferred to the transistors 21 and 22 by current mirror operation.
The current mirror circuit consisting of transistors 16, 17, 18, and 25 attempts to cause a constant current to flow through transistor 21. As mentioned above, the peak value of the transient current in each stage is given by the above constant current,
It is O during steady state. By increasing the value of the resistor 23, the transient current can be reduced, and by decreasing the value of the resistor 23, the transient response (the charging/discharging time of the stray capacitance) can be accelerated. Therefore, by using the resistor 23 as an LSI or an external device, it is possible to use it for low transient current or high speed depending on the purpose.

Note that the NAND circuit 5 also operates in the same manner as the inverter 4 and can exhibit the same effects.

For example, in FIG. 2, if we consider the case where the output terminal 27 is short-circuited to the negative power supply while the transistor 26 is on, the transistor 25
Therefore, due to the current mirror operation described above, a constant current determined by the size ratio of transistors 25 and 160 flows. On the other hand, if there is no transistor 25 as in the conventional case, a large current determined by the on-resistance of the transistor 26 will flow. Therefore, in FIG. 2, a so-called drooping current limiting operation is performed to prevent a large current from flowing down when the load is short-circuited.

Of course, in FIG. 1 as well, it is clear that the current when the load is short-circuited is suppressed to the constant current value that can flow through the transistor 8 or the transistor 22.

FIG. 3 shows a third embodiment of the invention. An input terminal 31 is connected to the input terminal of an analog circuit 32, such as an operational amplifier, and an N-channel transistor 3F, which functions as an optical follower, is connected to the output terminal. Bias power supply 3 for N-channel transistor
N-channel transistor 4 that performs constant current operation by 9
0 are connected in series, and an output terminal 38 is provided at the connection point. N-channel transistor 40 serves as a DC bias for N-channel transistor 37. Conventionally, the drain of the N-channel transistor 37 was directly connected to the power supply terminal 35, and the N-channel transistor 37 was operated as a source follower type output circuit. For example, if the output terminal 38 is at a relatively high voltage and is shorted to the negative power supply terminal 41, the gate of the N-channel transistor 37
The source-to-source voltage increases, the transistor 37 turns on, and a large current determined by the on-resistance flows. Therefore, according to the present invention, by using a current mirror circuit consisting of a resistor 36 and P-channel transistors 33 and 34, the maximum current that can flow through the transistor 37 is transferred to the transistor 34.
can be limited to a constant current value of In addition, output terminal 3
Although the transistor 34 is in the on state when the transistor 8 is not short-circuited, only the current of the transistor 37 forming the source follower (normally the same as the current of the constant current transistor 4o) flows, and the source current of about 0.1 V flows.
The voltage between the drains becomes high, and the source follower operates as before.

Second, FIG. 4 shows a specific example of the embodiment of the first apricot. Figure 4 is C
The present invention is implemented in a MOS operational amplifier. Differential unlangers 46, 47 connected to inputs 31, 42
．． N-channel transistor 48 receives the output and operates as a common source. Transistors 54, 55, . There is an operational amplifier consisting of transistors 43 and 51 forming a constant current circuit. In order to limit the output current of such an operational amplifier, the transistor 34 is connected to the power supply terminal 35 and the output transistor 5.
Likewise, a transistor 53 is connected between the ground terminal 41 and the drain of the output transistor 54.

The method of limiting the output current is that the transistors 34 and 53 act as current mirrors and cannot allow a current exceeding a certain level to flow, which is the same principle as in each of the embodiments described above.

Note that the output circuit of the present invention is not limited to the above-described embodiments, and may be any circuit in which a current mirror circuit configuration is inserted between the positive and negative power supplies.

〔Effect of the invention〕

According to the present invention, the peak value of a transient current can be suppressed to the current value of a constant current source using a current mirror, and no current flows in the logic section during steady state, so that a logic circuit with extremely low current and little transient current can be created. It is possible to provide a circuit in which a large current does not flow even when the output voltage is off.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a first embodiment of the present invention, Fig. 2 is a circuit diagram showing a second embodiment of the invention, and Fig. 3 is a circuit diagram showing a third embodiment of the invention. , Fig. 4 is a circuit diagram showing a specific example of the third embodiment, Fig. 5 is a circuit diagram showing a conventional example, and Fig. 6 is a circuit diagram showing a specific example of the third embodiment.
The figure is a specific circuit diagram of a conventional example. 1.2,31...Input terminal, 3,27...
...Output terminal, 4...Inverter, 5...
・・NAND, 6゜7・・・・Power terminal, 16~1
8, 25, 26, 33° 34.43 ~ 45, 51, 54
...P-channel MoS transistor, 22,2
3, 37, 40° 46-48, 50, 55...
N-channel MOS) transistor, 32... operational amplifier. Agent Patent Attorney Uchihara Otokan 1 Kunika;! I! 1 5th ``Kayaotsumen''

Claims (1)

[Claims] In an integrated circuit having a complementary MOS circuit, a P-channel MOS whose drain is connected to the positive power supply terminal of the circuit
a transistor, and an N-channel MOS transistor whose drain is connected to a negative power supply terminal of the circuit, the sources of the P-channel MOS transistors are commonly connected to a positive power supply, and the sources of the N-channel MOS transistors are commonly connected to a positive power supply. A complementary MOS integrated circuit, characterized in that it is connected to a negative power supply and a predetermined bias voltage is applied to the gate of each of the transistors.