JPS63124616A - Multiplexer - Google Patents

Abstract

PURPOSE:To constitute a multiplexer with priority and a few number of transistors (TR) by constituting the titled multiplexer by a 1st metal oxide film field effect TR MOSFET, a complementary conduction MOSFET and a 2nd MOSFET and using a 2nd electrodes of a 1st MOSFET and the 2nd MOSFET as the outputs. CONSTITUTION:With a 1st control line 1 at logic 'H', the 1st NMOSFET 5 is turned on and the logic state of a 1st signal line 3 is selected. With the 1st control line 1 at logic 'L' and the a control line at logic 'H', although the 1st NMOSFET 5 is turned off, the PMOSFET 7 is turned on and the NMOSFET 8 is turned off. Then the 2nd NMOSFET 6 is turned on to give logic 'H' of a 2nd control line 2 to the gate terminal of the 2nd NMOSFET 6 and only the logical state of a 2nd signal line 4 is selected. That is, either the 1st signal line 3 or the 2nd signal line 4 is selected optionally by controlling the level of the 1st and 2nd control lines 1, 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiplexer that has priority and requires a small number of transistors to be constructed.

[Conventional technology]

FIG. 2 is a diagram showing the configuration of a conventional multiplexer in which priorities are assigned to control lines. In this figure, 1 is a first control line, 2 is a second control line with a lower priority than the first control line 1, 3 and 4 are the first and second signal lines, and 5 is the first control line. A first N-channel metal oxide field effect transistor (hereinafter N-channel metal oxide field effect transistor is referred to as NMOSFET) has a control line 1 connected to a gate terminal and a first signal line 3 connected to a first electrode. ), 6 is a second N signal line to which the second signal line 4 is connected to the first electrode.
MOSFET, 9 is an inverter circuit connected to the second control line 2, 10 is a NOR whose input is connected to the output of the inverter circuit 9 and the first control line 1.
The circuit 11 is the output of a multiplexer in which the second electrode of the first NMOSFET 5 and the second electrode of the second NMOSFET 6 are connected.

Next, the operation will be explained.

When the first control line 1 and the second control line 2 are at logic "L", both the first NMOSFET 5 and the second NMOSFET 6 are turned off, and the logic of the first signal line 3 and the second signal line 4 is No state is selected.

When the first control line 1 is at logic “H”, the first NMOSF
ET5 is turned on and the logic state of the first signal line 3 is selected for the output 11 of the multiplexer. However, at this time, regardless of the state of the second control line 2, the second NMOSFET
6 is turned off and the logic state of the second signal line 4 is not selected. When the first control line 1 is at logic "L" and the second control line 2 is at logic "H'", the first NMOSFET 5 is turned off, the second NMOSFET 6 is turned on, and the second signal line 4 The logical state of is selected.

[Problems to be Solved by the Invention] In the conventional multiplexer as described above, two elements are used to prioritize the first and second control lines 1 and 2.
An inverter circuit 9 and a NOR circuit 10 are required, and six elements must be added in terms of the number of transistors, resulting in a problem that the circuit becomes large.

The present invention was made to solve these problems, and aims to provide a multiplexer that has priority and can be realized with a small number of transistors.

[Means for solving problems]

A multiplexer according to the present invention includes a first metal oxide film field effect transistor whose first electrode is connected to a first signal line, whose gate terminal is connected to a first control line, and whose drains are coupled to each other, Their gate terminals are both the first
a complementary conductive metal oxide field effect transistor with one source connected to a second control line and the other source connected to a power supply or ground; a second metal oxide field effect transistor connected to the drain terminal of the conductive metal oxide field effect transistor, the first electrode of which is connected to the second signal line; The second electrode of the metal oxide field effect transistor and the second electrode of the second metal oxide field effect transistor are outputs.

[Effect]

In this invention, the gate of the first metal oxide field effect transistor is controlled by the first control line, the gate of the first metal oxide field effect transistor is off, and the second control line is in a predetermined state. When the metal oxide field effect transistor is at a high level, the level on the second control line is sent to the gate terminal of the second metal oxide field effect transistor to control the gate.

〔Example〕

FIG. 1 is a diagram showing the configuration of an embodiment of the multiplexer of the present invention. In this figure, the same reference numerals as in FIG. 2 indicate the same parts, and reference numeral 7 denotes P to which the second control line 2 is connected to the source and the first control line 1 is connected to the gate terminal.
The MO3FET 8 is an NMO3FET whose drain is connected to the drain of the PMO5FET 7, whose source is grounded, and whose gate terminal is connected to the first control line 1, and these form a pair of complementary conductivity.

Next, the operation will be explained.

When the first control line 1 and the second control line 2 are at logic "L'", the first NMOSFET 5 and the second NMOSFET 6 are both turned off, and the first signal line 3 and the second signal line 4 are turned off. Neither logic state is selected.

When the first control line 1 is at logic “H”, the first NMOSF
ET5 is turned on and the logic state of the first signal line 3 is selected. However, at this time, PMO3FET7 is off and NM
Since the OSFET 8 is on and transmits the logic "L" to the gate terminal of the second NMOSFET 6, the second NMOSFET 6 is turned off regardless of the state of the second control line 2.
The logic state of the second signal line 4 is not selected.

However, when the first control line 1 is at logic "L" and the second control line 2 is at logic 14H", the first NM03FET
5 is off, but PMO3FET7 is on, NMOS
The FET 8 is off, and the second NMOSFET 6 is turned on to transmit the logic "HII" on the second control line 2 to the gate terminal of the second NMOSFET 6, so that only the logic state of the second signal line 4 is selected.

That is, by controlling the levels of the first control line 1 and the second control line 2, one of the first signal line 3 and the second signal line 4 can be arbitrarily selected.

〔Effect of the invention〕

As described above, the present invention includes a first metal oxide film field effect transistor whose first electrode is connected to a first signal line, whose gate terminal is connected to a first control line, and whose drain is connected to each other. , complementary conductive metal oxide films whose gate terminals are both connected to the first control line, a second control line is connected to one source, and a power supply or ground is connected to the other source. a field effect transistor and a second metal oxide field having its gate terminal connected to the drain terminal of a complementary conducting metal oxide field effect transistor and its first electrode connected to a second signal line; The second electrode of the first metal oxide field effect transistor and the second electrode of the second metal oxide field effect transistor are used as outputs. This has the effect of configuring a multiplexer.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an embodiment of the multiplexer of the present invention, and FIG. 2 is a diagram showing the configuration of a conventional multiplexer. In the figure, 1 is the first control line, 2 is the second control line, 3
is the first signal line, 4 is the second signal line, and 5 is the first NMO
SFET, 6 is the second NMOS FET, 7th PMO
5 is an FET, 8 is an NMOSFET, and 11 is an output of a multiplexer. Note that the same reference numerals in each figure indicate the same or identical parts.

Claims (1)

[Claims] a first metal oxide film field effect transistor having a first electrode connected to a first signal line and a gate terminal connected to a first control line; a complementary conductive metal oxide field effect transistor connected to a first control line, having one source connected to a second control line and the other source connected to a power supply or ground; and a gate terminal thereof; a second metal oxide field effect transistor connected to the drain terminal of the complementary conductive metal oxide field effect transistor and having a first electrode connected to a second signal line; A multiplexer characterized in that a second electrode of the first metal oxide field effect transistor and a second electrode of the second metal oxide field effect transistor are outputs.