JPS6318719A - Input buffer circuit - Google Patents

Input buffer circuit

Info

Publication number
JPS6318719A
JPS6318719A JP16321386A JP16321386A JPS6318719A JP S6318719 A JPS6318719 A JP S6318719A JP 16321386 A JP16321386 A JP 16321386A JP 16321386 A JP16321386 A JP 16321386A JP S6318719 A JPS6318719 A JP S6318719A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
channel mos
level
setting
tr
input buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16321386A
Inventor
Sumio Shiotani
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0021Modifications of threshold
    • H03K19/0027Modifications of threshold in field effect transistor circuits
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • H03K19/0185Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018585Coupling arrangements; Interface arrangements using field effect transistors only programmable

Abstract

PURPOSE:To change an input threshold level by connecting one conduction type transistor (TR) of a CMOS inverter in parallel and controlling one of TRs in conductive/nonconductive from an external terminal. CONSTITUTION:In setting a control terminal 2 to a low level, an N-channel MOS TR 8 is always nonconductive and the input buffer uses a P-channel MOS TR 5 and an N-channel MOS TR 7 to constitute the CMOS inverter. In setting the control terminal 2 at a high level, the N-channel MOS TR 8 is always conductive, and the input buffer circuit constitutes the inverter by the P-channel MOS TR 5 and MOS TRs 6, 7, 8. Thus, in setting the control terminal 2 being an external terminal to a low level, the input threshold voltage is brought into a CMOS level and in setting the terminal to a high level, the threshold voltage is brought into a TTL level.
JP16321386A 1986-07-10 1986-07-10 Input buffer circuit Pending JPS6318719A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16321386A JPS6318719A (en) 1986-07-10 1986-07-10 Input buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16321386A JPS6318719A (en) 1986-07-10 1986-07-10 Input buffer circuit

Publications (1)

Publication Number Publication Date
JPS6318719A true true JPS6318719A (en) 1988-01-26

Family

ID=15769448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16321386A Pending JPS6318719A (en) 1986-07-10 1986-07-10 Input buffer circuit

Country Status (1)

Country Link
JP (1) JPS6318719A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0405833A2 (en) * 1989-06-30 1991-01-02 AT&T Corp. Programmable logic level input buffer
EP0575124A2 (en) * 1992-06-15 1993-12-22 Fujitsu Limited Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0405833A2 (en) * 1989-06-30 1991-01-02 AT&T Corp. Programmable logic level input buffer
JPH0338873A (en) * 1989-06-30 1991-02-19 American Teleph & Telegr Co <Att> Integrated circuit
EP0405833A3 (en) * 1989-06-30 1991-11-06 American Telephone And Telegraph Company Programmable logic level input buffer
US6720804B2 (en) 1992-05-15 2004-04-13 Fujitsu Limited Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
EP0575124A3 (en) * 1992-06-15 1996-07-24 Fujitsu Ltd Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
US5557221A (en) * 1992-06-15 1996-09-17 Fujitsu Limited Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
US6034555A (en) * 1992-06-15 2000-03-07 Fujitsu Limited Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
US6492846B1 (en) 1992-06-15 2002-12-10 Fujitsu Limited Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
US6707325B2 (en) 1992-06-15 2004-03-16 Fujitsu Limited Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
EP0575124A2 (en) * 1992-06-15 1993-12-22 Fujitsu Limited Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
US6737893B2 (en) 1992-06-15 2004-05-18 Fujitsu Limited Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
US6744300B2 (en) 1992-06-15 2004-06-01 Fujitsu Limited Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation

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