JPH02123821A - Semiconductor circuit - Google Patents

Abstract

PURPOSE:To obtain a high resistance output by isolating P, N-channel transistors(TRs) electrically and interrupting the P, N-channel TRs with a pullup and pull-down TRs connected to each gate line. CONSTITUTION:With a low level voltage given to a gate line (a) and a high level voltage given to a gate line (b) respectively, a P-channel TR 6a and an N-channel TR 6b being components of a transmission gate 6 are both turned off, a voltage Ve on a gate line (e) is at a high level or in the floating state depending on the input voltage Vc. On the other hand, a voltage Vf on a gate line (f) is at a low level or in the floating. Since the P-channel TR 7 for pullup is turned on in this state, the gate line (e) goes to a high level independently of the input voltage Vc. Similarly, since a down N-channel TR 8 is turned on, the gate line (f) is at a low level conversely. Thus, a high resistance output is obtained from the output terminal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention mainly relates to CMO5 (complemental
y MetalOxide Se+5iconduct
or) It relates to a semiconductor circuit used as an inverter or the like.

[Conventional technology]

Figure 2 is a conventional low through current CMOS inverter circuit diagram, in which 11 is a P-channel transistor;
Reference numeral 2 indicates an N-channel transistor, 13 indicates a P-channel transistor, and 14 indicates an N-channel transistor.

The drains D of the P-channel transistor 11 and the N-channel transistor 12 are connected to each other, and the output terminal g
The source S of the P-channel transistor 11 is connected to the power supply, and the source S of the P-channel transistor 11 is connected to the power supply.
A CMOS inverter output circuit 10 is constructed with the source S of the CMOS inverter output circuit 10 set at a ground potential.

The gate line e of the P-channel transistor 11 and the gate line f of the N-channel transistor 12 are connected to each other via a diffused resistor 15, and the drain D1 of the P-channel transistor 13 is connected to the drain D of the N-channel transistor 14. ing. The source S of the P-channel transistor 13 is connected to the power supply, and the source S of the P-channel transistor 13 is connected to the power supply.
The source S of the channel transistor 14 is set to the ground potential, and the gate of the P channel transistor 13 and the gate of the N channel transistor 14 are connected to the input terminal C, respectively.

Such a CMOS inverter circuit operates as shown in FIG. 3 in the process of changing the input potential vc to the input terminal C from an initial high level state to a low level state. FIG. 3 shows time on the horizontal axis and potential on the vertical axis.

Now, when the input potential v6 to the input terminal C becomes lower than the threshold potential PCbVTM of the P-channel transistor 13, the P-channel transistor 13. Both N-channel transistors 14 are turned on, and the potential v0 of the gate line e rises to a high level, but the potential vf of the gate line f is such that the resistance value of the diffused resistor 15
．． Since it is sufficiently larger than the on-resistance of No. 14, it remains at a low level due to the voltage drop.

When the input potential V, is lower than the threshold voltage N ck V of the N-channel transistor 14, the P-channel transistor 13 is turned on, the N-channel transistor 14 is turned off, and the resistance value of the N-channel transistor 14 is Since it is sufficiently larger than the diffused resistor 15, the potential vt of the gate line f rises to a high level.

On the other hand, when the input potential 6 at the input terminal C is changed from a low level to a high level, the change occurs as shown by the broken line based on the same principle.

Therefore, during the rising and falling processes of the input potential V, the potentials V,, V, change as described above, so both transistors 11 and 12 of the CMOS inverter circuit are not turned on at the same time, and a through current flows. do not have.

[Problem to be solved by the invention]

By the way, such conventional CMOS with reduced through current
In inverter circuits, there is a problem in that it is difficult to make the CMOS inverter output high in resistance.

The present invention has been made in view of the above circumstances, and its object is to provide a semiconductor circuit that has a low through current and can provide a high resistance output.

[Means to solve the problem]

In the semiconductor circuit according to the present invention, a P-channel transistor for pull-up is connected to the gate line of the P-channel transistor in a CMOS inverter circuit, an N-channel transistor for pull-down is connected to the gate line of the N-channel transistor, and both gates of the P-channel transistor are connected to the gate line of the P-channel transistor. A cutoff function element is interposed between the lines, and a switching signal is input to the pull-up P-channel transistor, pull-down N-channel transistor, and cutoff function element to turn one of them on and the other off.

[Effect]

In the present invention, this electrically separates the P-channel transistor and N-channel transistor in the previous stage of the CMOS inverter output circuit, and also connects the P-channel transistor and N-channel transistor of the CMOS inverter output circuit to their respective gate lines. It is cut off by the pull-up and pull-down transistors.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS A case in which the present invention is configured as a tri-state inverter circuit will be specifically described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a semiconductor circuit according to the present invention (hereinafter referred to as the circuit of the present invention), in which l is a P-channel transistor, 2 is an N-channel transistor, 3 is a P-channel transistor, 4 is an N-channel transistor, 5 indicates the diffusion resistance.

P-channel transistor 1 and N-channel transistor 2
and the drains D are connected to each other and to the output terminal g.

The source S of the P-channel transistor 1 is connected to the power supply, and the source of the N-channel transistor 2 is connected to the ground potential.

The gate line e connected to the gate of the P-channel transistor l is connected to the drain D of the P-channel transistor 7 for pull-up, and the gate line r connected to the gate of the N-channel transistor 2 is connected to the drain D for pull-down. Drain D of N-channel transistor 7
are connected, and both gate lines e and f are interposed with a diffusion resistor 5 and a CMO3) transmission gate 6 connected in series, and each gate line e and f is connected to P
It is connected to each drain D of channel transistor 3 and N-channel transistor 4.

That is, P channel transistor 1 is connected to P channel transistor 3 . The output of P-channel transistor 7 for pull-up is input, and N-channel transistor 2 is connected to N-channel transistor 4. The output of the pull-down N-channel transistor 8 is used as an input.

Each source S of the P-channel transistor 3.7 is connected to the power supply, and each source S of the N-channel transistor 4.8 is connected to ground potential, and further connected to the P-channel transistor 3.7. N
The gates of the channel transistors 4 are connected to the input terminal C in a mutually connected state.

CMO5) The transmission gate 6 is constructed by connecting the sources and drains of a P-channel transistor 6a and an N-channel transistor 6b to each other, and the gate of the P-channel transistor 6a is connected to the gate of a pull-down N-channel transistor 8 by a line a. Further, the gate of the N-channel transistor 6b is connected to the gate of the P-channel transistor 7 for pull-up by a line b, and signals having opposite phases to each other are inputted to the lines a and b. .

Therefore, in such a circuit of the present invention, the gate line a
For example, when a high-level voltage is applied to gate line b and a low-level voltage is applied to gate line b, both the pull-up P-channel transistor 7 and the pull-down N-channel transistor 8 are turned off, and the P-channel transistor constituting the transmission gate 6 is turned off. Both SN channel transistors 6a and 6b are turned on and operate in the same manner as the conventional low penetration inverter circuit shown in FIG.

Conversely, when a low level voltage is applied to the gate line a and a high level voltage is applied to the gate line b, both the P channel transistor 6a and the SN channel transistor 6b constituting the transmission gate 6 are turned off, and the voltage on the gate line e V is at a high level or in a floating state depending on the value of the input voltage v6. On the other hand, the voltage (2) on the gate line f is at a low level or in a floating state.

In this state, the pull-up P-channel transistor 7 is in the on state, so the gate line e is at the input voltage ■. It will be at a high level regardless of the value of.

Similarly, since the pull-down N-channel transistor 8 is also in the on state, the gate line f becomes low level.

Therefore, both P-channel transistor 1 and N-channel transistor 2 are turned off, and a high resistance output is obtained from the output terminal.

In the above-mentioned embodiment, the transmission gate 6 has been described as having a configuration in which the P-channel transistor 5a and the N-channel transistor 6b are combined, but the structure is not limited to this, and a switching element or the like may be used. Any material may be used as long as it functions as a functional element. Moreover, when such an element is provided with a resistor, the diffused resistor 5 may be omitted.

〔Effect of the invention〕

As described above, the circuit of the present invention has a low through-current,
Moreover, it has the excellent effect of providing a high resistance output.

[Brief explanation of drawings]

FIG. 1 is an output circuit diagram of a tri-state inverter to which the present invention is applied, FIG. 2 is a conventional inverter circuit diagram, and FIG. 3 is an operation explanatory diagram. l...P channel transistor 2...N channel transistor 3...P channel transistor 4...
・N-channel transistor 5...diffusion resistor 6...
Blocking function element 7... P-channel transistor for pull-up 8... N-channel transistor for pull-down Note that in the drawings, the same reference numerals indicate the same or equivalent parts. Agent Masu Oiwa Diagram Funeral Diagram Electrogram Procedure Amendment (Voluntary) July 4, 1st Year

Claims (1)

[Claims] 1. In a CMOS inverter circuit, a P-channel transistor for pull-up is connected to the gate line of the P-channel transistor, and an N-channel transistor for pull-down is connected to the gate line of the N-channel transistor, and a blocking function element is installed between these two gate lines. A semiconductor characterized in that a switching signal is input to the pull-up P-channel transistor, the pull-down N-channel transistor, and the cutoff function element to turn one of them on and the other one to turn off. circuit.