JPH02123821A - Semiconductor circuit - Google Patents

Semiconductor circuit

Info

Publication number
JPH02123821A
JPH02123821A JP63277972A JP27797288A JPH02123821A JP H02123821 A JPH02123821 A JP H02123821A JP 63277972 A JP63277972 A JP 63277972A JP 27797288 A JP27797288 A JP 27797288A JP H02123821 A JPH02123821 A JP H02123821A
Authority
JP
Japan
Prior art keywords
gate line
channel
voltage
turned
trs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63277972A
Other languages
Japanese (ja)
Inventor
Koichi Kawauchi
Akio Kiji
Seiichiro Asari
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP63277972A priority Critical patent/JPH02123821A/en
Publication of JPH02123821A publication Critical patent/JPH02123821A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain a high resistance output by isolating P, N-channel transistors(TRs) electrically and interrupting the P, N-channel TRs with a pullup and pull-down TRs connected to each gate line.
CONSTITUTION: With a low level voltage given to a gate line (a) and a high level voltage given to a gate line (b) respectively, a P-channel TR 6a and an N-channel TR 6b being components of a transmission gate 6 are both turned off, a voltage Ve on a gate line (e) is at a high level or in the floating state depending on the input voltage Vc. On the other hand, a voltage Vf on a gate line (f) is at a low level or in the floating. Since the P-channel TR 7 for pullup is turned on in this state, the gate line (e) goes to a high level independently of the input voltage Vc. Similarly, since a down N-channel TR 8 is turned on, the gate line (f) is at a low level conversely. Thus, a high resistance output is obtained from the output terminal.
COPYRIGHT: (C)1990,JPO&Japio
JP63277972A 1988-11-01 1988-11-01 Semiconductor circuit Pending JPH02123821A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63277972A JPH02123821A (en) 1988-11-01 1988-11-01 Semiconductor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63277972A JPH02123821A (en) 1988-11-01 1988-11-01 Semiconductor circuit

Publications (1)

Publication Number Publication Date
JPH02123821A true JPH02123821A (en) 1990-05-11

Family

ID=17590835

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63277972A Pending JPH02123821A (en) 1988-11-01 1988-11-01 Semiconductor circuit

Country Status (1)

Country Link
JP (1) JPH02123821A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6121619A (en) * 1984-06-25 1986-01-30 Fujitsu Ltd Complementary tri-state mis gate circuit
JPS6360625A (en) * 1986-08-29 1988-03-16 Mitsubishi Electric Corp Complementary 3-state mos integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6121619A (en) * 1984-06-25 1986-01-30 Fujitsu Ltd Complementary tri-state mis gate circuit
JPS6360625A (en) * 1986-08-29 1988-03-16 Mitsubishi Electric Corp Complementary 3-state mos integrated circuit

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