JPS58120321A - Input circuit - Google Patents

Abstract

PURPOSE:To ensure a stable operation of an input circuit as a pull-up resistance, by connecting the drain of a p type MOS transistor having its source and gate connected to the gate and the output terminal of a CMOS type inverter respectively to a power supply. CONSTITUTION:An input terminal IN is connected to the gate of an input MOS inverter IV consisting of a p type MOS transistor TR3 and an n type MOSTR4 via a protecting resistance 1 as well as to the source of a p type MOSTR2. The gate and the drain of the TR2 are connected to an output terminal O of the IV and a power supply VDD, respectively. When the terminal IN is opened, the potential is unsteady at a gate node 5 of the IV. However, the potential is gradually charged by the leakage current of the TR2. When this potential exceeds the threshold voltage of the IV, an output O is set at an L level. Then the TR2 is turned on to complete the pull-up function of the terminal IN. When the terminal IN is fixed at a low level, the potential of the node 5 is lowered to less than the threshold voltage of the IV. Thus the terminal O is set at an H level, and the TR2 is turned off respectively. Then only the leakage current of the TR2 flows to the terminal IN from the power supply. As a result, the power consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Inventive insulated gate field effect transistor (hereinafter M08
The present invention relates to an input circuit consisting of a transistor (i), and particularly to an input circuit having a so-called pull-up paternal pull-down function that can fix the voltage level at a high or low level when an input terminal is opened.

Traditionally, pull-up or pull-down resistors in MO8 integrated circuits are constructed from MO8 resistors. The pull-up or pull-down resistor is used to increase the level of human effort required when the input terminal is opened, but it may also be possible to identify the input terminal to a potential opposite to the potential determined when the input terminal is opened. Such a case occurs when the function of the integrated circuit is provided with parity by leaving the cough input terminal open or connecting it to a fixed potential.

In this way, when the input terminal is fixed at a potential opposite to the potential determined when it is open, the pull-up or If-1-jk
The problem is an increase in current consumption due to the current flowing through the down resistor.

For example, when an input terminal with a pull-up resistor is connected to a ground potential (hereinafter referred to as GNI), a current flows from the power source to GND through the pull-up resistor. The input level of the input gate is determined by the division ratio between the pull-up resistor and the input protection resistor.

Therefore, the larger the resistor is, the more the current consumption decreases and the input power level becomes more stable. On the other hand, if the input terminal is opened and the pull-up resistor is too large,
The effect as a pull-up becomes weaker and it becomes weaker against foreign noise. Therefore, the pull-up resistor cannot be increased arbitrarily.

In the present invention, when an input terminal with a pull-up (or pull-down) is fixed to the GND (or power supply) level, the MOS transistor for the pull-up (or pull-down) resistor is cut off (hereinafter referred to as OFI?). An input circuit with a sufficiently low current consumption and a sufficiently low pull-up (or pull-down) resistance can be created by making the pull-up (or pull-down) resistor MO8 transistor conductive (hereinafter referred to as ON) when the input terminal is opened. It is about providing.

The present invention provides a pair of N-channel and P-channel MO8)
A complementary MO8 inverter consisting of two transistors and a P-channel (or N-channel) MOS transistor whose drain and source electrodes are connected to the gate electrode of the inverter and the power supply (or GND), respectively, have their gate electrodes connected to the complementary MO& This is an input circuit characterized by being connected to the output of an inverter.

Next, the present invention will be explained in detail according to embodiments using the drawings.

FIG. 1 (al is a circuit connection diagram showing one embodiment of the present invention,
1 is input image 1i & anti, 2 is P channel M for pull-up
OS transistors 3 and 4 respectively narrow the P-channel and N-channel transistors forming the input inverter. Now, when the input terminal IN is opened and the time of death is considered, the potential of the gate electrode (node 5) of the input inverter is initially unstable, but it is gradually charged to a high level by the leakage current of the P-channel transistor 2. Once this level exceeds the single value voltage of the input inverter, the output O of the inverter is inverted to a low level, and the P-channel transistor 2 whose gate electrode is connected to the output O is turned on.
state. The series of operations described above completes the pull-up function of the input terminal. Next, consider the case where the input terminal IN is fixed at a low level. In this case, the potential of node 5 is determined by the division ratio of the pull-up resistor and the input protection resistor, but since the value of the input protection resistor is usually 1 to several Ω, the ON resistance of P-channel transistor 2 is set to 10 Ω. If set to , the potential of node 5 will be below the threshold voltage of the input inverter. By doing this, the output O of the input inverter is inverted to high level, and the pull-up P-channel transistor 2 is turned off.
F. As mentioned above, when the input terminal IN is fixed at a low level, the pull-up P-channel transistor 2 is turned off, and the current a flowing from the power supply to the input terminal IN is only the leakage current of the P-channel transistor 2. , compared to the conventional manually operated path with pull-up, the extinguishing current can be significantly improved.

FIG. 2(a) is a circuit connection diagram showing another embodiment of the present invention, in which a resistor 7 is connected in parallel to the P-channel transistor 2 for pull-up. It goes without saying that this resistance can be realized using polycrystalline silicon, a diffusion layer, a P-well, etc. FIG. 3(a) is a circuit connection diagram showing another embodiment of the present invention. , P-channel MO8 with gate connected to GND)
6 is an example in which the transistor 9 realizes the high resistance in the other embodiments. In the examples shown in Figures 2(a) and 3(1), if the input terminals are left open, this high resistance causes the inverter to quickly invert to a low level, increasing the speed of the pull-up operation. I can do it.

The above explanation has mainly been about pull-ups, but the same idea can be applied to pull-downs as well.

Figure 1(b) shows the case of a pull-down resistor, and Figure 2(b) shows the case of a pull-down resistor.
and FIG. 3(b) respectively show the case where a high resistance for speeding up and an N-channel MO8 transistor for speeding up are connected in parallel to the N-channel MO8 transistor for pull-down resistor. Although a detailed explanation will be omitted, it is clear that the same applies to the case of the pull-up resistor as described above.As explained above, the present invention works as a stable pull-up (or pull-down) resistor when the input is open, and pulls the input terminal to a high or low level. When fixed at a low level, it has the effect of significantly reducing current consumption compared to conventional human-powered circuits with pull-ups (or pull-downs).

[Brief explanation of drawings]

Fig. 1(a), Fig. 2(a) and Fig. 3(a) are circuit connection diagrams showing an embodiment of the present invention regarding a human power circuit with pull-up, Fig. 1(b), FIG. 2(b) and FIG. 3(b) are circuit connection diagrams each showing an embodiment in the case of an input circuit with pull-down. 1... Input holding resistor, 2... P-channel MO8) transistor for pull-up, 3, 4...
...P-channel and N-channel MO8) transistors constituting a complementary MO8 inverter, 5...Inno<=ri gate, 6...N-channel MO8 for pull-down? / register, 7, 8...Resistance for speed-up, 9...P for speed-up
Channel MO8) Uy resistor, 10...N channel MO8) Ranister for speed up. ((1) Part (al) (a) (b) 1 Figure 2 Figure (b) 3 Figure

Claims (2)

[Claims] (1) A complementary MO8 human-powered inverter consisting of a pair of N-channel and P-channel MO8 transistors, and a P (or N
) An input circuit characterized in that a channel MO8 transistor is inserted, the gate electrode of the P (or N) channel MO8 transistor being connected to the output of the complementary ff1 MO8 inverter. (2) P (or N
) Channel MO8) transistor is inserted, the drain and source of the P (or N) channel MO8) transistor are connected with a high resistance, and its gate electrode is connected to the complementary! MO8
An input circuit characterized in that it is connected to the output of an inverter.