JPS6041325A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent an abnormal current from being flowed to a bus line to stabilize the operation by setting always the bus line, to which outputs of plural tri-state buffers and input terminals of one or more gate circuits are connected, to a determined potential. CONSTITUTION:Outputs of plural tri-state buffers 21 and 22 and input terminals of one or more gate circuits 31 are connected to a bus line 11 to constitute an MOSLSI. These buffers 21 and 22 consist of P type transistors TRs 41 and 42 and N type TRs 51-53 and 54-56, and a tri-state buffer input terminal 61 is connected to respective gates of TRs 41, 53, 42, and 56, and a tri-state buffer breaking signal terminal 72 is connected to respective gates of TRs 51, 52, 54, and 55. Or of the signal of the terminal 72 is operated in a two-input OR circuit 81, and the output is applied to the gate of a P type TR44. Thus, the line 11 is always set to a determined potential to prevent an abnormal current from being flowed to the line 11, thus stabilizing the operation of the MOSLSI.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a 0VIO8LSI with
This invention relates to a semiconductor integrated circuit that keeps the level IX stable at all times and prevents circuit latch-up and abnormal current generation.

In the CMO8LSI shown in Figure 1, multiple tri-state buffers that can block signals and set the output to high impedance and pass lines connected to the input terminals of one or more gate circuits are often used. Ru. In FIG. 1, 11 is a pass line, 21.22 is a tri-state buffer, 31 is a gate circuit, 41 to 43
are P-channel transistors, 51-57 are N-channel transistors, 61.62 is a tri-state buffer input signal, and 71.72 is a tri-state buffer cutoff signal.

However, when the tristate buffers 21 and 22 connected to the pass line 11 are all cut off, the pass line 11 becomes high impedance, and the potential of the pass line 11 is not determined. Therefore, the pass line 11 may have various potentials due to thermal excitation or the like. If the power supply voltage range is exceeded, latch-up may occur.

Also, when the potential exceeds the threshold voltage of both P-channel and N-channel transistors, the large sword circuit (first
In the figure, at 31), both the P-channel and N-channel transistors 43 and 57ρ become conductive, and an abnormal current flows. The CMO8LSI, which uses a pass line to which a plurality of tri-state buffers 21 and 22 and the input terminal of the gate circuit 31 are connected, has the above-mentioned drawbacks.

The present invention eliminates such drawbacks and provides a circuit that obtains stable operation when a pass line connected to an input terminal of a gate circuit and an output of a tristate buffer is applied to a CMOS LSI.

That is, the semiconductor integrated circuit according to the present invention includes a CMOS L having a pass line to which the outputs of a plurality of tri-state buffers and the input terminals of one or more gate circuits are connected.
The SI is characterized in that it includes a circuit that fixes the potential of a pass line to a power supply or ground potential when all outputs of tristate buffers for the pass line are at high impedance.

Next, one embodiment of the present invention will be described with reference to FIG.

Hereinafter, the same components as those in FIG. 1 will be described using the same numbers. Furthermore, numeral 44 is a P-channel transistor, and numeral 81 is a two-way OR circuit.

In the circuit shown in Figure 2, both cutoff signals 71 and 72 are 0.
”, the tristate buffers 21 and 22 are both cut off. At this time, the output of the OR circuit 81 is
Then, the P-channel transistor 44 becomes conductive, and the potential of the pass line becomes the power supply voltage.

This circuit makes the potential of the pass line logically stable, and even when the tri-state buffer is cut off, it is possible to prevent latch-up from occurring and abnormal current from flowing into the inverter 3'.

FIG. 3 shows another embodiment of the invention.

The symbols are the same as in Figure 2. In this case, the P-channel transistor 44 is always in a conductive state. However, this requires N-channel transistors 52, 53, 55, 56 in tri-state buffers 21, 22.
The tri-state buffer drives the pass line 11 by using a transistor with a conduction resistance larger than
“It can be done.

Furthermore, when either tri-state buffer 21 or 22 is in the cut-off state, the P-channel transistor 44 is conductive, thereby maintaining the pass line 11 at the power supply voltage.

Figure 4 shows the P-channel transistor 4 in Figure 3.
This is an example in which an N-channel transistor 58 is used instead of the transistor 4. The pass line 11 is kept at ground potential when all tristate buffers 21 and 22 are in the cutoff state.

As described above, according to the present invention, in a CMOS LSI, the path line to which the outputs of a plurality of tristate buffers and the input terminals of one or more gate circuits are connected is always set at a predetermined potential. This has the effect of preventing launch-up and the generation of abnormal current.

[Brief explanation of drawings]

FIG. 1 is a diagram of a pass line in a conventional CMOS LSI and the tri-state buffer and gate circuit connected thereto, and FIGS.
1 is a diagram illustrating an embodiment of a circuit that fixes a pass line in a MOS LSI, a tristate buffer connected to the pass line, a gate circuit, and a pass line to a power supply or ground potential; FIG. 11... Pass line, 21.22... Tri-state buffer, 31... Gate circuit, 41-44...
P channel transistor, 51-58...N channel transistor, 61.62 ・Tri-stay!・Pan input signal terminal, 71.72 ・Tri-state buffer cutoff signal terminal, 81... 2-person OR circuit Patent applicant NEC Corporation Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] (1) In a CMO8LSI that has a pass line to which the outputs of a plurality of tri-state buffers and the input terminal of one or more gate circuits are connected, when the outputs of the tri-state buffers to the pass line are all at high impedance, 1. A semiconductor integrated circuit comprising a circuit for fixing the potential of a lotus line to a power supply or ground potential.