JP2739785B2 - Test signal input circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test input circuit for an analog / digital hybrid integrated circuit.

[0002]

2. Description of the Related Art Conventionally, a digital integrated circuit often employs a test mode in order to perform a test efficiently. This application describes a case where the present invention is applied to an analog / digital mixed integrated circuit.

FIG. 4 shows an example of a conventional analog / digital hybrid integrated circuit. An analog circuit 10 having an analog terminal P1, a digital circuit 20, an input terminal P2 for switching it to a test mode, and a test circuit an input terminal P3 of the mode signal required when, consist Q _13, Q ₁₄ constituting the inverter as the interface unit. Although a similar interface circuit is provided for the terminal P2, it is assumed that the terminal P2 is included in the digital circuit, and the description is omitted.

[0004]

Although the terminal P2 is used only for testing a digital circuit, it must be provided as an external terminal of the integrated circuit, and the terminal cannot be used effectively. Was.

[0005]

According to the present invention, an analog / digital hybrid integrated circuit usually has a step of testing the analog section and the digital section separately (although a comprehensive test may be performed thereafter). One of the terminals of the analog section which is not used in the test of the digital section is shared with the input terminal required in the test.

That is, the test signal input circuit of the present invention
Receives the signal from the analog terminal and outputs the signal.
A first inverter circuit to be supplied to the digital circuit section;
Power supply line and first inverter with a power mode signal as input
And a second inverter circuit connected between the
The second inverter when the strike mode signal is at the first level
The circuit connects the power supply line to the first inverter circuit and
A second inverter when the strike mode signal is at a second level
The circuit interrupts the connection between the power supply line and the first inverter circuit.
Refused.

[0007]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

FIG. 1 shows a first embodiment of the present invention, and FIG.
The same components as those described above are denoted by the same reference numerals and description thereof is omitted.

The analog terminal P1 is connected to the gates of the transistors Q ₁ and Q _{4 in} addition to the original analog circuit 10, but since the gates have high impedance,
It has no effect on the original analog operation. The input signal P2 for setting the digital test mode is applied to the digital circuit 20 as in FIG. 4 and also applied to the gates of the transistors Q ₂ and Q ₃ . The transistors Q _{1 to} Q ₄ constitute a NAND circuit.

[0010] If a signal indicating the test mode is applied with the polarity of the high to the test mode terminal P2, the transistor Q ₂ is turned off and the transistor Q ₃ is turned on. At this time, a signal required for a digital test is externally applied to the analog terminal P1 irrespective of the original analog signal. In this case, the if test signal if high Q ₄ are turned on internal terminal I _T goes low, the Q ₁ is turned on if the test signal is low I _T becomes high. That is, the analog terminal P1 can serve as the input terminal P3 necessary for the test of FIG.

However, if only this is the case, it is possible to simply connect the terminals P1 and P3 internally in FIG. 4 and omit the P3 terminal. However, in this case, the original analog voltage developed terminal P1 to the non-test mode is also applied to the transistor Q _13, Q _14, this is the case of the intermediate potential, it will be turned on Q _13, Q ₁₄ both There is a drawback that a so-called through current occurs and power consumption increases.

In FIG. 1, in the non-test mode, that is, when the terminal P2 is low, even if the transistors Q ₁ ,
Even both turned on intermediate potential is applied to the gate of Q _4, Q ₃ because the gate is low the transistor Q ₃ are turned off, passage through current is cut off, no current flows. Further and transistor Q ₂ is turned on, regardless of the transistors Q _1, Q _4, the output I _T is (not indeterminate) has become high.

FIG. 2 shows a second embodiment of the present invention.
The difference from FIG. 1 lies in that the transistors Q _{5 to} Q ₈ constituting the R circuit are used and that the signal MODE indicating the test mode is obtained from the digital circuit side. There are various methods for creating a test mode, such as a test mode with a special combination of digital terminals and a test mode by setting a test flag (flip-flop) in a digital circuit. The MODE signal corresponds to such a case. In FIG. 2, when the MODE signal is low, it is a test mode, and when it is high, it is a non-test mode.

In this case, in the test mode, the transistor Q
₆ is turned on, the transistor Q ₅ since Q ₈ is turned off, Q
₇ operates as an inverter, a digital signal needed when digital test applied from the outside to the analog terminal P1 it is, appears to internal terminals I _T inverted. On the other hand, the non-test mode transistor Q ₆ is turned off, because the Q ₈ is turned on, I _T is always at a low (not indefinite). The original voltage (as a tentatively intermediate potential) to the analog terminal is the transistor Q ₆ through current for off does not flow even occur.

FIG. 3 shows a third embodiment of the present invention.
A transistor Q ₉ to Q ₁₂ and the inverter G ₁ constituting the clocked inverter, instead of the NOR circuit. In this circuit, the MODE signal becomes low in the test mode, the transistors Q ₉ and Q ₁₂ are turned on, and the transistors Q ₁₀ and Q ₁₁ operate as inverters. On the other hand, at the time of the non-test, since the transistors Q ₉ and Q ₁₂ are both turned off, no through current flows. Note that since the internal terminal _IT is a high inverter (undefined), this is most suitable when another signal is connected via a bus or the like.

[0016] Note also omitted one of the transistors Q ₉ or Q ₁₂ (drain-to-source short) having an application effect since the through current does not flow.

[0017]

According to the present invention, not only is it unnecessary to provide an input terminal required for testing a digital section in an analog / digital mixed integrated circuit, but also
The added circuit has a feature that it can function without malfunction (through current or the like) at the original analog terminal voltage.

The effect is further enhanced if there are a plurality of such terminals.

[Brief description of the drawings]

FIG. 1 is a diagram of a first embodiment of the present invention.

FIG. 2 is a diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram of a third embodiment of the present invention.

FIG. 4 is a diagram of a conventional example.

Claims (4)

(57) [Claims] An analog terminal and the analog terminal
And an analog circuit connected to the
Use in an integrated circuit device of the analog-digital mixed to
Test signal input circuit for the analog
A signal from a terminal and an output
A first inverter circuit to be supplied to the
Between the power supply line and the first inverter
A second inverter circuit connected to the
When the second mode signal is at the first level,
The power supply line to the first inverter circuit.
Connected when the test mode signal is at the second level
The second inverter circuit is connected to the power supply line and the first power supply line.
A test signal input circuit for disconnecting a connection with an inverter circuit . 2. An analog terminal and the analog terminal
And an analog circuit connected to the
Analog and digital integrated circuit devices
Test signal input circuit for the analog
The signal from the terminal is used as the gate input and the source and drain are
A first conductive line connected between the first power line and the output node
Gate of the first transistor of the type and the test mode signal
The source and drain are connected to the first power supply line as input.
And a second transistor of the first conductivity type connected between the second output node and the output node.
Transistor and gate signal from the analog terminal
One of the source and drain is connected to the second power supply line
A third transistor of a second conductivity type, and the test
The mode signal is used as the gate input and the source and drain are
The other of the source and the drain of the transistor 3 and the output
A fourth transistor of the second conductivity type connected between the node and the node
And the output node is connected to the digital circuit unit.
And a test signal input circuit. 3. An analog terminal and the analog terminal.
And an analog circuit connected to the
Analog and digital integrated circuit devices
Test signal input circuit for the analog
The signal from the terminal is used as the gate input and
Is connected to the first power supply line .
Transistor and test mode signal
Source and drain are the source and drain of the first transistor.
First conductivity type connected between the other end of the rain and the output node
And a signal from the analog terminal
And the source and drain are connected to the output node
3 of the second conductivity type connected between the power supply line
A transistor, and a gate input for the test mode signal.
The source / drain is connected to the output node and the second power supply line.
4th transistor of the second conductivity type connected between
And the output node is connected to the digital circuit unit.
And a test signal input circuit. 4. An analog terminal and the analog terminal
And an analog circuit connected to the
Analog and digital integrated circuit devices
Test signal input circuit for the analog
The signal from the terminal is used as the gate input and
The first transistor of the first conductivity type connected to the output node
Source and test mode signal as gate input and source
Rain is connected between the first power supply line and the first transistor.
A first conductivity type connected between the other of the source and the drain
And a signal from the analog terminal
Is the gate input and one of the source and drain is the output node
A third transistor of the second conductivity type connected to the point;
Use the inverted signal of the test mode signal as gate input and source
A drain is a source drain of the third transistor;
A second conductor connected between the other of the
A fourth transistor of an electrical type, wherein the output node is
Test characterized by being connected to a digital circuit part
Signal input circuit.