JPH03179914A - Bus driver circuit - Google Patents

Abstract

PURPOSE:To attain acceleration and a large scale and to reduce power consumption by providing a first logic circuit setting a input signal and an enable signal as input and whose output terminal is connected to the gate of a first N-channel MOS transistor, and a second logic circuit setting the output of the first logic circuit and the enable signal as the input and whose output terminal is connected to the gate of a second N-channel MOS transistor. CONSTITUTION:When an output control terminal is set at a high level, both output of NOR gates 1 and 2 go to low levels, and the N-channel MOS transistors 3 and 4 are turned off, and the output terminal OUT is set at a high impedance state. At this time, load capacitance on the output terminal OUT goes to the drain/source diffusion capacitance of the N-channel MOS transistors 3 and 4, and no diffusion capacitance of a P-channel MOS transistor is added. When the output control terminal is set at the low level, the inversion signal of an input terminal IN is transmitted to the output terminal OUT. However, the high level is set at potential decreased by the threshold voltage VTN of the N-channel MOS transistor than a high potential power source.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to (1) a bus driver circuit, in particular, a bus driver circuit that drives the output bus of a high-speed digital line space division switch or a loss point switch using MOS transistors; This invention relates to a bus driver circuit.

[Conventional technology]

Conventionally, as this type of bus driver circuit, a circuit as shown in FIG. 6, for example, has been used. This circuit performs high level, low level or high impedance control of the output terminal OUT using output control terminals E and E. When the output is enabled, that is, when E is at a high level and 100 is at a low level, the level of the input terminal IN is transmitted to the output terminal OUT.

It is the P-channel MOS transistor RO1 that pulls the output terminal OUT to a high level, and the N-channel transistor 62 pulls the output terminal OUT to a low level. The high impedance state of the output terminal is realized by a configuration in which the signal at the input terminal IN is subjected to NAND and NOR logic at the output control terminals E and E, respectively, and then input to the gates of both transistors.

As shown in FIG. 5, the bus driver circuits are arranged in an n×m matrix to form input buses IBI to IBn.

A crosspoint switch is a device that can switch the connection state between the output buses OBI'' and □OBm.

Input buses IBI to IBn each have a manual buffer IBUFI.
~IBUFn drives output bus OBI~OBm
is driven by each bus driver circuit Sw, . . . ~s w nm and is transmitted to the output buffers 0BUF'11-0BUF. No more than one bus driver circuit is enabled for each output bus.

[Problem to be solved by the invention]

When configuring a crosspoint switch using the above-mentioned bus driver circuit, consider the operating state of the crosspoint switch in the bus driver circuit shown in Figure 5, which requires wideband switching especially at frequencies above 150 MHz. , output terminals of n-1 bus driver circuits in a high impedance state are connected to one output bus, and input terminals of one output buffer are connected to one output bus.

Therefore, when n is large, the main load on the output bus is high
This is an output terminal in an impedance state, and M is off.
(OS) is the diffusion capacitance (with respect to the substrate) of the drain of the transistor. Therefore, in order to reduce the load on the output bus, it is desirable to reduce the area of the drain of the MOS transistor connected to the output terminal. However, reducing the area of the drain of the MOS transistor means reducing the width W of the gate of the MOS transistor, which means lowering the driving ability as a bus driver circuit. In other words, when making a crosspoint switch using a bus driver circuit, its speed and switch size are limited by the ratio of the diffusion capacitance per unit channel width of the MOS transistor connected to the output terminal and the driving capacity.

This can be expressed numerically as follows. First, the drive current per bus driver.

5- The diffusion capacitance C is approximated by a linear expression of the gate width W.

I = ・W k, , 2... Coefficient C" k 2 ・W Load capacitance C of n bus drivers, !=Charging the load C0 that does not depend on n to the logical amplitude ■ If we approximate the time T required for this as the output bus drive delay.

It is clear that the speed will not increase any further. Then, the larger the value of k2/1=capacity coefficient/current coefficient, the greater the delay. Furthermore, the smaller the logic amplitude V, the smaller the delay T.

The problem with the conventional bus driver circuit shown in FIG. Therefore, it is difficult to increase speed and scale due to the characteristics of the P-channel MOS transistor.

Also, P-channel MOS transistors are inferior to N-channel MOS transistors in terms of driving ability at the same W, so if you consider the fixture load, the W of a P-channel MOS transistor is lower than the W of an N-channel MOS transistor. Otherwise, the speed of the output bus will be limited by the waveform rise delay. As a result, the previous NAN
It is also necessary to increase W of the D gate 63, which means that the power consumption of the entire switch increases.

An object of the present invention is to provide a bus driver circuit that can be increased in speed and scale, and consumes less power.

[Means to solve the problem]

The bus driver circuit of the present invention includes a first N-channel M whose source-drain path is connected between a first power supply and an output terminal.
O8) a transistor and a second N-channel MOS whose source/drain path is connected between the output terminal and a second power supply;
a first logic circuit having an input signal and an enable signal as inputs and an output terminal connected to the gate of the first N-channel MOS transistor; and an output of the first logic circuit and the enable signal as inputs. and a second logic circuit whose output terminal is connected to the gate of the second ON channel MOS transistor.

〔Example〕

Hereinafter, the bus driver circuit of the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram for explaining one embodiment of the present invention. Input terminal IN and output control terminal l are NOR gate l
and the output of NOR gate 1 is an N-channel MOS
It is input to the gate of transistor 4. Further, the output of the NOR gate 1 and the output control terminal I are input to the NOR gate 2, and the output of the NOR gate 2 is input to the gate of the N-channel MOS transistor 3. The source and drain of the N-channel MOS transistor 4 are connected to the output terminal OUT and the high potential power supply VDD, respectively, and the source and drain of the N-channel MOS transistor 3 are connected to the low potential power supply VSS, respectively.
+ Connected to output terminal OUT.

When output control terminal E is at high level, NOR(G)1
and 2 outputs are both low level and null, N channel M
OS transistors 4 and 5 are turned off, and the output terminal OU
T becomes a high impedance state. At this time, the load capacitance attached to the output terminal OUT becomes the drain-source diffusion capacitance of the N-channel MOS transistors 3 and 4.
No diffusion capacitance of the P-channel MOS transistor is added.

When the output control terminal is at low level, the output terminal OUT
An inverted signal of the input terminal IN is transmitted to the input terminal IN. However, the high level is a potential lower than the high potential power supply by the threshold voltage VTN of the N channel MOS transistor 4.

This is because the present bus driver circuit operates as a source follower when the N-channel MO8+/run controller 4 is on. VTN is VDD-5■, ■5S-Ov due to the back gate effect, and when the substrate potential of N-channel transistors 3 and 4 is VS2, VTN is 15■
That's about it. Figure 2 shows the signal waveform. Therefore, the logic amplitude is reduced compared to the case of ■DD to ■ss. However, the threshold of the circuit that receives this signal level needs to be lowered.

Further, when operating as a source follower circuit, the mirror effect does not occur, so the driving ability of the NOR gate 1 for driving the gate of the N-channel MOS transistor 4 may be small. Also, another N
It has also become possible to drive OR gate 2.

When the NOR gate 1 is configured with a CMOS gate shown in FIG. 3, each M
The size of the O8+- transistors 31 to 34 can be reduced. This reduces the load on the input buses IBI to IBn when the loss point switch is configured as shown in FIG.

10- Furthermore, since the input terminal IN is directly input to the NOR gate without being received by an inverter, and is input to the gate of the P-channel MOS transistor 31 on the Vl and D side, the (output) impedance when the output is disabled is ), the mirror effect of the input of the NOR gate 1 seen from the input terminal IN is small, and the load capacitance of the input buses IBI to IBn becomes small.

According to the second circuit configuration, when a cross-point switch with n=m=32 is configured using a CMOS processor with a 1.2 μm rule, the delay from the input buffer sofa I BUF to the output buffer 0 EUF is 3 nsec, which is 10 nSec.
When a signal with a duty ratio of 50% is input with a C period, a power consumption value of 5 mW (Voo = 5 V) per channel has become possible.

FIG. 4 is a circuit diagram for explaining a second embodiment of the present invention. The difference from the first embodiment is that the output control terminal is directly connected to the gates of N-channel MOS transistors 41 and 42 connected to the output terminal, and the power supply V DD r V
S S to N channel MO8+- transistor 41.42
A P-channel MOS transistor 43 and an N-channel MOS transistor 44 are connected between the two MOS
8I - Located where the gate of the transistor is connected to the input terminal IN.

With this configuration, the load is light when the output terminal is in high impedance, and the logic amplitude of the output is small, as in the first embodiment. The advantage of this embodiment is that it requires fewer MOS transistors.

〔Effect of the invention〕

As explained above, in the bus driver circuit of the present invention, the high-level output from the conventional P-channel MOS transistor is replaced by an N-channel MOS transistor, which has a smaller diffusion capacitance than a P-channel MO8+ transistor.
This has the effect of reducing the diffusion capacitance during high impedance, lowering the output logic amplitude, and reducing the load on the gate in the previous stage of the bus driver output MOS transistor. Therefore,
By using the bus driver circuit of the present invention in a crosspoint switch, low power and high speed can be realized.

Furthermore, the configuration in which the input terminal is connected directly to the output control terminal without being buffered has the effect of reducing the input load when the output is high impedance.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram for explaining the first embodiment of the present invention, Fig. 2 is an operation waveform diagram of the circuit of Fig. 1, and Fig. 3 is a diagram of the NOR gate used in the circuit of Fig. 1. 4 is a circuit diagram for explaining the second embodiment of the present invention, FIG. 5 is a circuit diagram of a cross-point switch using a bus driver, and FIG. 6 is a circuit diagram of a conventional bus driver. It is. VDD...High potential power supply, ■, s...Low potential power supply, E, E...Output control terminal, IN, I
N...Input terminal, OUT...Output terminal, 3, 4, 33, 41°42.44.62...n
Channel MOS) transistor, 31, 32, 43.81
・・・・・・P channel MOS transistor, 1, 2・
...NOR gate, 63...NAND gate.

Claims (1)

[Claims] 1. A first N-channel MOS transistor with a source-drain path connected between a first power source and an output terminal; and a source-drain path connected between the output terminal and a second power source. a second N-channel MOS transistor, which receives an input signal and an enable signal, and whose output terminal is connected to the gate of the first N-channel MOS transistor; output and the enable signal are input, and the output terminal is the second N-channel MO.
and a second logic circuit connected to the gate of the S transistor. 2. The bus driver circuit according to claim 1, wherein the first logic circuit is a NOR gate constructed of CMOS gates. 3. A first N circuit whose source-drain path is connected between the first power supply and the output terminal and an enable signal applied to its gate.
a second N-channel MOS transistor whose source/drain path is connected between the output terminal and a second power source and whose gate is applied with the enable signal; and whose source/drain path is connected to the first power source. a P-channel MOS transistor connected between the first N-channel MOS transistor and having an input signal applied to its gate; and a P-channel MOS transistor whose source/drain path is connected between the second power supply and the second N-channel MOS transistor and whose gate and a third N-channel MOS transistor to which the input signal is applied.