JPH02290330A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To detect coincidence or discordance with a few element number by using a p-channel or an n-channel MOSFET to constitute an inverter circuit and a transmission gate circuit respectively. CONSTITUTION:When an input from a terminal 51 is logic 0, a p-channel FET 1 receiving a power supply VDD is turned on, an n-channel FET 4 is turned off and a signal 103 goes to logic 1. When the input 102 to the terminal 52 is logic 0, the n-channel FET 5 is turned on and the output 104 of the terminal 53 goes to logic 0. When the input 102 goes to logic 1, the p-channel FET 2 is turned on and the output 104 goes to logic 1. Moreover, when the input at the terminal 51 is logic 0, the p-channel FET 3 and the n-channel FET 4 keep the off-state. When the input 101 is logic 1, the n-channel FET of common source is turned on and the FETs 2, 5 are turned off. In this case, when the input 102 is logic 0, the FET 3 is turned on, the output 104 goes to logic 1, and when the input 102 goes to logic 1, the n-channel FET 6 is turned on and the output 104 goes to logic 0. Thus, only when the state of the inputs 51, 52 is coincident, the output goes to logic 0 and when discordant, the output is logic 1, then discordance is detected.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and in particular to a semiconductor integrated circuit that is configured with MOS transistors and that detects coincidence or mismatch of state values in two human input signals and outputs "1°". This study focuses on semiconductor integrated circuits that form logic circuits.

[Conventional technology]

Conventionally, in a semiconductor integrated circuit forming a logic circuit for detecting mismatch or coincidence of state values of two human input signals, the circuit configurations shown in FIGS. 5, 6, 7, and 8 are generally used. It is used. Of these, Figures 5 and 6
What is shown in the figure is an example of a logic circuit (hereinafter referred to as a mismatch detection circuit) that detects a mismatch between the state values of two human input signals and outputs a state value of "1". Shown is an example of a logic circuit (hereinafter referred to as a coincidence detection circuit) that detects coincidence of the state values of two human input signals and outputs a state value of "1". In FIG. 5, when the state values of the two human power signals at input terminals 59 and 60 both take "1" or "0", that is, when the state values of the two human power signals match, it is clear that the output The output signal at the terminal 61 is output as a state value "0". Further, when the state values of the two human power signals at the input terminals 59 and 60 do not match, the output signal at the output terminal 61 is always outputted as the state value "1". Therefore, the logic circuit shown in FIG. 5 is equipped with a logic function that outputs a state value of "0'° or "1" in response to the match or mismatch of the state values of the two human input signals, and Acts as a detection circuit.

FIG. 6 is an example of a mismatch detection circuit constructed using an inverter and a transmission gate circuit. When the state value of the input signal at the input terminal 62 is "0", the transmission gate circuit 17 is turned on, and the state value of the output signal at the output terminal 64 is in phase with the state value of the input terminal 63.

Also, the state value of the input signal at the input terminal 62 is “1”.
In this case, the transmission gate circuit 18 is turned on, but since the inverter 16 is involved, the bad value of the output signal at the output terminal 64 is
The phase is opposite to the state value of . Therefore, this logic circuit also has a logic function that outputs a state value of "0" or "1" in response to the match or mismatch of the state values of the two human input signals. In FIG. 7, two
O only when the state values of human input signals are both “0”
The output of the R circuit 20 becomes “0”°, and the input terminal 6
The state values of the two human power signals at 5 and 66 are both "1".
”, the output of the NAND circuit 21 is “1”
becomes. Therefore, in any of these cases, the state value of the output signal at the output terminal 67 is "1". If the state values of the two human input signals at the input terminals 65 and 66 do not match, the OR circuit 20 and the NAND circuit 21 Since all outputs are "1", the state value of the output signal at the output terminal 67 is always "0". Therefore,
In the case of this logic circuit, a state value of "1" or "0" is output in response to a match or mismatch between the state values of the two human input signals, and acts as a match detection circuit.

FIG. 8 shows a circuit configuration similar to that of the conventional example shown in FIG. 6, but the transmission gate circuit 2
This is because the relationship between the state value of the input signal at the input terminal 68, which is the gate control signal for each of the gates 5 and 26, and the state value of the output of the inverter 24 is in an opposite phase compared to the case of FIG. , the state value of the output signal at the output terminal 70 becomes "1'" when the state values of the input signals at the input terminals 68 and 69 match, and
The state value of the output signal at the output terminal 70 becomes "0" when the state values of the input signals at the input terminals 68 and 69 do not match. Therefore, this logic circuit functions as a coincidence detection circuit.

[Problem to be solved by the invention]

In the above-mentioned conventional semiconductor integrated circuit forming a logic circuit for detecting coincidence or mismatch of state values of two human input signals, in the case of FIGS. 5 and 7, at least 10
Requires an IIOS transistor for the device and also requires a sixth
In the case of FIG. 8 and FIG. 8, at least eight elements of 14OS transistors are required, and a large number of transistors must be used in one meter due to the configuration.
It has the disadvantage of becoming a hindrance to increasing the density of semiconductor integrated circuits. [Means for explaining the problem] The semiconductor integrated circuit of the present invention has a “1” or a “0”, respectively.
Detecting a mismatch between the state values of two input signals, the first input signal and the second input signal, in response to the input of a first input signal and a second input signal having a state value of ". A discrepancy detection circuit that outputs an output signal with a state value of "1°",
Alternatively, in a semiconductor integrated circuit forming a coincidence detection circuit that detects coincidence of state values of two input signals, the first input signal and the second input signal, and outputs an output signal with a state value of "1°", The mismatch detection circuit is configured such that the first input signal is connected to a first P-channel MOS transistor and a first N-channel MOS transistor forming an inverter circuit.
The gate of the transistor and the second P-channel MOS forming the transmission gate circuit The gate of the transistor and the third P-channel MOS forming the transfer gate circuit
the source of the P-channel MOS transistor, and the output of the inverter circuit forms the transmission gate circuit.
The second input signal is input to the gate of the transistor and the source of a third N-channel MOS transistor forming a transfer gate circuit, and the second input signal is input to a second P-channel MOS transistor forming a transmission gate circuit.
S transistor and the sources of the second N-channel MOS transistor, and the gates of the third P-channel MOS transistor and the third N-channel MOS transistor forming transfer gate circuits, respectively, and the second The drain output of the P-channel MOS transistor and the second N-channel MOS F-transistor and the third P-channel MOS transistor
~transistor and the drain output of the third N-channel type UOS transistor are commonly connected to form a mismatch detection circuit, the coincidence detection circuit comprising:
The first input signal is connected to a first input signal forming an inverter circuit.
of the P-channel type lIlOS transistor and the first N
input to the gate of the channel type MOS transistor, the gate of the second N-channel type MOS transistor forming the transmission gate 1 circuit, and the source of the third N-channel type VOS transistor forming the transfer gate circuit; The output of the inverter circuit is connected to a second transmission gate circuit forming the transmission gate circuit.
The gate of the P-channel MOS transistor and the third P-channel MOS transistor 1 forming the transfer gate circuit.
The second input signal is input to the source of the 40s transistor, and the second input signal is input to the second P channel type MOS transistor and the second N transistor forming the transmission circuit.
A source of a channel type MOS transistor, a third P channel type MOS transistor, and a third N channel type MOS transistor forming a transfer gate circuit, respectively.
the gate of the transistor, and the drain output of the second P-channel MOS transistor and the second N-channel MOS transistor and the third P-channel MOS transistor and the third N-channel MOS transistor. The drain outputs are commonly connected to form a coincidence detection circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention. This embodiment is an example of forming a logic circuit for detecting a mismatch between the state values of two human input signals, and as shown in FIG.
The device includes channel type MOS transistors 1 to 3 and N channel type MOS transistors 4 to 6.

In FIG. 1, a P-channel type 140s transistor 1 and an N-channel type MOS transistor 4 function as an inverter circuit that directly receives an input signal LOI from an input terminal 51 as a gate input and outputs a signal 103. In addition, P channel type MOS transistor 2 and N
The channel type MOS transistor 5 constitutes a transmission gate circuit whose source input is the input signal 102 from the input terminal 52.

When the input signal 101 from the input terminal 51 is at the 0° level, that is, the LOW level, the P-channel MOS transistor 1 is supplied with the power supply van as a source input.
turns on, and the N-channel MOS transistor 4
Since . is in the off state, the signal 103 becomes HIGH level. In this case, when the input signal 102 from the input terminal 52 is at the LO%I1 level, the N-channel MOS
The transistor 5 is turned on because its gate input is at the old GH level due to the signal 103, and the output terminal 53 outputs a signal 104 at the LO%ll level, that is, the "0" level. Further, in this case, when the incoming signal 102 from the input terminal 52 is at the HIGH level, the P-channel MOS transistor 2 is turned on because its gate input is at the LOW level due to the signal 101, and the output terminal 53 A signal 104 of HIGH level, ie, "1" level, is output from. Note that when the input signal 101 at the input terminal 51 is at the "On level," the P-channel MOS transistor 3 and the N-channel MOS transistor 6 are both held in the OFF state. When the input signal 101 is at the “1” level, that is, the old GH level, the source input is
Since the N-channel MOS transistor 4 connected to D is turned on and the signal 103 becomes the LOII level, the P-channel MOS transistor 2 whose gate input is directly the input signal 101 from the input terminal 5l and the signal 1
Both N-channel type MOS transistors 5 with gate input 03 are turned off. In this case, input terminal 5
When the input signal 102 from 2 is at the LO%II level, the input signal 102 at the HIGH level is used as the source input.
The P-channel MOS transistor 3 to which 1 is input is turned on, and the output terminal 63 outputs an output signal 104 at a HIGH level, that is, a "1" level. Further, in this case, the input signal 10 from the input terminal 52
2 is the old GH level, the L
The N-channel MOS transistor 6 to which the signal 103 at the OI1 level is input is turned on, and the output terminal 53 outputs an output signal 104 at the LOW level, that is, the "0° level."

Therefore, in the first embodiment, when the state values of the input signals at the input terminals 51 and 52 match, the output signal 104 at the "0" level is output to the output terminal 53; , an output signal 104 of "1" level is output to the output terminal 53. This truth table is as shown in FIG. That is, the first embodiment functions as a mismatch detection circuit.

Next, a second embodiment of the present invention will be described. FIG. 3 is a circuit diagram of a second embodiment of the invention. This embodiment is an example of forming a logic circuit for detecting coincidence of state values of two human input signals, and as shown in FIG. The device includes transistors 10 to 12.

In FIG. 3, a P-channel MOS transistor 7
The N-channel MOS transistor 10 directly receives an input terminal 105 from the input terminal 55 as a gate input, and functions as an inverter circuit that outputs a signal 107. Further, the P-channel type MOS transistor 8 and the N-channel type MOS transistor 11 constitute a transmission gate circuit whose source input is the input terminal 106 from the input terminal 56. As is clear from FIG. 3, the P-channel MOS transistor 7 and the N-channel MOS transistor 7 act as an inverter circuit.
The output side of the transistor 10 has a reverse phase relationship with that of the inverter circuit in the first embodiment shown in FIG.

Therefore, in the case of FIG. 3, when the state values of the input signals at the input terminals 55 and 56 match, the output signal 108 at the "1" level is output to the output terminal 57, and when they do not match, An output signal 108 of “0” level is output to the output terminal 57. This truth table is as shown in FIG. That is, the second example is
It can be seen that it operates as a coincidence detection circuit.

〔Effect of the invention〕

As described above in detail, the present invention is configured using one set of an inverter circuit and a transmission gate circuit, and one element of a P-channel MOS transistor and an N-channel MOS transistor, respectively, and is different from conventional circuits. It is possible to form a coincidence detection circuit and a mismatch detection circuit with a smaller number of elements than in the conventional structure, and there is an effect that an obstacle to increasing the density of semiconductor integrated circuits can be eliminated.

[Brief explanation of the drawing]

1 and 3 are circuit diagrams of the first and second embodiments of the present invention, respectively, and FIGS. 2 and 4 are truth tables in the first and second embodiments, respectively. 5, 6, 7, and 8 are circuit diagrams of conventional semiconductor integrated circuits, respectively. In the figure, 1 to 3.7 to 9...P channel type MOS transistor, 4 to 6, 10 to 12...
・N-channel MOS transistor, 13...
・AND circuit, 14.15...NOR circuit, 1
6,19,23.24...Inverter, 17.
1g, 25.26 --- one transmission gate circuit, 20 --- OR circuit, 21.22 ---
・NAND circuit. Agent Patent Attorney Uchihara Onyu 1 Zuyu 2t! 1 Sub-concave flash mouth f3-AND rotation 74-15-NOR mouth roadbed diagram 1G, I'l---Inhata 17-18-1. Seki

Claims (1)

[Scope of Claims] In response to the input of a first input signal and a second input signal each having a state value of "1" or "0", the first input signal and the second input signal are A discrepancy detection circuit that detects a discrepancy between the state values of two input signals and outputs an output signal with a state value of "1", or a discrepancy detection circuit that detects a discrepancy between the state values of the two input signals, the first input signal and the second input signal In a semiconductor integrated circuit forming a coincidence detection circuit that detects coincidence and outputs an output signal with a state value of "1," the mismatch detection circuit is configured such that the first input signal is connected to a first input terminal forming an inverter circuit. The gates of the channel type MOS transistor and the first N-channel type MOS transistor, and the second gate forming the transmission gate circuit.
the gate of a P-channel MOS transistor, and a third P-channel MOS transistor forming a transfer gate circuit.
the source of the S transistor, and the output of the inverter circuit is input to the gate of the second N-channel MOS transistor forming the transmission gate circuit, and the third N-channel MO5 transistor forming the transfer gate circuit. and the source of
The second input signal connects the sources of a second P-channel MOS transistor and a second N-channel MOS transistor forming a transmission gate circuit;
a third P, each forming a transfer gate circuit;
the gates of the channel type MOS transistor and the third N-channel type MOS transistor, and the drain output of the second P-channel type MOS transistor and the second N-channel type MOS transistor and the third
The drain outputs of the P-channel MOS transistor and the third N-channel MOS transistor are commonly connected to form a mismatch detection circuit, and the coincidence detection circuit is configured such that the first input signal is The gates of the first P-channel MOS transistor and the first N-channel MOS transistor forming an inverter circuit and the gates of the second N-channel MOS transistor forming a transmission gate circuit form a transfer gate circuit. Third N-channel MOS
The output of the inverter circuit is input to the source of the transistor, and the output of the inverter circuit is input to the gate of the second P-channel MOS transistor forming the transmission gate circuit, and the third P-channel MOS transistor forming the transfer gate circuit. and the second input signal is input to the sources of a second P-channel MOS transistor and a second N-channel MOS transistor forming a transmission circuit, respectively, and a third input signal forming a transfer gate circuit. P-channel MOS transistor and third N-channel MOS
the gate of the transistor, and the drain output of the second P-channel MOS transistor and the second N-channel MOS transistor, and the third P-channel MOS transistor and the third N-channel MOS transistor.
The drain output of the OS transistor is commonly connected,
A semiconductor integrated circuit configured to form a coincidence detection circuit.