JPH05152929A - Cmos input circuit - Google Patents

Abstract

PURPOSE:To reduce a signal propagation delay time between an input and an output by setting a source potential of a PMOS transistor(TR) in an input circuit section to a power supply potential through the conduction of a switch means at the initial state of switch operation and non-conduction after the completion of operation. CONSTITUTION:When a level of an input signal IN changes from an H into an L level, a PMOS TR 13 is conductive and an NMOS TR 14 is nonconductive. Since a potential at a node 16 reaches in advance a power supply voltage VCC) a larger current than that with the case when the potential of the node 16 is less than the voltage VCC flows to the TR 13. Thus, the potential at an output node 12 rises toward an H level rapidly so as to reduce the signal propagation delay time between the input and output after an input signal IN changes till an output signal OUT changes. When the potential at the node 12 rises to some degree, a PMOS TR 18 changes the conduction state and then nonconduction state sequentially.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS having a function of converting a TTL level signal into a CMOS level signal.
Type input circuit.

[0002]

2. Description of the Related Art When supplying a TTL level signal to a CMOS circuit, the TTL level signal cannot be directly input into the CMOS circuit because the input amplitude in the CMOS circuit and the TTL output amplitude do not match. .. Therefore, conventionally, a TTL level signal is converted to a CMOS level by lowering the circuit threshold voltage in the input section of the CMOS circuit. 17A to 17D are circuit diagrams each showing a configuration of a conventional input circuit for converting a TTL level signal into a CMOS level.

The circuit shown in FIG. 17A is a P channel MOS.
This is a CMOS inversion circuit in which the gates of the transistor 31 and the N-channel MOS transistor 32 are connected in common, and
The circuit threshold voltage is adjusted by the ratio of the channel width W of the S transistors 31 and 32. That is, when the channel width of the P-channel MOS transistor 31 is WP and the channel width of the N-channel MOS transistor 32 is WN, WP <WN
Both channel widths are set so as to satisfy the following relationship, and the circuit threshold voltage is lowered.

However, in this circuit, since the amplitude of the TTL level signal does not reach the power supply level (Vcc), the P channel MOS transistor 31 is not completely turned off even when the input signal is at the "H" level. However, there is a drawback in that the through current continues to flow between the power supplies and the characteristic of the low current consumption peculiar to the CMOS circuit is impaired.

The circuits shown in FIGS. 17B to 17D are
In the inverting circuit including the P-channel MOS transistor 33 and the N-channel MOS transistor 34, the source node 35 of the P-channel MOS transistor 33 and the power supply voltage V
The circuit threshold voltage is lowered by adding a level shift element for lowering the source potential of the MOS transistor 33 below the power supply potential Vcc between the node of cc and the node of cc. b)
In the circuit of, the N-channel MOS transistor 36 is (c)
In the circuit of (3), a diode 37 is used, and in the circuit of (d), a bipolar NPN transistor 38 is used.

However, the circuits shown in FIGS. 17B to 17D have the following problems. For example, in the case of the circuit of FIG. 17B, when the P-channel MOS transistor 33 changes from the non-conducting state to the conducting state, this M
Since the source potential of the OS transistor 33 is lower than the power supply potential Vcc, the current flowing between the source and drain of the MOS transistor 31 is suppressed as compared with the case where this potential is the power supply potential Vcc. In addition, N channel MO
Since current flows through the S-transistor 36, the P-channel M
The potential of the source of the OS transistor 33 instantaneously drops to near the ground level. Therefore, there is a drawback that the signal propagation delay time between the input and the output when the input signal changes from "H" level to "L" level and the output signal changes from "L" level to "H" level. .

Further, in the prior art, the input section is composed of only P-channel and N-channel MOS transistors, and the threshold voltage of the P-channel MOS transistor is made higher than that of other than the input section to lower the circuit threshold voltage of the input section. Has been done. However, this method has a drawback that the number of masks used during manufacturing and the number of steps are increased, and the manufacturing cost is high. In addition, the current is suppressed because the threshold voltage of the P-channel MOS transistor is high,
As in the conventional circuits (b) to (d), there is a drawback that the signal propagation delay time between the input and the output becomes long when the input signal changes from the "H" level to the "L" level.

[0008]

As described above, in the conventional circuit, there is a problem that the low current consumption property is impaired, or the low current consumption property is not impaired, but the signal propagation delay time between the input and output becomes long. is there.

The present invention has been made in consideration of the above circumstances, and an object thereof is to achieve low current consumption and to prevent an increase in signal propagation delay time between input and output. It is to provide a CMOS type input circuit.

[0010]

In the CMOS type input circuit of the present invention, an input circuit section composed of P channel and N channel MOS transistors and a source of the P channel or N channel MOS transistor in the input circuit section are provided. And P-channel or N
A potential shift means for shifting the source potential of the channel MOS transistor from the power source potential, and a switch operation when a MOS transistor provided in parallel with the potential shift means and having its source potential shifted by the potential shift means perform a switch operation. The switch means is electrically connected in the initial stage and turned off after the switch operation is completed.

[0011]

When the P-channel MOS transistor in the input circuit section performs the switch operation, the switch means is conductive at the beginning of the switch operation and the source potential of the P-channel MOS transistor is set to the power supply potential, and the switch operation is completed after the switch operation is completed. The means becomes non-conductive.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows the structure of a CMOS type input circuit according to the first embodiment of the present invention. The circuit of this embodiment has an inverting function of inverting an input signal of TTL level and outputting it at a CMOS level, and is a P channel MOS in which each gate is connected to an input node 11 and each drain is connected to an output node 12. Transistor 13 and N channel M
The input circuit section 15 including the OS transistor 14, the power supply node to which the positive voltage Vcc is supplied, and the source node 16 of the P-channel MOS transistor 13 in the input circuit section 15 are described.
N-channel MOS for level shift with the source and drain inserted between and the gate connected to the power supply node
It is composed of a transistor 17 and a P-channel MOS transistor 18 which has a source-drain inserted between the power supply node and the node 16, a gate connected to the output node 12, and which acts as a switch element.

In the input circuit having the above configuration, the input circuit section
Since the source-drain of the level-shifting N-channel MOS transistor 17 is inserted between the source node 16 of the P-channel MOS transistor 13 and the power supply node in 15, the source node of the P-channel MOS transistor 13 is formed. The potential of 16 drops below the power supply potential Vcc, the circuit threshold voltage drops below that of a normal CMOS inversion circuit, and TT
It is suitable for L level.

On the other hand, when the input signal IN supplied to the input node 11 is at the "H" level, the P channel MOS transistor 13 is in the non-conductive state and the N channel MOS transistor 14 is in the input circuit section 15. In the conductive state, the output signal OUT at the output node 12 is "L"
It is at a level. At this time, the P-channel MOS transistor 18 whose gate receives the "L" level output signal OUT is in a conductive state. Therefore, at this time, P
The potential of the source node 16 of the channel MOS transistor 13 rises to the power supply potential Vcc and is stable.

Next, when the input signal IN is inverted from "H" level to "L" level, the P-channel MOS transistor 13 becomes conductive and the N-channel MOS transistor 14 becomes non-conductive. At this time, since the potential of the node 16 has been set to Vcc in advance, a larger current flows through the MOS transistor 13 as compared with the case where the potential of the node 16 is lower than Vcc. Therefore, the potential of the output node 12 rapidly rises toward the "H" level, and the signal propagation delay time between the input and the output from the change of the input signal IN to the change of the output signal OUT can be shortened. .. And
When the potential of output node 12 rises to some extent, P-channel MOS transistor 18 sequentially changes from conductive state to non-conductive state. After the P-channel MOS transistor 18 is turned off, the node 16 is charged through the N-channel MOS transistor 17.

FIG. 2 shows each signal waveform when the output signal OUT changes from the "L" level to the "H" level after the input signal IN changes from the "H" level to the "L" level in the above embodiment circuit. The output signal OUT1 is in the case of this embodiment, and the output signal OUT2 is shown in FIG.
(B) to (d) of the conventional circuit.
As shown in the figure, the time when the potential of the output signal OUT1 starts changing is earlier than the time when the potential of the output signal OUT2 starts changing in the conventional circuit, and the signal propagation delay time between the input and output is improved as compared with the conventional case. ing.

Further, in the circuit of this embodiment, it is not necessary to set the channel width of each MOS transistor so that there is an extreme difference as in the conventional circuit shown in FIG. Through-current does not continue to flow, and the low current consumption characteristic of a CMOS circuit can be maintained.

FIG. 3 shows a second embodiment of the present invention, which is a case where the present invention is applied to one having an inversion function.
The circuit of this embodiment is different from that of FIG. 1 in that a diode 19 is used in place of the N-channel MOS transistor 17 used as a level shift element, and is otherwise the same. The description is omitted.

FIG. 4 shows a third embodiment of the present invention, which is a case where the present invention is applied to one having an inversion function.
The circuit of this embodiment is different from that of FIG. 1 in that an NPN type bipolar transistor 20 is used in place of the N channel MOS transistor 17 used as a level shift element. Since they are the same, the description will be omitted.

FIG. 5 shows a circuit of a first modification of the circuit of the first embodiment. The circuit of the first embodiment has a signal inverting function, but this modified circuit has two input signals IN1 and IN2, and the NAND circuit for both signals is used.
A NAND type input circuit unit 15 that takes logic is used. That is, the input circuit section 15 is composed of two P-channel MOS transistors 21 and 22 and N-channel MOS transistors 23 and 24, respectively. The sources and drains of the two P-channel MOS transistors 21 and 22 are inserted in parallel between the node 16 and the output node 12, and the gate of the MOS transistor 21 receives one input signal IN1. The gate of the MOS transistor 22 is connected to the node 11A and the input node 11B to which the other input signal IN2 is supplied. Also, 2
Drains of N-channel MOS transistors 23, 24
The sources are inserted in series between the output node 12 and the ground node to which the ground voltage is supplied. The gate of the MOS transistor 23 is connected to the input node 11B and the MOS transistor 23 is connected to the ground node.
The 24 gates are connected to the input node 11A, respectively.

In the case of this modified circuit, two input signals I
When one of N1 and IN2 goes to "L" level and the potential of the output node 12 rises, the P channel MO
The potential of the node 16 is set to the power supply potential V by the S transistor 18.
Since it is set to cc, the potential of the output node 12 rapidly rises toward the "H" level as in the case of the embodiment shown in FIG.

FIG. 6 shows a circuit of a second modification of the circuit of the first embodiment. In this modified circuit, the input signal is I
A NOR type input circuit section 15 which is composed of two of N1 and IN2 and takes NOR logic of both signals is used. That is, the input circuit section 15 is composed of two P-channel MOS transistors 21 and 22 and N-channel MOS transistors 23 and 24, respectively, as in the case of FIG. 5, but unlike the case of FIG. P channel MOs
The node 16 is between the source and drain of the S transistors 25 and 26.
Between the output node 12 and the output node 12 and two N
The drains and sources of the channel MOS transistors 23 and 24 are inserted in parallel between the output node 12 and the ground node.

In the case of this modified circuit, two input signals I
Both N1 and IN2 go to "L" level, and output node 12
When the potential of the output node 12 rises, the potential of the node 16 is set to the power source potential Vcc by the P-channel MOS transistor 18 in advance, so that the potential of the output node 12 rapidly increases as in the case of the embodiment of FIG. It rises toward the "H" level.

FIG. 7 shows a circuit of a third modification of the circuit of the first embodiment. This modified circuit has a multi-input NA.
The input circuit section 15 that takes the ND logic is used. That is, in the input circuit section 15, the P-channel MOS transistors 25, 2 whose sources and drains are connected in parallel and whose gates are respectively connected to a plurality of input nodes are connected.
, And N-channel MOS transistors 26, 26, ... In which the source and drain are connected in series, and each gate is connected to each of the plurality of input nodes.

FIG. 8 shows a circuit of a fourth modification of the circuit of the first embodiment. This modified circuit has a multi-input NO
The input circuit section 15 which takes R logic is used. That is, in the input circuit section 15, P-channel MOS transistors 25, 25, whose sources and drains are connected in series and whose gates are respectively connected to a plurality of input nodes,
, And N-channel M in which the source and drain are connected in parallel, and each gate is connected to each of the plurality of input nodes.
It is composed of OS transistors 26, 26 ,.

9 to 12 show first to fourth modified circuits of the second embodiment circuit of the present invention shown in FIG. 3, respectively. Each of these modified circuits is shown in FIG.
Since the modification similar to that of FIG. 8 is applied to the circuit of the second embodiment of FIG. 3, the portions corresponding to those of FIG. 5 to FIG. 8 are designated by the same reference numerals and the description thereof will be omitted.

FIGS. 13 to 16 show first to fourth modified circuits of the third embodiment circuit of the present invention shown in FIG. 4, respectively. Since each of these modified circuits is also the same as the modified circuits of FIGS. 5 to 8 applied to the circuit of the third embodiment of FIG. 4, the parts corresponding to those of FIGS. The description is omitted.

It is needless to say that the present invention is not limited to the above-mentioned embodiments or modified examples, and various modifications can be made. For example, in the above-described embodiment, the case where the source potential of the P-channel MOS transistor in the input circuit section 15 is shifted from the power supply potential Vcc by the level shift element has been described. This is the source of the N-channel MOS transistor in the input circuit section 15. It is needless to say that the present invention can be applied to an input circuit in which a level shift element is provided between a ground node and a ground node to level shift the source potential on the ground potential side.

[0030]

As described above, according to the present invention,
It is possible to provide a CMOS type input circuit capable of achieving low current consumption and preventing the signal propagation delay time between input and output from becoming long.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment circuit of the present invention.

FIG. 2 is a signal waveform diagram in the circuit according to the first embodiment.

FIG. 3 is a circuit diagram of a second embodiment circuit according to the present invention.

FIG. 4 is a circuit diagram of a circuit according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram of a first modification circuit of the first embodiment.

FIG. 6 is a circuit diagram of a second modification circuit of the first embodiment.

FIG. 7 is a circuit diagram of a third modification circuit of the first embodiment.

FIG. 8 is a circuit diagram of a fourth modification circuit of the first embodiment.

FIG. 9 is a circuit diagram of a first modification circuit of the second embodiment.

FIG. 10 is a circuit diagram of a second modification circuit of the second embodiment.

FIG. 11 is a circuit diagram of a third modification circuit of the second embodiment.

FIG. 12 is a circuit diagram of a fourth modification circuit of the second embodiment.

FIG. 13 is a circuit diagram of a first modification circuit of the third embodiment.

FIG. 14 is a circuit diagram of a second modification circuit of the third embodiment.

FIG. 15 is a circuit diagram of a third modification circuit of the third embodiment.

FIG. 16 is a circuit diagram of a fourth modification circuit of the third embodiment.

FIG. 17 is a circuit diagram of a conventional circuit.

[Explanation of symbols]

11, 11A, 11B ... Input node, 12, 12A, 12B ... Output node, 13, 21, 22, 25 ... P-channel MOS transistor, 14, 23, 24, 26 ... N-channel MOS transistor,
15 ... Input circuit section, 16 ... Node, 17 ... N for level shift
Channel MOS transistor, 18 ... P channel MOS transistor acting as switch element, 19 ... Diode, 20 ... NPN type bipolar transistor,

Claims (11)

[Claims] 1. An input circuit section configured using P-channel and N-channel MOS transistors, and a P-channel or N-channel MO in the input circuit section.
A potential shift means inserted between the source of the S-transistor and the power supply for shifting the source potential of the P-channel or N-channel MOS transistor from the power supply potential is provided in parallel with the potential shift means, and is provided by the potential shift means. A CMOS-type input circuit, comprising: a switching means that is turned on at the beginning of the switching operation and is turned off after the switching operation of the MOS transistor whose source potential is shifted, when the switching operation is performed. 2. The C according to claim 1, wherein the operation of the switch means is controlled based on an output signal of the input circuit section.
MOS type input circuit. 3. The CMOS type input circuit according to claim 1, wherein the potential shift means is composed of a MOS transistor. 4. The CMOS type input circuit according to claim 1, wherein the potential shift means is composed of a diode. 5. The CMOS type input circuit according to claim 1, wherein the potential shifting means is composed of a bipolar transistor. 6. The CMOS type input circuit according to claim 2, wherein the switch means is composed of a MOS transistor whose gate is connected to the output terminal of the input circuit section. 7. An input circuit section composed of P-channel and N-channel MOS transistors, and a source of the P-channel MOS transistor inserted between the source and the power source of the P-channel MOS transistor in the input circuit section. A potential shift means for shifting the potential from the power supply potential and a P channel M provided in parallel with the potential shift means and having its source potential shifted by the potential shift means.
When the OS transistor performs a switch operation, the CMOS type input is provided with a switch means composed of a P-channel MOS transistor which is conductive at an initial stage of the switch operation and is in a non-conductive state after the switch operation is completed. circuit. 8. The CMOS type input circuit according to claim 7, wherein the potential shift means is composed of a MOS transistor. 9. The CMOS type input circuit according to claim 7, wherein the potential shifting means is composed of a diode. 10. The CMOS type input circuit according to claim 7, wherein the potential shift means is composed of a bipolar transistor. 11. The CMOS type input circuit according to claim 7, wherein a gate of a P-channel MOS transistor forming the switch means is connected to an output terminal of the input circuit section.