JPH0431205B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention is directed to controlling the amount of rush current flowing when both are turned on simultaneously in a circuit having a PNP transistor and an NPN transistor, and furthermore, controlling the amount of rush current that flows when both are turned on at the same time. Complementary MIS that can reduce power consumption by reducing the power consumption to almost 0, realizing a 3-state circuit, and eliminating the current flowing in the circuit in a high impedance state.
This invention relates to a bipolar mixed 3-state gate circuit.

(2) Technical background CMIS circuit (hereinafter referred to as PMOS transistor) consisting of PMIS transistor (hereinafter referred to as PMOS transistor) and NMIS transistor (hereinafter referred to as NMOS transistor)
CMOS circuits (CMOS circuits) have low power consumption, so their use as semiconductor integrated circuits is expanding. In addition, since the circuit that connects a PNP transistor and an NPN transistor in series between the power supplies V _DD and V _SS with their collectors common is made of bipolar transistors, the output current can be increased, so the drive capacity is large and the output buffer is increased. This is suitable.

In addition, the 3-state circuit has low level, high level,
It has three high-impedance output states.
For example, this circuit is used when a plurality of circuit elements are connected to one bus and only the necessary circuit elements are accessed from the bus.

(3) Prior art and problems However, when a 3-state circuit is realized by combining the bipolar transistor circuit with a CMOS circuit, when the input signal transitions from high level to low level or from low level to high level, the output stage There was a problem in that the PNP transistor and NPN transistor were turned on at the same time, causing a rush current to flow between the power supplies V _DD and V _SS . Furthermore, due to this rush current, even though a bipolar transistor circuit is provided in the output stage, there is a drawback that a large output current cannot be passed.

(4) Purpose of the Invention The present invention reduces power consumption by controlling the rush current, and allows a large output current to flow, making it suitable for an output buffer and a complementary MIS bipolar mixed circuit capable of realizing a 3-state circuit. The purpose is to provide a 3-state gate circuit.

(5) Structure of the Invention According to the present invention, the above-mentioned object is to provide a first P-type MIS transistor connected to a high-potential power supply side, a first N-type MIS transistor connected to a low-potential power supply side, and a first P-type MIS transistor connected to a low-potential power supply side. a first impedance element provided between the transistors, the first P-type and N-type impedance elements;
A first complementary MIS gate circuit receives an input signal in common to the gates of the P-type MIS transistors, a second P-type MIS transistor connected to the high potential power supply side, and a second P-type MIS transistor connected to the low potential power supply side. an N-type MIS transistor and a second impedance element provided between the two transistors;
a second complementary MIS gate circuit that receives an input signal in common to the gates of the MIS transistors and the gates of the N-type MIS transistors; and a pull-up gate circuit whose base is connected to the connection point between the first P-type MIS transistor and the first impedance element. and a pull-down bipolar transistor whose base is connected to a connection point between the second N-type MIS transistor and the second impedance element, and the pull-up bipolar transistor and the pull-down bipolar transistor are A bipolar circuit that is controlled separately and independently by the first impedance element and the second impedance element and has a connection point of the bipolar transistor as an output terminal, and is connected between a high potential power supply and the base of the pull-up bipolar transistor. and a third N-type MIS transistor connected between a low potential power supply and the base of the pull-down bipolar transistor.
The third P type and N type with MIS transistor
This is achieved by providing a complementary BiMIS 3-state circuit characterized in that an enable signal and its inverted signal are applied to the gates of MIS transistors, respectively.

(6) Embodiments of the invention Next, embodiments of the invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the CMOS bipolar mixed three-state gate circuit of the present invention. 1st, 2nd
The sources of PMOS transistors P ₁ and P ₂ are connected to the power supply V _DD
connected to the first and second NMOS transistors.
The sources of N ₁ and N ₂ are connected to the power supply V _SS , and the sources of the first and second PMOS transistors P ₁ and P ₂ and the first and second
The gates of the NMOS transistors N ₁ and N ₂ are commonly connected to the input terminal IN. And the first PMOS
Transistor P ₁ and first NMOS transistor N ₁
constitutes the first CMOS transistor circuit,
The second PMOS transistor P ₂ and the second NMOS transistor N ₂ constitute a second CMOS transistor circuit. Also, PNP transistor _T1 and
The emitters of NPN transistor T ₂ are each a power supply
They are connected to V _DD and V _SS , forming a pull-up transistor and a pull-down transistor, and their collectors are commonly connected to the output terminal OUT. Additionally, a third PMOS transistor P ₃ and a third
The sources of _the NMOS transistor N ₃ are connected to the power supplies V _DD and V _SS respectively, and the enable signal T _C is applied to the gate of the third PMOS transistor P ₃ . An enable signal T _C is applied via an inverter I to control the output terminal to a high impedance state.

Then, for example, a resistor R 1 is used as a first impedance element, and a resistor R ₁ is connected to the first and third PMOS transistors P ₁ ,
the drain of P ₃ and the first NMOS transistor N ₁
The connection point B of this resistor _R1 and the drain of the first PMOS transistor is connected to the base of the PNP transistor _T1 . Further, as a second impedance element, for example, a resistor R ₂ is inserted and connected between the drain of the second PMOS transistor and the drains of the second and third NMOS transistors, and this resistor R ₂ and the second
The connection point C with the drain of the NMOS transistor _N2 is connected to the base of the NPN transistor _T2 .

Complementary type according to the present invention configured as described above
The operation of the embodiment of the CMOS bipolar mixed three-state gate circuit will be described below.

First, when the enable signal is low level, the third PMOS transistor _P3 and
Since both NMOS transistors _N3 are turned off,
A bipolar CMOS gate circuit operation that has the same configuration as the bipolar CMOS circuit described in the previously filed Japanese Patent Application No. 130438/1983, and the output signal changes to high level or low level in response to the high level or low level of the input signal. This is what we do.

That is, the operation of the bipolar CMOS gate circuit having such a configuration will be explained using the voltage transfer characteristic diagrams shown in FIGS. 2 and 3. In particular, Figure 3 shows the input signal voltage
The voltage transfer characteristics between V _iN , the potential V _B at point B, and the potential V C at point _C , which are indicated by solid lines, will be explained. First, the case where the input voltage V _iN at the input terminal IN is at a low level will be described. Input voltage V _iN is low level (nearly 0V)
When , PMOS transistors P ₁ and P ₂ are on,
Since NMOS transistors N ₁ and N ₂ are off,
The connection point B becomes a high level (approximately V _DD = 5V),
On the other hand, regarding the connection point C, the base current of the NPN transistor _T2 flows through the resistor _R2 , and V _SS =0V.
It is clamped to a high level by the base-emitter forward voltage drop V _BE (0.8V) of the NPN transistor _T2 . Therefore, PNP transistor T ₁
is off and NPN transistor _T2 is on.

In other words, the input voltage V _iN =L level, that is, approximately
When V _SS = 0V, the potential V _B at point B is approximately V _DD
(5V), and the potential V _C at point C is V _SS +V _BE .

Conversely, when the input voltage V _iN is at a high level,
PMOS transistor P ₁ is off, NMOS transistor N ₁ is on, PMOS transistor P ₂ is off,
Since NMOS transistor _N2 is in the on state,
Point C is at a low level (approximately 0V), and the NPN transistor _T2 is in an off state. At point B, the PNP transistor T ₁ is turned on and the base current of the PNP transistor T ₁ flows through R ₁ and the NMOS transistor N ₁ , so V _DD − V _BE (Forward voltage drop between the base and emitter of the PNP transistor T ₁ V _BE is clamped to approximately 0.8V). That is, when the input voltage V _iN = V _DD , the voltage at point _B is V _C = V _DD − V _BE =
It is set to 4.2V.

Next, for the sake of easy understanding of the operation, a case where the input voltage V _iN changes from a low level to a high level, ie, in the order of , , , as shown in FIG. 2, will be described.

First, as mentioned above, when the input voltage V _iN is at a low level, PMOS transistors P ₁ and P ₂ are turned on.
Since NMOS transistors N ₁ and N ₂ are off,
The potential V _B at point B is approximately V _DD level, and the potential V _C at point C is
Since NPN transistor T ₂ is on, V _SS +V _BE
is clamped to. As the input voltage V _iN increases,
NMOS transistor as shown in Figure 2
When the threshold voltage Vth (N) of N ₁ and N ₂ is reached,
Since the NMOS transistor _N1 is turned on, _VB gradually drops as shown in FIG. but,
V _C is determined by the forward voltage V _BE of the NPN transistor T ₂ and is clamped to V _SS +V _BE because the NMOS transistor N ₂ is on but not yet sufficiently turned on.

Next, when the input voltage V _iN increases further,
Since the NMOS transistor N ₁ becomes deeply turned on, V _B drops further. At this time, NMOS
Since the transistor N ₂ is also turned on deeply, V _C is influenced by the impedance of the NMOS transistor N ₂ more strongly than the impedance between the base and emitter of the NPN transistor _{T 2 at} the point shown by . The base potential of will be lower than V _SS +V _BE . Therefore, the NPN transistor T ₂ is turned off, and V _C gradually begins to fall. At this point, the base potential of the PNP transistor T ₁ becomes a high level on the high power supply V _DD side due to the PMOS transistor P ₁ in the on state, and since the voltage between the base and emitter does not exceed V _BE , the PNP transistor T ₁ remains off.

Then, when the input voltage V _iN increases further,
As shown at point , the NMOS transistor N ₁ is turned on sufficiently deeply, so the potential at point B becomes sufficiently low through the resistor R ₁ and becomes less than V _DD −V _BE .
Turn on PNP transistor _T1 . Therefore,
V _B will be clamped to the voltage V _DD − V _BE .

Therefore, then PNP transistor T ₁ turns from on to off, and then NPN transistor T ₂
goes from off to on, so between
PNP transistor T ₁ and NPN transistor
Both T and ₂ are off.

Then, the input voltage V _iN further increases and the PMOS
When the threshold voltage Vth (P) of transistors P ₁ and P ₂ is exceeded (point in Figure 2), PMOS transistor P ₂ is completely turned off and NMOS transistor N ₂ is sufficiently turned on, so V _C becomes low. as shown
V _SS . At this time, since the NMOS transistor N ₁ is also sufficiently turned on, the NPN transistor T ₁ is also turned on, and V _B remains clamped to V _DD −V _BE .

Then, the input voltage V _iN rises above Vth (P) and
When V _DD is reached (in Figure 2), V _B is V _DD −
remains clamped at V _BE and V _C is held at V _SS .

Next, the input voltage V _iN is now reversely changed from V _DD to,
, will be explained below. input voltage
When V _iN falls to Vth(P), PMOS
Transistor P ₂ gradually starts conducting, so
As shown in , V _C increases from V _SS to V _SS +V _BE . At this time, the base potential of the PNP transistor _T1 is at a low level because the NMOS transistor _N1 is on and the PMOS transistor _P1 is not yet sufficiently conductive. Therefore, since the PNP transistor T ₁ is conductive, V _B remains clamped to V _DD −V _BE .

When the input voltage V _iN further decreases, the conduction of the PMOS transistor P ₁ becomes sufficiently deep, so that the potential at point B rises and the PNP transistor T ₁ is turned off at that point. Therefore, V _B starts to rise as shown in the figure. At this time, the PMOS transistor _P2 also becomes more conductive, so the potential of V _C continues to rise.

Next, as the input voltage V _iN further decreases, V _C becomes
When the threshold value V _BE of the NPN transistor T ₂ is exceeded,
NPN transistor T ₂ turns on and V _C is clamped to V _SS + V _BE as shown.

In other words, when the input voltage V _iN is higher,
PNP transistor T ₁ is on, input voltage V _iN
When is low, PNP transistor _T2 is turned on,
Between the PNP transistor _T1 and NPN
Both transistors _T2 are turned off. Therefore, since both of them are not turned on, no rush current flows.

Next, when the input voltage V _iN decreases further, NMOP
When the threshold value Vth (N) of the transistors N ₁ and N ₂ is about to be lowered or lower, the NMOS transistor N ₁ turns off at the point. At this time, PMOS transistor _P2
is on, so V _C remains clamped to V _SS + V _BE .

In Fig. 3, the dashed-dotted lines V _B ′, V _C ′ represent the resistances R ₁ ,
When R ₂ is large and the PNP transistor T ₁
requires a larger input voltage V _iN for conduction and V _B to be clamped to V _DD − V _BE ;
A smaller input voltage V _iN is required because the NPN transistor T ₂ conducts and V _C is clamped to V _SS +V _BE . Therefore, transistors T ₁ , T ₂
The range of input voltages that can be turned off simultaneously is large.

In addition, in FIG. 3, the two-dot chain lines V _B ″ and V _C ″ represent the case where the resistances R ₁ and R ₂ are small, contrary to the above, and
The input voltages at which PNP transistor T ₁ and NPN transistor T ₂ are turned on become close. When the resistors R ₁ and R ₂ are smaller, for example 0, there is an input voltage range in which the PNP transistor T ₁ and the NPN transistor T ₂ are turned on simultaneously, and as in the conventional case, the PNP transistor T ₁ and the NPN transistor T ₂ are turned on. Ratsuyu flows through it.

As detailed above, according to this embodiment,
By combining a CMOS transistor, a bipolar transistor, and a resistor, it is possible to adjust the input voltage range at which the bipolar transistor turns off and off, and completely eliminate the bipolar transistor from turning on and off. .

Then, when the enable signal T _C goes low level,
PMOS transistor P ₃ and NMOS transistor N ₃
Since both are turned on, the base potential of the PNP transistor _T1 becomes a high level, and the base potential of the NPN transistor _T2 becomes a low level. For this reason,
PNP transistor T ₁ and NPN transistor T ₂
are both forced off, so the input signal
When V _iN changes to high or low level, the output OUT is maintained in a high impedance state.

Therefore, depending on the high or low level of the enable signal _TC , the embodiment of FIG. 1 operates as a three-state gate circuit.

By the way, when the enable signal T _C becomes low level and transistors P ₃ and N ₃ are both turned on and the output is in a high impedance state,
Now, if the input IN is at a low level, both PMOS transistors P ₁ and P ₂ are turned on, so the power supply V _DD
−P ₂ −R ₂ −N ₃ −V Current flows in _{the SS} path. However, the resistor R ₂ has an appropriate impedance that can sufficiently suppress the rush current when both transistors P ₂ and N ₂ are turned on when the input IN is at an intermediate level between high and low levels. The current consumption is not that large.

On the other hand, similarly, the input IN is in a high impedance state.
If is at a high level, then the power supply V _DD −P ₃ −R ₁ −
A current of N ₁ −V _SS flows through the impedance element R ₁
Therefore, current consumption can be sufficiently suppressed.

In this way, the existence of R ₁ and R ₂ simply means that
It has the function of preventing the PNP transistor T ₁ and the NPN transistor T ₂ from being turned on simultaneously, and also suppressing current consumption that would otherwise flow when the output is high impedance.

Another embodiment of the present invention shown in FIG. 4 is an example in which the current flowing when the output is at high impedance can be almost completely eliminated.

In addition to the embodiment shown in FIG. 1, this embodiment connects a fourth PMOS transistor P ₄ between the drain of PMOS transistor P ₂ and resistor R ₂ ,
4th NMOS transistor N ₄ with resistor R ₁ and NMOS
_Two drains of the transistor _N1 are connected, and an inverted signal of the control signal T _C is applied to the gate of the PMOS transistor _P4 , and a control signal is applied to the gate of the NMOS transistor _N4 .

In this embodiment, it is assumed that the enable signal _TC is at a low level and the output OUT is in a high impedance state. However, in this embodiment, both the PMOS transistor P ₄ and the NMOS transistor N ₄ are turned off, so that the current path formed in the embodiment of FIG. 1 is eliminated depending on the low level or high level of the input signal IN. It is possible.

(7) Effects of the Invention As described above, according to the present invention, a bipolar transistor is used in the output stage, a CMOS circuit is used in the previous stage, and the bipolar transistors, which have a large drive current, are simultaneously turned on during a transient and generate a large rush current. It is suitable for an output buffer gate because it prevents the current from flowing, reduces power consumption, and allows a large output current. Furthermore, it can be used as a 3-state gate buffer, and the current flowing inside the circuit can be kept small in the high-impedance state, and there is no extra power consumption due to 3-state operation. .

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
3 and 3 are characteristic diagrams showing the voltage transfer characteristics of the above embodiment of the present invention, and FIG. 4 is a circuit diagram showing another embodiment of the present invention. P ₁ , P ₂ , P ₃ , P ₄ ...PMOS transistor,
_N1 , _N2 , _N3 , _N4 ...NMOS transistor, _T1
...PNP transistor, _T2 ...NPN transistor, _R1 , _R2 ...Resistor, T _C ...Enable signal,
I...Inverter.

Claims (1)

[Claims] 1. A first P-type MIS transistor connected to the high-potential power supply side, a first N-type MIS transistor connected to the low-potential power supply side, and a first transistor provided between the two transistors. 1 impedance element,
a first complementary MIS gate circuit that commonly receives an input signal to the gates of the first P-type and N-type MIS transistors; a second P-type MIS transistor connected to the high potential power supply side; and a low potential power supply. the second N connected to the side
a second complementary MIS gate, comprising a type MIS transistor and a second impedance element provided between the two transistors, and receiving an input signal in common at the gates of the second P-type and N-type MIS transistors; a pull-up bipolar transistor whose base is connected to a connection point between the first P-type MIS transistor and the first impedance element; and a pull-up bipolar transistor whose base is connected to the second N-type MIS transistor and the second impedance element. a pull-down bipolar transistor connected to the connection point, the pull-up bipolar transistor and the pull-down bipolar transistor being separately and independently controlled by the first impedance element and the second impedance element, A bipolar circuit whose output terminal is the connection point of the bipolar transistor, and a third P-type MIS connected between a high potential power supply and the base of the pull-up bipolar transistor.
transistor, and a third N-type MIS transistor connected between a low potential power source and the base of the pull-down bipolar transistor, and the gates of the third P-type and N-type MIS transistors each have an enable signal and its inversion. Complementary BiMIS 3-state circuit characterized by the addition of signals. 2 The first impedance element and the first N-type
A fourth N-type MIS transistor is interposed and connected between the MIS transistor, and a fourth P-type MIS transistor is interposed and connected between the second impedance element and the second P-type MIS transistor. 2. The complementary BiMIS three-state circuit according to claim 1, wherein said enable signal and its inverted signal are applied to the gates of said fourth N-type and P-type MIS transistors, respectively.