JP3227966B2 - Bootstrap circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bootstrap circuit, and more particularly to a complementary metal oxide semiconductor (CMOS).
and a bootstrap circuit for an integrated circuit.

[0002]

2. Description of the Related Art CMOS (Complementary Metal Oxide)
In a bootstrap circuit used in an integrated circuit, the back gate bias is set to, for example, a negative potential so that the threshold voltage of the MOS transistor increases and the output dynamic range does not appear. To be raised.

Specifically, for example, an N-well type CMOS having an N-type region (hereinafter referred to as an N-well) formed on a P-type substrate
As shown in FIG. 3, the bootstrap circuit used in the first embodiment includes a drive transistor 52 that changes the potential of a drive signal line 51 and a control transistor 53 that controls the gate of the drive transistor 52 according to a change in an input signal.
A capacitor 54 for raising the potential of the drive signal line 51 to a predetermined potential or higher; and a precharge transistor 55 for applying a predetermined potential to the gate of the drive transistor 52 in advance.

Assuming that the power supply voltage (V _CC ) of the CMOS is 5 volts, 5 volts are supplied to the gate of the control transistor 53 and the drain of a precharge transistor (hereinafter referred to as a precharge transistor) 55. As will be described later, the potential (V _BB ) of the back gate bias (N well) of the control transistor 53, the capacitor 54, and the precharge transistor 55 is set to -3 volts.

The input signal inverted by the inverter circuit 61 is supplied to the source of the driving transistor 52,
The inverter transistor 61, 62, 63, 64 and the capacitor 6 connected in cascade are connected to the source of the control transistor 53.
At 5, an input signal delayed by a predetermined time t is supplied. On the other hand, an input signal delayed by a predetermined time t and inverted by an inverter circuit 66 is supplied to a terminal 54 a connecting the source and the drain of the capacitor 54, and an input signal is supplied to a gate of the precharge transistor 55. The input signal is supplied to the gate of an output transistor 56 constituting a so-called push-pull circuit which is an output buffer circuit, and the drive signal line 51 is connected to the gate of the output transistor 57 of the push-pull circuit. Further, a transistor 67 driven by an input signal is connected between the drive signal line 51 and the ground via a transistor 68 which is always on.

Therefore, in this bootstrap circuit,
Indicates that the voltage of the input signal is V, as shown in FIG. 4A._CCbolt
In the state shown in FIG._CCBol
Supply of the control transistor 53
Is off, and the gate of the precharge transistor 55 is
V_CCThe bolt is supplied,
Charge transistor 55 is in the ON state,
As shown in FIG. 4B, the gate voltage of the
(V_CC-V_TH) Bolts. Where V _THIs
This is a so-called threshold voltage of the recharge transistor 55.

An inverted input signal (0 volt) is supplied to the source of the driving transistor 52 via an inverter circuit 61. The driving transistor 52 is in an ON state and a transistor to which the input signal is supplied. 67 is an ON state. Therefore, the voltage of the drive signal line 51, which is the output of the drive transistor 52, is
As shown in FIG. As a result, the output transistor 56 is on, and the output transistor 5
7 is an off state. That is, the output voltage is 0 volt, as shown in FIG. 4D. In this state, the inverter circuit 66 is connected to the terminal 54a of the capacitor 54.
, And 0 volt is supplied to a terminal 54b which is a gate.
Are in a state where no charge is accumulated.

Next, as shown in FIG. 4A, when the voltage of the input signal changes from V _CC volts to 0 volts, the output transistor 56 and the transistor 67 change to the off state, and the source voltage of the driving transistor 52 becomes zero. It changes from volts to _Vcc volts. At this time, the precharge transistor 55 changes to the off state, and the control transistor 53 maintains the off state for a predetermined time t determined by the capacitor 65 and the like.

Therefore, the gate of the driving transistor 52 is in a floating state for a predetermined time t, so that the gate voltage of the driving transistor 52 becomes (V _CC −) as shown in FIG. V _TH ) or more, and the drive transistor 52 maintains the on state for a predetermined time. As a result, the capacitor 54 is charged via the drive transistor 52.

After a lapse of a predetermined time t, the control transistor 53 changes to the ON state, the gate voltage of the drive transistor 52 becomes 0 volt, and the drive transistor 52 changes to the OFF state. As a result, the drive signal line 51 changes to a floating state. At this time, the _Vcc volt is supplied to the terminal 54a of the capacitor 54, and as shown in FIG.
_CC volts and the voltage obtained by adding the predetermined voltage alpha volts charged within a predetermined time t (V _CC + α) V a drive signal line 51
Is applied.

As a result, the output transistor 57 changes to the ON state, and the output voltage becomes V _{CC as} shown in FIG. 4D.
Change to bolts. That is, when the output transistor 57 is turned on, the voltage applied to the gate of the output transistor 57 is increased by α volts to activate the bootst, thereby shortening the turn-on time of the output transistor 57 (steep rise).

By the way, the Bootst effect, that is, α volt, is determined by the capacitance of the capacitor 54 and its charging current. If the capacitance of the capacitor 54 is the same, the admittance of the drive transistor 52 in the ON state within a predetermined time t. The smaller is the higher. In other words, the higher the gate voltage (V _cc −V _TH ) for maintaining the drive transistor 52 in the on state for the predetermined time t, the higher the Boost effect. Therefore, in this conventional bootstrap circuit, the potential (V well) of the back gate bias (N well) of the control transistor 53, the capacitor 54, and the precharge transistor 55 is prevented in order to prevent the threshold voltage V _TH from increasing due to the _body effect. _BB ) is -3 volts.

[0013]

As described above, the conventional N
The bootstrap circuit used in the well-type CMOS has a problem that a power supply for setting the back gate bias to a negative potential is required.

On the other hand, when the bootstrap circuit having the above-described circuit configuration is used in a P-well type CMOS, the back gate bias becomes 0 volt, the threshold voltage V _TH rises due to the effect of the substrate effect, and the bootst effect decreases. was there.

The present invention has been made in view of such circumstances, and has a back gate bias (P-well) of 0.
It is an object of the present invention to provide a bootstrap circuit having a high bootst effect in a volt P-well type CMOS.

[0016]

In order to solve the above-mentioned problems, the present invention provides a drive transistor for changing the potential of a drive signal line, and a control for controlling a gate of the drive transistor according to a change in an input signal. A control transistor comprising an N-channel transistor formed in a P-well, and using the back gate bias as a source potential, wherein the potential of the drive signal line is set to a predetermined potential or more. A lifting capacitor is provided, wherein the capacitor comprises an N-channel transistor formed in a P-well, and the back gate bias is used as a source potential.

Further, the bootstrap circuit according to the present invention includes an N-channel transistor having a precharge transistor for applying a predetermined potential to the gate of the drive transistor in advance, wherein the precharge transistor is formed in a P well. And the back gate bias is used as the source potential.

[0018]

[0019]

[0020]

According to the present invention, a drive transistor for changing the potential of the drive signal line and a control transistor for controlling the gate of the drive transistor in accordance with a change in the input signal are provided. The control transistor is formed in a P-well. In a bootstrap circuit having a back gate bias as a source potential, a capacitor that raises the potential of a drive signal line to a predetermined potential or more is an N-channel transistor formed in a P-well, The back gate bias is used as the source potential.

Further, in the bootstrap circuit according to the present invention, the precharging transistor for applying a predetermined potential to the gate of the driving transistor in advance is an N-channel transistor formed in a P well, and the back gate bias is applied to the source. Potential.

Further, in the bootstrap circuit according to the present invention, the precharging transistor for applying a predetermined potential to the gate of the driving transistor in advance is an N-channel transistor formed in a P well, and the back gate bias is applied to the source. Potential.

In the bootstrap circuit according to the present invention, the capacitor for raising the potential of the drive signal line to a predetermined potential or higher is an N-channel transistor formed in a P-well, and the back gate bias is used as the source potential. .

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a bootstrap circuit according to the present invention will be described below with reference to the drawings. This example is
The bootstrap circuit according to the present invention is applied to a P-well type CMOS having a back gate bias of 0 V. FIG. 1 is a block diagram showing a configuration of a so-called push-pull type driving circuit composed of the P-well type CMOS. FIG.

As shown in FIG. 1, the driving circuit includes a driving transistor 12 for changing the potential of the driving signal line 11.
And the drive transistor 12 according to a change in the input signal.
And a capacitor 14 for raising the potential of the drive signal line 11 to a predetermined potential or higher, and a precharge transistor 15 for applying a predetermined potential to the gate of the drive transistor 12 in advance. A bootstrap circuit is provided. The drive circuit also includes output transistors 16 and 17 cascaded between a power supply and ground as an output buffer.

Assuming that the power supply voltage (V _CC ) of this drive circuit is 5 volts, 5 volts are supplied to the gate of the control transistor 13 and the drain of a precharge transistor (hereinafter referred to as a precharge transistor) 15. The back gates (N wells) of the control transistor 13, the capacitor 14, and the precharge transistor 15 are connected to the sources of the respective transistors, and the respective back gate biases are set to the respective source potentials.

Then, the input signal inverted by the inverter circuit 21 is supplied to the source of the drive transistor 12, and
The cascade-connected inverter circuits 21, 22, 23, 24 and the capacitor 2 are connected to the source of the control transistor 13.
At 5, an input signal delayed by a predetermined time is supplied.
On the other hand, the input signal delayed by a predetermined time and inverted by the inverter circuit 26 is supplied to the terminal 14 a connecting the source and the drain of the capacitor 14, and the input signal is supplied to the gate of the precharge transistor 15. The input signal is supplied to the gate of the output transistor 16, and the drive signal line 11 is connected to the gate of the output transistor 17. Further, a transistor 27 driven by an input signal is connected between the drive signal line 11 and the ground via a transistor 28 which is always on.

Therefore, in this bootstrap circuit, when the voltage of the input signal is at V _CC volts, V _CC volts is supplied to the source of the control transistor 13 so that the control transistor 13 is in the off state, When the _Vcc volt is supplied to the gate of the charge transistor 15, this precharge transistor 1
Reference _numeral 5 denotes an ON state, and the voltage of the gate of the driving transistor 12 is (V _CC -V _TH ) volts. here,
V _TH is a so-called threshold voltage of the precharge transistor 15.

The inverted input signal (0 volt) is supplied to the source of the driving transistor 12 via the inverter circuit 21. The driving transistor 12 is in an on state and the transistor to which the input signal is supplied. 27 is an ON state. Therefore, the voltage of the drive signal line 11, which is the output of the drive transistor 12, is 0 volt. As a result, the output transistor 16 is on, and the output transistor 17 is off. That is, the output voltage is 0 volt. In this state, 0 volt is supplied to the terminal 14a of the capacitor 14 via the inverter circuit 26, and 0 volt is supplied to the terminal 14b, which is a gate. There is no state.

Next, the voltage of the input signal is changed from V _CC volts to 0.
If changes to the bolt, the output transistor 16 and the transistor 27 is thereby changed to the OFF state, the source voltage of the driving transistor 12 changes to V _CC volts 0 volts. At this time, the precharge transistor 15
Is turned off, and the control transistor 13
Maintain the off state for a predetermined time determined by the above-described capacitor 25 and the like.

Therefore, the gate of the driving transistor 12 is in a so-called floating state for a predetermined time, and the gate voltage of the driving transistor 12 rises to (V _CC -V _TH ) volts or more due to the capacitance between the source and the gate of the driving transistor 12. The drive transistor 12 maintains the ON state for a predetermined time. As a result, the capacitor 14 is charged via the drive transistor 12.

Thereafter, when a predetermined time elapses, the control transistor 13 changes to the ON state, and the drive transistor 1
2 has a gate voltage of 0 volts, and the driving transistor 12 changes to the off state. As a result, the drive signal line 1
1 changes to a floating state. At this time,
The terminal 14a of the capacitor 14 is supplied with V _CC volts. The capacitor 14 adds a voltage (V _CC +) obtained by adding V _CC volts and a predetermined voltage α volt charged within a predetermined time.
α) Volts are applied to the drive signal line 11.

As a result, the output transistor 17 changes to the ON state, and the output voltage changes to V _CC volts. That is, when the output transistor 17 is turned on, the voltage applied to the gate of the output transistor 17 is increased by α volts to activate the bootst, thereby shortening the turn-on time of the output transistor 17 (steep rise).

By the way, the Bootst effect, that is, α volt, is determined by the capacitance of the capacitor 14 and its charging current. If the capacitance of the capacitor 14 is the same, the admittance of the drive transistor 12 in the ON state within a predetermined time is determined. Smaller is higher. In other words, the higher the gate voltage (V _cc −V _TH ) that keeps the drive transistor 12 in the ON state for a predetermined time, the higher the Bootst effect. Therefore, in this bootstrap circuit,
The potential (V) of the back gate bias (N well) of the control transistor 13 and the precharge transistor 15 is
_By setting _BB ) as the source potential of each transistor, the body effect can be suppressed, and the threshold voltage V _TH can be reduced as compared with the case where the back gate is not connected to the source. Voltage (V _CC
−V _TH ) can be increased, and the Bootst effect can be enhanced. Further, by setting the back gate bias of the capacitor 14 to the source potential, the substrate effect can be suppressed, the efficiency of the capacitor 14 can be increased as compared with the case where the back gate is not connected to the source, and the Bootst effect can be enhanced. be able to.

Next, an embodiment in which the bootstrap circuit according to the present invention is applied to a row decoder of a DRAM will be described with reference to FIG. This decoder, as shown in FIG. 2, includes a drive transistor 32 that changes the potential of a drive signal line 31 and a control transistor 33 that controls the gate of the drive transistor 32 according to a change in an input signal. Multiple strap circuits,
For example, as shown in FIG. Since these bootstrap circuits have the same circuit configuration, one bootstrap circuit will be described.

Assuming that the power supply voltage (V _CC ) of the decoder is 5 volts, 5 volts is supplied to the gate of the control transistor 33. The back gate (N well) of the control transistor 33 is connected to the source, and the back gate bias is set to the source potential.

As shown in FIG. 2, the decoder includes a three-input NAND circuit 41 for obtaining a negative logical product of, for example, three selector signals, and the three-input NAND circuit 41.
An inverter circuit 42 for inverting the output of the inverter transistor 42 and supplying the inverted output to the source of the drive transistor 32;
And a transistor 44 driven by the output of the inverter circuit 43 between the drive signal line 31 and the ground. Then, an input signal is supplied to the source of the drive transistor 32.

Therefore, in this bootstrap circuit, when the voltages of the three selector signals are all at V _CC volts, V _CC volts is supplied to the source of the control transistor 33, so that the control transistor 33 is turned off. The gate of the drive transistor 32 is in a floating state and is in an on state. When 0 volt is supplied to the transistor 44,
This transistor 44 is off. As a result, the input signal (0 volt) supplied to the source of the driving transistor 32 is output as it is. In this case, for example, when the input signal is changed to V _CC volts 0 volts, the gate voltage of the driving transistor 32 by the capacitance between the source and the gate of the driving transistor 32 rises, for example, the charging of the capacitor in the subsequent stage of the load circuit Speed up. That is, it is possible to shorten the rise time of the output voltage (to make the rise steep) by using the bootst. By the way, in this decoder, the substrate effect is suppressed by setting the potential (V _BB ) of the back gate bias (N well) of the control transistor 33 as the source potential as described above, and the back gate is not connected to the source. The substrate effect is suppressed as compared with the above, and the Bootst effect can be enhanced as in the above-described embodiment.

When any one of the selector signals is 0 volt, the transistor 44 is on, and the potential of the drive signal line 31 is 0 volt.

[0040]

As is apparent from the above description, according to the present invention, the back gate bias of the control transistor and the precharge transistor is set to the source potential of each transistor, thereby suppressing the substrate effect, The threshold voltage V is lower than when the gate is not connected to the source.
_TH can be reduced, that is, the gate voltage of the driving transistor can be increased, and the Bootst effect can be enhanced.

By setting the back gate bias of the capacitor to the source potential, the substrate effect can be suppressed.
The efficiency of the capacitor can be increased as compared with the case where the back gate is not connected to the source, and the Bootst effect can be enhanced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a specific circuit configuration of a drive circuit using a bootstrap circuit according to the present invention.

FIG. 2 shows a diagram of a D using a bootstrap circuit according to the present invention.
FIG. 3 is a block diagram illustrating a specific circuit configuration of a RAM decoder.

FIG. 3 is a block diagram showing a circuit configuration of a conventional bootstrap circuit.

FIG. 4 is a time chart for explaining an operation of a conventional bootstrap circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 11 drive signal line 12 drive transistor 13 control transistor 14 capacitor 15 precharge transistor 31 drive signal line 32 drive transistor 33 control transistor

Claims (2)

(57) [Claims] 1. A driving transistor for changing a potential of a driving signal line, and a control transistor for controlling a gate of the driving transistor in accordance with a change in an input signal, wherein the control transistor is formed in an N-well formed in a P-well. An N-channel type bootstrap circuit comprising a channel-type transistor and having a back gate bias as a source potential, comprising a capacitor for raising the potential of the drive signal line to a predetermined potential or more, wherein the capacitor is formed in a P-well. A bootstrap circuit comprising a transistor and having a back gate bias as a source potential. 2. A pre-charging transistor for applying a predetermined potential to a gate of the driving transistor in advance,
2. The bootstrap circuit according to claim 1, wherein said precharging transistor is an N-channel transistor formed in a P-well, and a back gate bias thereof is used as a source potential.