JP2673891B2 - Driving circuit for electrostatic induction thyristor - Google Patents

Description

The present invention relates to a drive circuit for an electrostatic induction thyristor (hereinafter referred to as SI thyristor), and more particularly to a drive circuit for a double gate SI thyristor.

SI thyristors have a wide range of applications from high-voltage / high-current power conversion such as DC power transmission to relatively small power control such as small power supply devices, but the present invention has been complicated in the past.
The drive circuit of the thyristor simplifies and increases the utility value of the SI thyristor.

(Prior Art) A SI thyristor is a latch-up type switching element, which is driven by inputting a positive / negative trigger pulse and a quench pulse to a gate, and an example thereof is shown in FIG. .

The circuit shown in FIG. 5 will be described. The SI thyristor used here is a normally-off type. As described above, the SI thyristor operates by the positive / negative trigger pulse and the quench pulse, but in FIG. 5 (a), the p-channel MOS transistor 52, the positive bias power supply 54, the n-channel MOS transistor 53 and the negative pulse are supplied. The buffer circuit composed of the bias power supply 55 is operated by inputting the trigger pulse φ _ON and the quench pulse φ _OFF , respectively. Trigger pulse phi _ON and quenched pulse phi _OFF is inputted at the timing shown in (b). Further, a resistor 57 is inserted between the buffer circuit and the gate of the SI thyristor in order to limit the current flowing into the gate of the SI thyristor. Capacitance 56 is a speed-up capacitor. The diode 58 is provided so that the current from the gate at the time of turn-off is not limited by the resistor 57.

(Problems to be Solved by the Invention) In the circuit of FIG. 5 which operates the SI thyristor by triggering and quenching, high-speed switching is realized by optimizing the values of the gate resistor 57 and the speed-up capacitor 56. In other words, it has a high degree of freedom, so it is a circuit that can maximize the capabilities of SI thyristors.

However, there are problems that two positive and negative power supplies are required, the control circuit for generating the trigger pulse and the quench pulse is complicated, and the number of parts for the buffer is large.

(Means for Solving the Problem) The SI thyristor controls conduction and interruption by changing the potential distribution of the channel portion near the cathode with the gate voltage. The normally-off type SI thyristor has a high potential barrier against the electrons of the cathode in the channel only by the diffusion potential of the gate and the cathode, and the gate bias is 0.
Is shut off. If a slight potential corresponding to the diffusion potential between the gate and the cathode is given to the gate,
The SI thyristor latches up and becomes conductive.
Further, in order to return the conductive state to the cutoff state, it is sufficient to set the gate to the same potential as the cathode and restore the diffusion potential. This creates a potential barrier in the channel sandwiched by the gates, which is the main current path. At this time, a diffusion potential creates a potential barrier in the channel. At this turn-off, the hole that was flowing from the gate into the channel is pulled out,
If the voltage drop due to the gate resistance of this hole current is not made sufficiently small, the SI thyristor will remain conductive with this slight voltage drop. Since the gate resistance of the SI thyristor itself is sufficiently small, this state occurs only by the external drive circuit. Therefore, in the circuit of FIG.
Avoided by 58.

The SI thyristor drive circuit of the present invention is an invention invented as a means for solving the above-mentioned problems by utilizing the characteristics of the normally-off type SI thyristor.

Hereinafter, the principle of the present invention will be described with reference to FIG.

In FIG. 1 (a), 1 is a normally-off type SI thyristor, a capacitor 2 is connected to its gate, and a semiconductor switch element 3 is connected between the gate and the cathode. The control terminal 4 of the switch element 3 is controlled by a pulse φ _G , and this φ _G is an input pulse to the capacitor 2. The waveform of the pulse φ _G is shown in (b).

At a potential of the pulse phi _G is V _off when the period T ₁ in Fig. 1 (b), the semiconductor switching element 3 by the potential In the conductive state, SI thyristor 1 between the gate and the cathode is not at the same potential It is in the cutoff state. When the pulse φ _G changes from V _off to V _on at time t ₁ , the potential of the gate of the SI thyristor 1 rises due to capacitive coupling. At this time, the semiconductor switch element 3 is in the cutoff state at the potential V _{on of the} pulse φ _G.

As described above, the normally-off type SI thyristor shifts from the cutoff state to the conduction state when a slight voltage corresponding to the diffusion potential of the gate and the cathode is applied. At this time, the gate current is not required except for the amount required to charge the input capacitance viewed from the gate, and it is not necessary to pass a direct current.

During the period T _2, the SI thyristor 1 is in the conductive state. When the pulse φ _G changes from V _on to V _off at time t ₂ ,
The semiconductor switch element 3 is turned on again and the SI thyristor 1 is turned off.

As described above, the ON resistance of the semiconductor switch element 3 is selected to be small so that the gate is not forward biased by the voltage drop due to the gate current. In this way, the SI thyristor 1 is turned off again (time period T ₃ ).

Pulse phi _G level block the V _on the semiconductor switching element 3 state of, chosen so that V _off becomes conductive, and (V
_on −V _off ) is selected so that the gate of SI thyristor 1 can be triggered.

When V _on > V _off cannot be established depending _on the type of the semiconductor switching element 3, the pulse φ _G is divided into an on-pulse φ _GON and an off-pulse φ _GOFF , as shown in FIG. Input to control terminal 4.
φ _GON and φ _GOFF are pulses as shown in Fig. 1 (d),
The respective potentials are selected so that V ₂ −V ₁ is a potential difference that can trigger the gate of the SI thyristor 1 and V ₃ is a potential at which the semiconductor switching element 3 is in the cutoff state and V ₄ is at a conductive state.

(Operation) In the drive circuit of the SI thyristor shown in FIG. 1, based on the characteristics of the SI thyristor, without impairing its characteristics,
(1) The drive circuit can be simplified, (2) the drive circuit can be easily designed, (3) the number of components of the drive circuit can be reduced, (4) the control circuit can be simplified, and (5) gate loss can be reduced. It has the effect that it can be reduced.

It is not necessary to generate trigger pulse / quench pulse, which simplifies the control circuit.In particular, since the gate is blocked by the capacitor during the conduction period of the SI thyristor, and no direct current flows, the holding current does not flow and gate loss is reduced. There is no need to increase it.

Next, the drive circuit of the SI thyristor which is the premise of the present invention will be described with reference to FIGS. 2, 3 and 4.

FIG. 2A shows an example in which the semiconductor switch element 3 in FIG. 1A is a p-channel MOS transistor 31. The same numbers as in FIG. 1 are the same below. The potential of V _off of the pulse φ _G may be determined by the threshold voltage of the p-channel MOS transistor, and V _off may be 0 V in the case of a normally-on p-channel MOS transistor. Since the substrate of the p-channel MOS transistor is common to the cathode, the parasitic diode requires a rising voltage higher than the gate potential when the SI thyristor 1 is in the conductive state.

The relationship between the characteristics of the capacitor 2 (Cg) and the p-channel MOS transistor 31 and the switching characteristics of this drive circuit when a 1200V-5A class normally-off type SI thyristor 1 is used is explained below. Depending on the user's purpose, the value of capacitance 2 and p-channel MOS
The transistor 31 can be selected.

That is, if the normally-off type SI thyristor input impedance is simply considered to be in parallel with the resistor R and the capacitor C, then φ _G
When the rising edge of is given by a step function, the gate current Ig flowing into the gate at the rising edge of φ _G is as follows.

Ig = (Vg / R) · {Cg / (Cg + C)} · exp [-t / {(Cg + C) R}] where Vg is the threshold voltage of the p-channel MOS transistor and V _th (V _on -V _th ).

Therefore, by appropriately selecting Vg and Cg, the gate current required for turn-on can be passed for the period required for turn-on.

The gate current and its period required for this turn-on change depending on the anode voltage and the anode current.

FIGS. 7A to 7D show an example of changes in the turn-on area due to the difference in Cg. The upper right area of the curve in the figure is the turn-on area in each Cg. Further, although V _on is used as a parameter in the example of FIG. 7, the threshold voltage of the p-channel MOS transistor used is 0 to −1V.

The reason why the gate current required for turn-on and the period thereof vary depending on the anode voltage and the anode current is explained as follows.

The normally-off type SI thyristor is similar to the one in which the operation of a conventional thyristor with a pnpn structure is explained as connecting two bipolar transistors pnp and npn.
The bipolar transistor and the n-channel normally-off type SIT are described as being connected. The gate-open normally-off SI thyristor consists of these pnp bipolar transistors and n-channel normally-off SI thyristor.
It turns on when the sum of the current width ratios of T becomes 1 or more. The current amplification factor of the gate-open normally-off type SIT increases with the drain voltage, and also increases with the emitter current in the pnp bipolar transistor. That is, the current amplification factor of the gate-open normally-off SI thyristor changes depending on the anode voltage and the anode current. At the time of turn-on, the p-channel MOS transistor 31 connected to the gate of the normally-off type SI thyristor 1 is in the cutoff state, and only the capacitor 2 is connected to the gate. At this time, a direct current does not flow from the outside to the gate, so it may be considered that the gate is open. Therefore, the gate current required for turn-on and its period vary depending on the anode voltage and the anode current.

Next, the p-channel MOS transistor 31 will be described. The p-channel MOS transistor 31 is an example in which the switch 3 shown in FIG. 1A is realized by an electronic device. The major difference between the p-channel MOS transistor 31 and the switch 3 is that the p-channel MOS transistor 31 has a resistance R _on even when it is in a conductive state. Therefore, the gate current flowing at turn-off is limited by this resistor R _on . The gate of the normally-off type SI thyristor in the conductive state is at a certain potential V _{GK (on)} , but the maximum value of the gate current V _{GK (on)} / R _on cannot be exceeded.
R _on must be chosen so that the gate current required for turn-off is less than V _{GK (on)} / R _on . Moreover, when the gate current becomes smaller due to R _on , the time required for turn-off becomes longer.

FIGS. 8A to 8F show changes in turn-off time due to R _on . Again, t _f is the fall time of the anode voltage,
t _stg indicates the accumulation time. I _Goff is the maximum value of gate current. t _off is the time required for turn- _{off and} is defined by t _off = t _stg + t _f . In this example, R _on is required to be 1Ω or less.

2 (b) shows the substrate of the p-channel MOS transistor 32 of FIG. 2 (a) connected to the gate.
The same operation as in FIG.

FIG. 2 (c) shows the semiconductor switch element 3 of FIG. 1 (a).
Is an example in which SIT33 of p channel is used. If this p-channel SIT33 is normally on, V _{off of} pulse φ _G
0 may be 0, and if it is normally off, it may be set to a potential at which the SIT 33 becomes conductive. Similarly, V _on may be set to a potential at which the SIT 33 is in the cutoff state or higher and the SI thyristor 1 is triggered.

2 (d) is the semiconductor switch element 3 of FIG. 1 (a).
Is a PNP transistor 34. Since the bipolar transistor is a current control element, the base resistor 35 is provided. The potential of V _off of the pulse φ _G becomes a negative voltage with which the transistor 34 becomes conductive. V _on is set to 0 or a positive voltage because the transistor 34 is cut off and the SI thyristor is triggered.

FIG. 3 (a) is a semiconductor switch element 3 of FIG. 1 (a).
Is an n-channel MOS transistor 36. The substrate is connected to the cathode. If the rising voltage of the parasitic diode on the substrate is equal to or higher than the gate voltage when the SI thyristor 1 is in the conductive state, the substrate of the n-channel MOS transistor 37 may be connected to the gate as shown in FIG. 3 (b).

FIG. 3 (c) is the semiconductor switch element 3 of FIG. 1 (c).
Is an n-channel SIT38.

FIG. 3 (d) is a semiconductor switch element 3 of FIG. 1 (c).
Is an NPN transistor 39. Since the bipolar transistor is a current control element, the base resistor 40 is provided.

(Embodiment) FIG. 4 (a) shows a drive circuit for a double gate SI thyristor. The double gate SI thyristor p ⁺ -p ⁺ -n ^{- -}
consists of four-layer structure of n ^+, anode the p ⁺ layer and the n ⁺ layers, respectively, at the cathode, p ⁺ region of the first gate is said n ^- is formed in a layer, the n ⁺ region of the second gate It is provided in the p ^- layer. Therefore, normally-off type double gate
Even if a voltage is applied between the anode and the cathode in the SI thyristor, the SI thyristor is in the off state. Therefore, in order to turn it on, the p ⁺ region of the first gate, the n ⁻ layer of the SI thyristor, and the second A pulse is applied so that the junction between the n ⁺ region of the gate and the p ⁻ layer of the SI thyristor is in the forward direction, and conversely, in order to change from the ON state to the OFF state, the junction is zero or reverse. A pulse having a direction may be applied.

As shown in FIG. 4 (a), capacitors 21 and 22 are connected to the first gate G1 and the second gate G2 of the normally-off type double gate SI thyristor 11, respectively, and between the first gate G1 and the cathode K. Is an n-channel MOS transistor 3
01 is provided, and a p-channel MOS transistor 302 is connected between the second gate G2 and the anode.
In order to drive the normally-off type double gate SI thyristor 11, as shown in FIG.
Positive and negative pulses of φ _G1ON and φ _G2ON are simultaneously applied to the first gate G1 and the second gate G2 via 1, 22 to _bring the SI thyristor 11 into a conductive state. Next, φ _G1OFF and φ are applied to the gates of the p-channel MOS transistor 301 and the n-channel MOS transistor 302, _{respectively.}
The positive and negative _G2OFF pulses are simultaneously applied to turn on the MOS transistors 301 and 302 to turn off the SI thyristor 11.

(Effect of the Invention) FIG. 6 shows the switching characteristics of the 1200V, 5A class normally-off SI thyristor in the circuit of FIG. 2 (a). Capacitance 2 is Cg = 1000pF, p-channel MOS transistor 31 is R
_on = 0.85Ω, and the pulse φ _G has V _on = + 5V and V _off = −7V.

Here, t _r is the rising speed of the anode voltage at turn-on, t _d is the turn-on delay time, and t _on is the turn-on time, which is given by t _on = t _d + t _r . In addition, I _Gon indicates the maximum value of the gate current at turn-on.

Looking at the gate current, it can be seen that fast switching is performed with a value that is sufficiently smaller than the anode current.
It can be seen that the gate loss is reduced compared to the conventional drive circuit using the trigger / quench method. Furthermore, since the SI thyristor is turned on and off only at the transitional rise and fall of the gate pulse, there is the effect that the drive pulse is simplified.As mentioned above, the operating range was confirmed experimentally. ing.

The drive circuit of the SI thyristor according to the present invention is driven by insulation control, and the thyristor is turned on / off at the timing of the dynamic rising and falling portions of the gate pulse. Fig. 9 shows the waveform of each part of a typical SI thyristor. The gate current I _G is the trigger pulse current I _Gon
It can be seen that the gate drive power is small only with the quench pulse current I _Goff .

The capacitors 21 and 22 in FIG. 4 (a) may be MOS gate capacitors formed on the gate of the SI thyristor via an insulating layer. Similarly, pMOS transistors 31, 32, p-channel SIT33, n-channel SIT38, PNP transistor 3
4, NPN transistor 39, nMOS transistors 36, 37, 30
2, switching transistors such as pMOS transistor 301 may also be integrated on the same chip as the main SI thyristor, in which case isolation control (MOS-Controlled) SI
Should be called a thyristor.

The present invention is an invention relating to a drive circuit for an electrostatic induction thyristor by insulation control, which is a novel and simple operation circuit and is of high industrial value.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the present invention, FIGS. 2 and 3 are diagrams showing an example which is a premise of the present invention, FIG. 4 is a diagram showing an embodiment of the present invention, and FIG. 5 is a conventional technique. FIG. 6 is a diagram showing the effect of the invention, FIG. 7 is a diagram showing an example of the relationship between the capacitance 2 and turn-on characteristics, and FIG. 8 is a p-channel MOS transistor 3
Figure 1 shows an example of the relationship between 1 and turn-off characteristics. Figure 9 shows SI.
It is a figure which shows the typical operation waveform of each part at the time of driving a thyristor. 1 ... Normally off type SI thyristor, 2 ... Capacity, 3 ...
… Semiconductor switch element, 4 …… Control terminal of semiconductor switch element, 11 …… Normally off type double gate SI thyristor, G1 …… First gate, G2 …… Second gate, 301 …… n
Channel MOS transistor, 302 ... p channel MOS
Transistor, 21, 22 ... Capacity, φ _G1ON …… positive pulse, φ _G1OFF …… positive pulse, φ _G2ON …… negative pulse,
φ _G2OFF …… Negative pulse

Claims (1)

(57) [Claims] 1. A normally-off type electrostatic induction thyristor having an anode terminal, a cathode terminal, and first and second gate terminals, one end of which is connected to a first input terminal and the other end of which is the first gate. A first capacitive element connected to the terminal, a second capacitive element having one end connected to the second input terminal and the other end connected to the second gate terminal, and a third input terminal A control electrode connected to the first
A first semiconductor switch element connected between the gate terminal and the cathode terminal, and a control electrode connected to a fourth input terminal,
Second semiconductor switch element connected between the gate terminal and the anode terminal of the normally-off static induction thyristor by applying a pulse signal to the first and second input terminals at the same time. A pulse signal is simultaneously applied to the third and fourth input terminals to make the first and second semiconductor switch elements conductive, and the normally-off static induction thyristor is cut off. Driving circuit for electrostatic induction thyristor.